Revised January 1999 MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop General Description The MM74C373 and MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with 3STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again. The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on positive-going transitions of the CLOCK input. Both the MM74C373 and the MM74C374 are being assembled in 20-pin dual-in-line packages with 0.300” pin centers. Features ■ Wide supply voltage range: ■ High noise immunity: 3V to 15V 0.45 VCC (typ.) ■ Low power consumption ■ TTL compatibility: Fan out of 1driving standard TTL ■ Bus driving capability ■ 3-STATE outputs ■ Eight storage elements in one package ■ Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs ■ 20-pin dual-in-line package with 0.300” centers takes half the board space of a 24-pin package Ordering Code: Order Number MM74C373M Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C374M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS005906.prf www.fairchildsemi.com MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop October 1987 MM74C373 • MM74C374 Connection Diagrams Pin Assignments for DIP and SOIC MM74C373 MM74C374 Top View Top View MM74C373 MM74C374 Truth Tables Output LATCH Disable ENABLE D L H L H L L H X X Hi-Z H Q Clock D Q H H H L L L L L L X Q L L X Q L H X Q H X X Hi-Z L = LOW logic level H = HIGH logic level X = Irrelevant = LOW-to-HIGH logic level transition Q = Preexisting output level Hi-Z = High impedance output state www.fairchildsemi.com Output Disable 2 MM74C373 • MM74C374 Block Diagrams MM74C373 (1 of 8 Latches) MM74C374 (1 of 8 Flip-Flops) 3 www.fairchildsemi.com MM74C373 • MM74C374 Absolute Maximum Ratings(Note 1) Operating VCC Range −0.3V to VCC + 0.3V Voltage at Any Pin (Soldering, 10 seconds) −40°C to +85°C Storage Temperature Range (TS) −65°C to +150°C 700 mW Small Outline 500 mW 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Power Dissipation Dual-In-Line 18V Lead Temperature (TL) Operating Temperature Range (TA) MM74C373 3V to 15V Absolute Maximum VCC DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 V VCC = 10V 8.0 V VCC = 5V 1.5 V VCC = 10V 2.0 V VCC = 5V, IO = −10 µA 4.5 VCC = 10V, IO = −10 µA 9.0 V V VCC = 5V, IO = 10 µA 0.5 VCC = 10V, IO = 10 µA 1.0 V 1.0 µA 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V IOZ 3-STATE Leakage Current VCC = 15V, VO = 15V ICC Supply Current VCC = 15V VCC = 15V, VO = 0V 0.005 −1.0 −0.005 0.005 −1.0 µA −0.005 0.05 V µA 300 µA 0.8 V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VOUT(1) Logical “1” Output Voltage VOUT(0) Logical “0” Output Voltage VCC − 1.5 VCC = 4.75V, IO = −360 µA VCC − 0.4 VCC = 4.75V, IO = −1.6 mA 2.4 V V V VCC = 4.75V, IO = 1.6 mA 0.4 V OUTPUT DRIVE (Short Circuit Current) ISOURCE Output Source Current VCC = 5V, VOUT = 0V −12 −24 mA −24 −48 mA 6 12 mA 24 48 mA TA = 25°C (Note 2) ISOURCE Output Source Current VCC = 10V, VOUT = 0V TA = 25°C (Note 2) ISINK ISINK Output Sink Current VCC = 5V, VOUT = VCC (N-Channel) TA = 25°C (Note 2) Output Sink Current VCC = 10V, VOUT = VCC (N-Channel) TA = 25°C (Note 2) Note 2: These are peak output current capabilities. Continuous output current is rated at 12 mA max. www.fairchildsemi.com 4 (Note 3) MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted Symbol tpd0, tpd1 tpd0, tpd1 tSET-UP Typ Max Units Propagation Delay, Parameter VCC = 5V, CL = 50 pF 165 330 ns LATCH ENABLE to Output VCC = 10V, CL = 50 pF 70 140 ns VCC = 5V, CL = 150 pF 195 390 ns VCC = 10V, CL = 150 pF 85 170 ns LATCH ENABLE = VCC In to Output VCC = 5V, CL = 50 pF 155 310 ns VCC = 10V, CL = 50 pF 70 140 ns VCC = 5V, CL = 150 pF 185 370 ns VCC = 10V, CL = 150 pF 85 170 ns VCC = 5V 70 140 ns VCC = 10V 35 70 ns Minimum Set-Up Time Data In tr , tf t1H, t0H tH1, tH0 tTHL, tTLH tHOLD = 0 ns Maximum LATCH ENABLE Frequency tPWH Min Propagation Delay Data to CLOCK/LATCH ENABLE fMAX Conditions VCC = 5V 3.5 6.7 VCC = 10V 4.5 9.0 MHz MHz Minimum LATCH ENABLE VCC 5V 75 150 Pulse Width VCC = 10V 55 110 Maximum LATCH ENABLE VCC = 5V NA µs Rise and Fall Time VCC = 10V NA µs Propagation Delay OUTPUT RL = 10k, CL = 5 pF DISABLE to High Impedance VCC = 5V 105 210 ns State (from a Logic Level) VCC = 10V 60 120 ns Propagation Delay OUTPUT RL = 10k, CL = 50 pF DISABLE to Logic Level VCC = 5V 105 210 ns (from High Impedance State) VCC = 10V 45 90 ns Transition Time VCC = 5V, CL = 50 pF 65 130 ns VCC = 10V, CL = 50 pF 35 70 ns VCC = 5V, CL = 150 pF 110 220 ns VCC = 10V, CL = 150 pF 70 140 ns LE Input (Note 4) 7.5 10 pF OUTPUT DISABLE 7.5 10 pF CLE Input Capacitance COD Input Capacitance ns ns Input (Note 4) CIN Input Capacitance Any Other Input (Note 4) 5 7.5 pF COUT Output Capacitance High Impedance 10 15 pF CPD Power Dissipation Capacitance State (Note 4) Per Package (Note 5) 200 pF Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. 5 www.fairchildsemi.com MM74C373 • MM74C374 AC Electrical Characteristics MM74C373 • MM74C374 AC Electrical Characteristics (Note 6) MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted Symbol tpd0, tpd1 tSET-UP tPWH, tPWL Typ Max Units Propagation Delay, Parameter VCC = 5V, CL = 50 pF Conditions Min 150 300 ns CLOCK to Output VCC = 10V, CL = 50 pF 65 130 ns VCC = 5V, CL = 150 pF 180 360 ns VCC = 10V, CL = 150 pF 80 160 ns Minimum Set-Up Time Data In tHOLD = 0 ns to CLOCK/LATCH ENABLE VCC = 5V 70 140 ns VCC = 10V 35 70 ns VCC = 5V 70 140 ns VCC = 10V 50 100 Minimum CLOCK Pulse Width ns VCC = 5V 3.5 7.0 MHz VCC = 10V 5 10 MHz fMAX Maximum CLOCK Frequency t1H, t0H Propagation Delay OUTPUT RL = 10k, CL = 50 pF DISABLE to High Impedance VCC = 5V 105 210 ns State (from a Logic Level) VCC = 10V 60 120 ns tH1, tH0 tTHL, tTLH tr, tf Propagation Delay OUTPUT RL = 10k, CL = 50 pF DISABLE to Logic Level VCC = 5V 105 210 ns (from High Impedance State) VCC = 10V 45 90 ns Transition Time VCC = 5V, CL = 50 pF 65 130 ns VCC = 10V, CL = 50 pF 35 70 ns VCC = 5V, CL = 150 pF 110 220 ns VCC = 10V, CL = 150 pF 70 140 Maximum CLOCK Rise VCC = 5V 15 >2000 5 >2000 ns µs and Fall Time VCC = 10V CCLK Input Capacitance CLOCK Input (Note 7) 7.5 10 pF µs COD Input Capacitance OUTPUT DISABLE 7.5 10 pF Input (Note 7) CIN Input Capacitance Any Other Input (Note 7) 5 7.5 pF COUT Output Capacitance High Impedance 10 15 pF State (Note 7) CPD Power Dissipation Capacitance Per Package (Note 8) 250 pF Note 6: AC Parameters are guaranteed by DC correlated testing. Note 7: Capacitance is guaranteed by periodic testing. Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. www.fairchildsemi.com 6 MM74C373, MM74C374 Change in Propagation Delay per pF of Load Capacitance (∆tPD/pF) vs Power Supply Voltage MM74C373 Propagation Delay, LATCH ENABLE to Output vs Load Capacitance MM74C373 Propagation Delay, Data In to Output vs Load Capacitance MM74C373, MM74C374 Output Sink Current vs VOUT MM74C373 Propagation Delay, CLOCK to Output vs Load Capacitance MM74C373, MM74C374 Source Current vs VCC − VOUT 7 www.fairchildsemi.com MM74C373 • MM74C374 Typical Performance Characteristics MM74C373 • MM74C374 Typical Applications Data Bus Interfacing Element Simple, Latching, Octal, LED Indicator Driver with Blanking for Use as Data Display, Bus Monitor, µP Front Panel Display, Etc. 3-STATE Test Circuits and Switching Time Waveforms t1H, tH1 t0H , tH0 t1H, CL = 5 pF t0H, CL = 5 pF tH1, CL = 50 pF www.fairchildsemi.com tH0, CL = 50 pF 8 MM74C373 • MM74C374 Switching Time Waveforms MM74C373 Output Disable = GND MM74C374 Output Disable = GND 9 www.fairchildsemi.com MM74C373 • MM74C374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013. 0.300” Wide Package Number M20B www.fairchildsemi.com 10 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued)