FAIRCHILD MM74HC161SJ

Revised February 1999
MM74HC161 • MM74HC163
Synchronous Binary Counter with Asynchronous Clear
• Synchronous Binary Counter with Synchronous Clear
General Description
The MM74HC161 and MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high
speed counting applications. They offer the high noise
immunity and low power consumption inherent to CMOS
with speeds similar to low power Schottky TTL. The HC161
and the HC163 are 4 bit binary counters. All flip-flops are
clocked simultaneously on the LOW-to-HIGH transition
(positive edge) of the CLOCK input waveform.
These counters may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held LOW counting is disabled
and the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken HIGH before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the
CLEAR input. The clear function on the MM74HC163
counter is synchronous to the clock. That is, the counters
are cleared on the positive edge of CLOCK while the clear
input is held LOW.
The MM74HC161 counter is cleared asynchronously.
When the CLEAR is taken LOW the counter is cleared
immediately regardless of the CLOCK.
Two active HIGH enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be HIGH to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the HIGH level portion of the QA output. The RC output is
fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■ Typical operating frequency: 40 MHz
■ Typical propagation delay; clock to Q: 18 ns
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ Wide power supply range: 2–6V
Ordering Code:
Order Number
MM74HC161M
MM74HC161SJ
MM74HC161MTC
MM74HC161N
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC163SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC163MTC
MM74HC163N
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS005008.prf
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MM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear • Synchronous Binary
Counter with Synchronous Clear
September 1983
MM74HC161 • MM74HC163
Connection Diagram
Truth Tables
MM74HC161
Pin Assignments for DIP, SOIC, SOP and TSSOP
CLK CLR ENP ENT
Load
Function
X
L
X
X
X
Clear
X
H
H
L
H
Count & RC disabled
X
H
L
H
H
Count disabled
X
H
L
L
H
Count & RC disabled
↑
H
X
X
L
Load
↑
H
H
H
H
Increment Counter
MM74HC163
CLK CLR ENP ENT
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2
Function
L
X
X
X
Clear
X
H
H
L
H
Count & RC disabled
X
H
L
H
H
Count disabled
X
H
L
L
H
Count & RC disabled
↑
H
X
X
L
Load
↑
H
H
H
H
Increment Counter
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
Logic Diagram
Load
↑
Recommended Operating
Conditions
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC+1.5V
DC Output Voltage (VOUT)
−0.5 to VCC+0.5V
±20 mA
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin
DC VCC or GND Current, per pin
V
DC Input or Output Voltage
0
VCC
V
−40
+85
°C
(tr, tf) VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature
(TL) (Soldering 10 seconds)
Symbol
VIH
VIL
VOH
Parameter
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
DC Electrical Characteristics
Conditions
Units
Input Rise or Fall Times
−65°C to +150°C
Storage Temperature Range (TSTG)
6
Operating Temperature Range (TA)
±50 mA
(ICC)
Max
2
(VIN, VOUT )
±25 mA
(IOUT)
Min
Supply Voltage (VCC)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
(Note 4)
TA=25°C
VCC
Typ
TA=−40 to 85°C TA=−55 to 125°C
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
1.5
Input Voltage
4.5V
3.15
3.15
3.15
V
V
6.0V
4.2
4.2
4.2
V
V
Maximum LOW Level
2.0V
0.5
0.5
0.5
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT| ≤ 4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT| ≤ 5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
VIN = V IH or VIL
IIN
|IOUT| ≤ 4.0 mA
4.5V
0.2
0.26
0.33
0.4
|IOUT| ≤ 5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
Maximum Quiescent
VIN = VCC or GND
6.0V
8.0
80
160
µA
Supply Current
IOUT = 0 µA
Maximum Input
Current
ICC
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC161 • MM74HC163
Absolute Maximum Ratings(Note 1)
(Note 2)
MM74HC161 • MM74HC163
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Typ
Guaranteed Limit
Units
fMAX
Symbol
Maximum Operating Frequency
Parameter
Conditions
43
30
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to RC
30
35
ns
tPHL, tPLH
Maximum Propagation Delay, Clock to Q
29
34
ns
tPHL, tPLH
Maximum Propagation Delay, ENT to RC
18
32
ns
tPHL
Maximum Propagation Delay, Clear to Q or RC
27
38
ns
tREM
Minimum Removal Time, Clear to Clock
10
20
ns
tS
Minimum Set Up Time Clear, Load,
30
ns
Enable or Data to Clock
tH
Minimum Hold Time, Data from Clock
5
ns
tW
Minimum Pulse Width Clock,
16
ns
Clear, or Load
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
fMAX
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tREM
tS
tS
Parameter
Conditions
VCC
TA=25°C
TA=−40 to 85°C TA=−55 to 125°C
Typ
Guaranteed Limits
Units
Maximum Operating
2.0V
10
5
4
4
MHz
Frequency
4.5V
40
27
21
18
MHz
6.0V
45
32
25
21
MHz
Maximum Propagation
2.0V
100
215
271
320
ns
Delay, Clock to RC
4.5V
32
43
54
64
ns
ns
6.0V
28
37
46
54
Maximum Propagation
2.0V
88
175
220
260
ns
Delay, Clock to RC
4.5V
18
35
44
52
ns
6.0V
15
30
37
44
ns
Maximum Propagation
2.0V
95
205
258
305
ns
Delay, Clock to Q
4.5V
30
41
52
61
ns
6.0V
26
35
44
52
ns
Maximum Propagation
2.0V
85
170
214
253
ns
Delay, Clock to Q
4.5V
17
34
43
51
ns
6.0V
14
29
36
43
ns
Maximum Propagation
2.0V
90
195
246
291
ns
Delay, ENT to RC
4.5V
28
39
49
58
ns
ns
6.0V
24
33
42
49
Maximum Propagation
2.0V
80
160
202
238
ns
Delay, ENT to RC
4.5V
16
32
40
48
ns
ns
6.0V
14
27
34
41
Maximum Propagation
2.0V
100
220
275
325
ns
Delay, Clear to RC
4.5V
32
44
55
66
ns
6.0V
28
37
47
55
ns
Maximum Propagation
2.0V
100
210
260
315
ns
Delay, Clear to Q
4.5V
32
42
52
63
ns
6.0V
28
36
45
54
ns
Minimum Removal
2.0V
125
158
186
ns
Time Clear to Clock
4.5V
25
32
37
ns
6.0V
21
27
32
ns
Minimum Setup
2.0V
150
190
225
ns
Time Clear or Data
4.5V
30
38
45
ns
ns
to Clock
6.0V
26
32
38
Minimum Setup
2.0V
135
170
200
ns
Time Load
4.5V
27
34
41
ns
to Clock
6.0V
23
29
35
ns
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4
Symbol
tS
tH
tH
tW
tTLH, tTHL
tr, tf
Parameter
(Continued)
Conditions
VCC
TA=25°C
Units
Guaranteed Limits
Minimum Setup
2.0V
175
220
260
ns
Time Enable
4.5V
35
44
52
ns
ns
to Clock
6.0V
30
37
44
Minimum Hold Time
2.0V
50
63
75
ns
Data from Clock
4.5V
10
13
15
ns
6.0V
9
11
13
ns
Minimum Hold Time
2.0V
0
0
0
ns
Enable, Load or Clear
4.5V
0
0
0
ns
to Clock
6.0V
0
0
0
ns
Minimum Pulse Width
2.0V
80
100
120
ns
Clock, Clear, or
4.5V
16
20
24
ns
Load
6.0V
14
17
20
ns
Maximum
2.0V
40
75
95
110
ns
Output Rise and
4.5V
8
15
19
22
ns
Fall Time
6.0V
7
13
16
19
ns
Maximum Input Rise
2.0V
1000
1000
1000
ns
and Fall Time
4.5V
500
500
500
ns
400
400
400
500
6.0V
CPD
TA=−40 to 85°C TA=−55 to 125°C
Typ
Powert Dissipation
(per package)
90
ns
pF
Capacitance (Note 5)
CIN
Maximum Input Capacitance
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
Logic Waveforms
Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit
5
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MM74HC161 • MM74HC163
AC Electrical Characteristics
MM74HC161 • MM74HC163
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
MM74HC161 • MM74HC163
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
7
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MM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear • Synchronous Binary
Counter with Synchronous Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.