MICRON MT49H32M9CFM-XX

16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
288Mb SIO REDUCED
LATENCY (RLDRAM II)
MT49H16M18C
MT49H32M9C
Features
Figure 1: 144-Ball FBGA
• 288Mb
• 400 MHz DDR operation (800 Mb/s/pin data rate)
• Organization
• 16 Meg x 18, 32 Meg x 9 Separate I/O
• 8 banks
• Cyclic bank switching for maximum bandwidth
• Reduced cycle time (20ns at 400 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Read latency (RL), row cycle time, and burst
sequence length
• Balanced READ and WRITE latencies in order to
optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-chip DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (8K refresh for each bank; 64k refresh
command must be issued in total each 32ms)
• 144-ball FBGA package
• HSTL I/O (1.5V or 1.8V nominal)
• 25Ω–60Ω matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT
Options
Valid Part Numbers
PART NUMBER
MT49H16M18CFM-xx
MT49H32M9CFM-xx
DESCRIPTION
16 Meg x 18 RLDRAM II
32 Meg x 9 RLDRAM II
Marking
• Clock Cycle Timing
2.5ns (400 MHz)
3.3ns (300 MHz)
5ns (200 MHz)
• Configuration
16 Meg x 18
32 Meg x 9
• Package
144-ball FBGA
(11mm x 18.5mm)
NOTE:
Table 1:
-25
-33
-5
MT49H16M18CFM
MT49H32M9CFM
FM
BM (lead-free)1
1. Contact Micron for availability of lead-free
products.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_1.fm - Rev. F 11/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Programmable Impedance Output Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Clock Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Mode Register Set Command (MRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Write Basic Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
AUTO REFRESH Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Operation with Multiplexed Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Refresh Command in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Disabling the JTAG Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Identification (ID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
HIGH-Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
CLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18CTOC.fm - Rev. F 11/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagram – 16 Meg x 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
16 Meg x 18 Ball Assignment (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
32 Meg x 9 Ball Assignment (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Clock/Input Data Clock Command/Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mode Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mode Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Basic WRITE Burst/DM Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write Burst Basic Sequence: BL = 2, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Write Burst Basic Sequence: BL = 4, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WRITE Followed By READ: BL = 2, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
WRITE Followed By READ: BL = 4, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ Burst: BL = 2, RL = 4, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ Burst: BL = 4, RL = 4, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ Followed by WRITE, BL = 2, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ followed by WRITE, BL = 4, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ/WRITE Interleave: BL = 4, tRC = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ/WRITE Interleave: BL = 4, tRC = 6, WL = 7, Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ/WRITE Interleave: BL = 4, tRC = 8, WL = 9, Configuration 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ Burst with ODT: BL = 2, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ NOP READ with ODT: BL = 2, Configuration 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
READ NOP NOP READ with ODT: BL = 2, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Command Description in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Mode Register Set Command in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Power-Up Sequence in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Burst Refresh Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE Burst Basic Sequence: BL = 4, with Multiplexed Addresses, Configuration 1, WL = 6 . . . . . .34
READ Burst Basic Sequence: BL = 4, with Multiplexed Addresses, Configuration 1, RL = 5. . . . . . . .34
TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
TAP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18CLOF.fm - Rev. F 11/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Valid Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Address Widths at Different Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Command Table1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
RLDRAM Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
On-Die Termination DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Address Mapping in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Configuration Table In Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
TAP AC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
TAP AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
AC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
IDD Operating Conditions and Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18CLOT.fm - Rev. F 11/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
General Description
is referenced to the free-running output data clock.
This architecture eliminates the need for high-speed
bus turnaround.
Commands, addresses, and control signals are registered at every positive edge of the differential input
clock, while input data is registered at both positive
and negative edges of the input data clock(s).
Read and write accesses to the RLDRAM are burstoriented. The burst length is programmable from 2, 4,
or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the
core and 1.5V or 1.8V for the output drivers.
Bank-scheduled refresh is supported with row
address generated internally.
A standard FBGA 144-ball package is used to enable
ultra high-speed data transfer rates and a simple
upgrade path from former products.
The Micron® 288Mb reduced latency DRAM
(RLDRAM) II is a high-speed memory device designed
for high bandwidth communication data storage.
Applications include, but are not limited to, transmitting or receiving buffers in telecommunication systems and data or instruction cache applications
requiring large amounts of memory. The chip's eightbank architecture is optimized for high speed and
achieves a peak bandwidth of 28.8 Gb/s, using two
separate 18-bit double data rate (DDR) parts and a
maximum system clock of 400 MHz.
The DDR separate I/O interface transfers two 18- or
9-bit wide data word per clock cycle at the I/O balls.
The read port has dedicated data outputs to support
READ operations, while the write port has dedicated
input balls to support WRITE operations. Output data
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 2: Functional Block Diagram – 16 Meg x 18
Column Decoder
Sense Amp and Data Bus
Bank 6
Output Buffers
Q0–Q17
D0–D17
Memory Array
Bank 7
Control Logic and Timing Generator
DM
Input Buffers
Column Decoder
Bank 5
Memory Array
Sense Amp and Data Bus
Memory Array
Row Decoder
VREF
Column Decoder
Bank 3
CS#
QK[1:0], QK#[1:0]
Memory Array
REF#
QVLD
Bank 2
WE#
Output Data Clock
Memory Array
DK
Output Data Valid
Row Decoder
Row Decoder
Column Decoder
Column Decoder
Memory Array
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Bank 1
Row Decoder
Row Decoder
Bank 4
Memory Array
Sense Amp and Data Bus
Bank 0
Column Decoder
Memory Array
Row Decoder
DK#
Row Decoder
Refresh
Counter
Row Address
Buffer
CK
Row Decoder
, B0, B1, B2
CK#
Column Address
Buffer
1, 2
Sense Amp and Data Bus
Column Address
Counter
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
A0–A19
NOTE:
1. When the BL = 8 setting is used, A18 and A19 are “Don’t Care.“
2. When BL = 4 setting is used, A19 is “Don’t Care.”
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 3: 16 Meg x 18 Ball Assignment (Top View) 144-Ball FBGA
1
2
3
4
VREF
VDD
VTT
VSS
D4
D5
VEXT
Q4
Q5
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSS
VSSQ
VDDQ
VEXT
Q0
Q1
TMS
D0
D1
TCK
VDD
VTT
A
B
C
D
(A22)1
D6
Q6
VSSQ
VSSQ
QK0#
QK0
VSS
E
2
D7
D8
A6
A9
Q7
Q8
A7
VSS
VDDQ
VSSQ
VDD
VSS
VDDQ
VSSQ
VDD
VSS
Q2
Q3
A2
VSS
D2
D3
A1
A4
(A20)2
QVLD
A0
A3
NF3
DK#
CS#
A16
D14
D15
QK1
D16
D17
ZQ
VDD
VDD
VSS
A17
Q14
Q15
QK1#
Q16
Q17
VEXT
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDD
VDD
VSS
A12
Q9
Q10
Q11
Q12
Q13
VEXT
B0
B1
A14
A11
D9
D10
D11
D12
D13
TDO
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
F
G
H
J
K
L
M
N
P
R
T
U
V
(A21)
A5
A8
B2
NF3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
NOTE:
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal.
This may optionally be connected to GND.
3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 4: 32 Meg x 9 Ball Assignment (Top View) 144-Ball FBGA
A
B
C
1
2
VREF
VSS
3
4
VEXT
4
5
6
7
8
9
10
11
12
VSS
VSS
VEXT
TMS
TCK
4
VDD
DNU
DNU
VSSQ
VSSQ
Q0
D0
VDD
VTT
DNU4
DNU4
VDDQ
VDDQ
Q1
D1
VTT
D
(A22)
1
DNU4
DNU4
VSSQ
VSSQ
QK0#
QK0
VSS
E
(A21)2
DNU4
DNU4
VDDQ
VDDQ
Q2
D2
A20
F
A5
A8
B2
DNU4
A6
A9
DNU4
A7
VSS
VSSQ
VDD
VSS
VSSQ
VDD
VSS
Q3
A2
VSS
D3
A1
A4
QVLD
A0
A3
NF3
DK
REF#
WE#
NF3
DK#
CS#
A16
VDD
VDD
VSS
A17
VDD
VDD
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VSS
A12
B0
B1
A14
A11
CK
CK#
A13
A10
A18
DNU4
DNU4
VSSQ
VSSQ
Q4
D4
A19
A15
DNU
4
DNU4
VDDQ
VDDQ
Q5
D5
DM
VSS
DNU4
DNU4
VSSQ
VSSQ
Q6
D6
VSS
VTT
DNU
4
4
DNU
VDDQ
VDDQ
Q7
D7
VTT
VDD
VREF
DNU4
DNU4
ZQ
VEXT
VSSQ
VSS
VSSQ
VSS
Q8
VEXT
D8
TDO
VDD
TDI
G
H
J
K
L
M
N
P
R
T
U
V
NOTE:
1. Reserved for future use. This signal is not connected.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal.
3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected
to GND.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 2:
Ball Descriptions
SYMBOL
TYPE
DESCRIPTION
CK, CK#
Input
CS#
Input
WE#, REF#
Input
A[0:20]
Input
A21
–
A22
DKx, DKx#
–
Input
DM
Input
BA[0:2]
D0–D17
Input
Input
Q0–Q17
Output
QKx, QKx#
Output
QVLD
Output
TMS
TDI
TCK
Input
Input
TDO
ZQ
Output
Input/Output
VREF
Input
VEXT
Supply
VDD
Supply
Input Clock: CK and CK# are differential clock inputs. Addresses and commands are
latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip Select: CS# enables the command decoder when LOW and disables it when HIGH.
When the command decoder is disabled, new commands are ignored, but internal
operations continue.
Command Inputs: Sampled at the positive edge of CK, WE#, and REF# define (together
with CS#) the command to be executed.
Address Inputs: A[0:20] define the row and column addresses for READ and WRITE
operations. During a MODE REGISTER SET, the address inputs define the register
settings. They are sampled at the rising edge of CK. In the x18 configuration, A[20] is
reserved for address expansion. These expansion addresses can be treated as address
inputs, but they do not affect the operation of the device.
Reserved for future use. This signal is internally connected and can be treated as an
address input.
Reserved for future use. This signal is not connected and may be connected to ground.
Input Data Clock: DKx and DKx# are the differential input data clocks. All input data is
referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. D0–
D17 are referenced to DK0 and DK0#.
Input Data Mask: The DM signal is the input mask signal for WRITE data. Input data is
masked when DM is sampled HIGH, along with the WRITE input data. DM is sampled on
both edges of DK.
Bank Address Inputs: Select to which internal bank a command is being applied.
Data Input: The D signals form the 18-bit input data bus. During WRITE commands, the
data is referenced to both edges of DK.
Data Output: The Q signals form the 18-bit output data bus. During READ commands,
the data is referenced to both edges of QK.
Output Data Clocks: QKx and QKx# are opposite polarity, output data clocks. During
READs, they are free running and edge-aligned with data output from the RLDRAM.
QKx# is ideally 180 degrees out of phase with QKx. QK0 and QK0# are aligned with Q0–
Q8 and QK1 and QK1# are aligned with Q9–Q17. Consult the RLDRAM II Design Guide
for more details.
Data Valid: The QVLD indicates valid output data. QVLD is edge-aligned with QKx and
QKx#.
IEEE 1149.1 Test Inputs: These balls may be left as No Connects if the JTAG function is
not used in the circuit
IEEE 1149.1 Clock Input: This ball must be tied to VSS if the JTAG function is not used in
the circuit.
IEEE 1149.1 Test Output: JTAG output.
External Impedance [25Ω–60Ω]: This signal is used to tune the device outputs to the
system data bus impedance. Q output impedance is set to 0.2 x RQ, where RQ is a
resistor from this signal to ground. Connecting ZQ to GND invokes the minimum
impedance mode. Connecting ZQ to VDD invokes the maximum impedance mode. Refer
to Figure 10 on page 16 to activate this function.
Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input
buffers.
Power Supply: 2.5V nominal. See Table 19, DC Electrical Characteristics and Operating
Conditions, on page 41 for range.
Power Supply: 1.8V nominal. See Table 19, DC Electrical Characteristics and Operating
Conditions, on page 41 for range.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 2:
Ball Descriptions (continued)
SYMBOL
TYPE
VDDQ
Supply
VSS
VSSQ
VTT
Supply
Supply
Supply
NF
DNU
–
–
DESCRIPTION
DQ Power Supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise
immunity. See Table 19: “DC Electrical Characteristics and Operating Conditions” on
page 41 for range.
Ground.
DQ Ground: Isolated on the device for improved noise immunity.
Power Supply: Isolated Termination Supply. Nominally, VDDQ/2. See Table 19, DC
Electrical Characteristics and Operating Conditions, on page 41 for range.
No Function: These balls may be connected to ground.
Do Not Use: These balls may be connected to ground.
Commands
Table 3:
According to the functional signal description, the
following command sequences are possible. All input
states or sequences not shown are illegal or reserved.
All command and address inputs must meet setup and
hold times around the rising edge of CK.
Table 4:
Address Widths at Different
Burst Lengths
CONFIGURATION
BURST LENGTH
x18
x9
BL = 2
BL = 4
BL = 8
19:0
18:0
17:0
20:0
19:0
18:0
Command Table1
OPERATION
Device DESELECT/No Operation
MRS: Mode Register Set
READ
WRITE
AUTO REFRESH
CODE
CS#
WE#
REF#
A(20:0)
B(2:0)
NOTES
DESEL/NOP
MRS
READ
WRITE
AREF
H
L
L
L
L
X
L
H
L
H
X
L
H
H
L
X
OPCODE
A
A
X
X
X
BA
BA
BA
2
3
3
NOTE:
1. X represents a “Don’t Care”; H represents a logic HIGH; L represents a logic LOW; A represents a valid address; and BA
represents a valid bank address.
2. Only A[17:0] are used for the MRS command.
3. See Table 3 above.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 5:
Description of Commands
COMMAND
DESCRIPTION
DESEL/NOP1
The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects
the chip. Use the NOP command to prevent unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected. Output values depend on
command history.
The mode register is set via the address inputs A(17:0). See Figure 10 on page 16 for further
information. The MRS command can only be issued when all banks are idle and no bursts are in
progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA(2:0)
inputs selects the bank, and the address provided on inputs A(20:0) selects the data location within
the bank.
The WRITE command is used to initiate a burst write access to a bank. The value on the BA(2:0)
inputs selects the bank, and the address provided on inputs A(20:0) selects the data location within
the bank. Input data appearing on the DS is written to the memory array subject to the DM input
logic level appearing coincident with the data. If the DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored (i.e., this part of the data word will not be written).
The AREF is used during normal operation of the RLDRAM to refresh the memory content of a
bank. The command is nonpersistent, so it must be issued each time a refresh is required. The value
on the BA(2:0) inputs selects the bank. The refresh address is generated by an internal refresh
controller, effectively making each address bit a “Don’t Care” during the AREF command. The
RLDRAM requires 64K cycles at an average periodic interval of 0.49µs2 (MAX). To improve
efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic
intervals of 3.9µs3.
MRS
READ
WRITE
AREF
NOTE:
1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.
2. Actual refresh is 32ms/8K/8 = 0.488µs.
3. Actual refresh is 32ms/8k = 3.90µs.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 6:
AC Electrical Characteristics
Note 1
-25
DESCRIPTION
-33
-5
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Clock
Clock cycle time
tCK, tDK
2.5
5.7
3.3
5.7
5.0
5.7
ns
System frequency
f
175
400
175
300
175
f
CK, DK
0.15
0.20
200
MHz
0.25
ns
Clock phase jitter
tCKVAR
Clock HIGH time
tCKH, tDKH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock LOW time
t
CKL, tDKL
0.45
0.55
0.45
0.55
0.45
0.55
t
Clock to input data clock
tCKDK
-0.3
0.5
-0.3
1.0
-0.3
1.5
Mode register set cycle time to
any command
Setup Times
Address/command and input
setup time
Data-in and data mask to DK
setup time
Hold Times
Address/command and input
hold time
Data-in and data mask to DK
hold time
Data and Data Strobe
Output data clock HIGH time
t
NOTES
2
CK
ns
MRSC
6
6
6
tAS/tCS
0.4
0.5
0.8
ns
tDS
0.25
0.3
0.4
ns
AH/tCH
0.4
0.5
0.8
ns
tDH
0.25
0.3
0.4
ns
tQKH
0.9
1.1
0.9
1.1
0.9
1.1
tCKH
t
QKL
0.9
1.1
0.9
1.1
0.9
1.1
t
QK edge to clock edge skew
tCKQK
-0.25
0.25
-0.3
0.3
-0.5
0.5
CKL
ns
QK edge to output data edge
t
QKQ0,
QKQ1
-0.2
0.2
-0.25
0.25
-0.3
0.3
ns
3
tQKQ
-0.3
0.3
-0.35
0.35
-0.4
0.4
ns
4
tQKVLD
-0.3
0.3
-0.35
0.35
-0.4
0.4
ns
t
Output data clock LOW time
t
CK
t
QK edge to any output data
edge
QK edge to QVLD
NOTE:
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF
of the command, address, and data signals.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3. tQKQ0 is referenced to Q0–Q8 in x18.
tQKQ1 is referenced to Q9–Q17 in x18.
4. tQKQ takes into account the skew between any QKx and any Q.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 5: Clock/Input Data Clock
Command/Address Timings
tCK
tCKH
Initialization
The RLDRAM must be powered up and initialized in
a predefined manner. Operational procedures other
than those specified may result in undefined operations or permanent damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and
start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same
time as VDDQ. Apply VDDQ before or at the same
time as VREF and VTT. Although there is no timing
relation between VEXT and VDD, the chip starts
the power-up sequence only after both voltages
are at their nominal levels. The pad supply must
not be applied before the core supplies. Maintain
all remaining balls in NOP conditions.
2. Maintain stable conditions for 200µs (MIN).
3. Issue three MRS commands: two dummies plus
one valid MRS.
4. tMRSC after the valid MRS, issue eight Auto
Refresh commands, one on each bank and separated by 2,048 cycles. Initial bank refresh order
does not matter.
5. After tRC, the chip is ready for normal operation.
tCKL
CK#
CK
CMD,
ADDR
VALID
VALID
tCKDK
VALID
tCKDK
tAS
tAH
DKx#
DKx
tDK
tDKH
tDKL
DON’T CARE
Figure 6: Power-Up Sequence
VEXT
VDD
VDDQ
VREF
VTT
CK#
CK
CMD
NOP
NOP
MRS
MRS
MRS
NOP
RF0
RF1
RF7
AC
ADD
200µs MIN
tMRSC
MRS: MRS command
RFx: REFRESH Bank x
AC: Any command
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MT49H8M18C_2.fm - Rev. F 11/04 EN
2,048
cycles
MIN
6 × 2,048
cycles
MIN
tRC
DON’T CARE
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Programmable Impedance Output
Buffer
Output impedance updates may be required
because, over time, variations may occur in supply
voltage and temperature. The device samples the value
of RQ. An impedance update is transparent to the system and does not affect device operation. All data
sheet timing and current specifications are met during
an update.
The RLDRAM II is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the
resistor must be five times the desired impedance. For
example, a 300Ω resistor is required for an output
impedance of 60Ω. To ensure that output impedance is
one fifth the value of RQ (within 15 percent), the range
of RQ is 125Ω to 300Ω.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Clock Considerations
The RLDRAM II utilizes internal delay-locked loops
for maximum output, data valid windows. It can be
placed into a stopped-clock state to minimize power
with a modest restart time of 1,024 cycles.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 7:
Clock Input Operating Conditions
Notes 1–8
PARAMETER/CONDITION
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
MIN
MAX
UNITS
NOTES
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
-0.3
0.2
0.4
VDDQ/2 - 0.15
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
VDDQ/2 + 0.15
V
V
V
V
9
9
10
Figure 7: Clock Input
VIN(DC) MAX
Maximum Clock Level
CK#
X
VDDQ/2 + 0.15
VIX(AC) MAX
VID(DC)12
VDDQ/2
VDDQ/2 - 0.15
11
X
VID(AC)
13
VIX(AC) MIN
CK
Minimum Clock Level
VIN(DC) MIN
NOTE:
1. DKx and DKx# have the same requirements as CK and CK#.
2. All voltages referenced to VSS.
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operations are tested for the full voltage range specified.
4. Outputs (except for IDD measurements) measured with equivalent load.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are tested for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in the
range between VIL(AC) and VIH(AC).
6. The AC and DC input level specifications are as defined in the HSTL Standard (i.e., the receiver will effectively switch as a
result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
7. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input
reference level for signals other than CK/CK# is VREF.
8. CK and CK# input slew rate must be ≥ 2 V/ns (≥4 V/ns if measured differentially).
9. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
10. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the
same.
11. CK and CK# must cross within this region.
12. CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2.
13. Minimum peak-to-peak swing.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Mode Register Set Command (MRS)
Figure 9: Mode Register Set
The mode register stores the data for controlling the
operating modes of the memory. It programs the
RLDRAM configuration, burst length, test mode, and
I/O options. During a MRS command, the address
inputs A(17:0) are sampled and stored in the mode register. tMRSC must be met before any command can be
issued to the RLDRAM. The mode register may be set
at any time during device operation. However, any
pending operations are not guaranteed to successfully
complete. See the RLDRAM II design guide for more
details.
CK#
CK
CS#
WE#
REF#
Figure 8: Mode Register Set Timing
A(17:0)
COD
CK#
A(20:18)
CK
CMD
MRS
NOP
NOP
AC
BA(2:0)
DON’T CARE
tMRSC
DON’T CARE
NOTE:
COD: code to be loaded into the register.
NOTE:
MRS: MRS command and AC: any command.
Figure 10: Mode Register Bit Map
A(17:10)
Reserved1
A9
A8
Impedance
On-Die
Termination Matching
On-Die
Termination
A9
0
1
A7
A6
A5
DLL Reset
Unused
Address
Mux
DLL Reset
Termination
Disabled (default)
Enabled
A3
A2
A1
Burst Length
A0
Configuration
Configuration
Burst Length
A7
DLL Reset
A4
A3
BL
A2
A1
A0
RLDRAM
Configuration
0
DLL reset (default)
0
0
2 (default)
0
0
0
12 (default)
0
1
4
0
0
1
12
1
0
82
0
1
0
2
1
1
not valid
0
1
1
3
1
0
0
reserved
1
DLL enabled
Impedance
Matching
A8
Resistor
0
internal 50Ω3
(default)
1
A4
external
Address Mux
A5
Address Mux
1
0
1
reserved
0
nonmultiplexed
(default)
1
1
0
reserved
1
1
1
reserved
1
address multiplexed
NOTE:
1. Bits A(17:10) must be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
cycle times (tRC) are shown in clock cycles as well as in
nanoseconds.
The shaded areas correspond to configurations that
are not allowed.
Configuration Table
Table 8 shows, for different operating frequencies,
the different RLDRAM configurations that can be programmed into the mode register. The READ and
WRITE latency (tRL and tWL) values along with the row
Table 8:
RLDRAM Configuration Table
CONFIGURATION
FREQUENCY
400 MHz
300 MHz
200 MHz
1
SYMBOL
1
2
3
UNIT
tRC
4
6
8
cycles
tRL
4
6
8
cycles
tWL
5
7
9
cycles
tRC
20.0
ns
tRL
20.0
ns
tWL
22.5
ns
tRC
20.0
26.7
ns
tRL
20.0
26.7
ns
tWL
23.3
30.0
ns
30.0
40.0
ns
tRC
20.0
tRL
20.0
30.0
40.0
ns
tWL
25.0
35.0
45.0
ns
NOTE:
1. BL = 8 is not available for configuration 1.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Write Basic Information
Figure 11: WRITE Command
Write accesses are initiated with a WRITE command, as shown in Figure 11. Row and bank addresses
are provided together with the WRITE command.
During WRITE commands, data will be registered at
both edges of DK according to the programmed burst
length (BL). A WRITE latency (WL) one cycle longer
than the programmed READ latency (RL + 1) is
present, with the first valid data registered at the first
rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent
READ command. Figures 15 and 16 illustrate the timing requirements for a WRITE followed by a READ for
bursts of two and four, respectively.
Setup and hold times for incoming D relative to the
DK edges are specified as tDS and tDH. The input data
is masked if the corresponding DM signal is HIGH. The
setup and hold times for data mask are also tDS and
t
DH.
CK#
CK
CS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
NOTE:
A: address; BA: bank address.
Figure 12: Basic WRITE Burst/DM Timing
CK#
CK
tCKDK
DKx#
DKx
WRITE
Latency
tDS tDH
D
tDS tDH
D0
D1
D2
D3
DM
Data
masked
tDS
Data
masked
tDH
DON’T CARE
Timing Parameters
-25
MAX
-33
MAX
MIN
-25
SYMBOL
MIN
tDS
0.25
0.3
0.4
ns
tDH
0.25
0.3
0.4
ns
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
MIN
-5
MAX UNITS
18
-33
-5
SYMBOL
MIN
MAX
MIN
MAX
MIN
tCKDK
-0.3
0.5
-0.3
1.0
-0.3
MAX UNITS
1.5
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 13: Write Burst Basic Sequence: BL = 2, RL = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
WR
WR
WR
WR
WR
WR
WR
WR
WR
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA4
A
BA5
A
BA6
A
BA7
CK#
CK
RC = 4
WL = 5
DK#
DK
D
D0a D0b D1a D1b D2a D2b D3a
D3
Figure 14: Write Burst Basic Sequence: BL = 4, RL = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
A
BA0
CK#
CK
A
BA1
A
BA0
A
BA3
A
BA0
RC = 4
WL = 5
DK#
DK
D
D0a D0b
D0c
D0d D1a D1b
D1c
D1
DON’T CARE
NOTE:
1. A/BAx: Address A of bank x
WR: WRITE command
Dxy: Data y to bank x
RC: Row cycle time
WL: WRITE latency
2. Any free bank may be used in any given CMD. The sequence shown is only one example of a bank sequence.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 15: WRITE Followed By READ: BL = 2, RL = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
8
9
CMD
WR
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA2
CK#
CK
WL = 5
RL = 4
DK#
DK
D
D0a
D0b
Q1a Q1b Q2a Q2b
Q
QKx
QKx#
DON’T CARE
Figure 16: WRITE Followed By READ: BL = 4, RL = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
8
9
CMD
WR
RD
WR
RD
NOP
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
D0c
D0d D2a
CK#
CK
WL = 5
RL = 4
DK#
DK
D0a
D
Q
D0b
Q1a Q1b Q1c
D2b
D2c
D2d
Q1d Q3a Q3b Q3c
Q3d
QKx
QKx#
DON’T CARE
WL: WRITE latency
RD: READ
Qxy: Data y from bank x
RL: READ latency
NOTE:
A/BAx: Address A of bank x
WR: WRITE
Dxy: Data y to bank x
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Read Basic Information
Figure 17: READ Command
Read accesses are initiated with a READ command,
as shown in Figure 17. Row and bank addresses are
provided with the READ command.
During READ bursts, the memory device drives the
read data edge-aligned with the QK signal. After a programmable read latency, data is available at the outputs. The data valid signal indicates that valid data will
be present in the next half clock cycle.
The skew between QK and the crossing point of CK
is specified as tCKQK. tQKQ0 is the skew between QK0
and the last valid data edge considered over all the
data generated at the Q signals. tQKQ1 is the skew
between QK1 and the last valid data edge considered
over all the data generated at the Q signals. tQKQx is
derived at each QKx clock edge and is not cumulative
over time. tQKQ is the maximum of tQKQ0 and tQKQ1.
After completion of a burst, assuming no other
commands have been initiated, output data (Q) will go
High-Z. Back-to-back READ commands are possible,
producing a continuous flow of output data.
The data valid window is derived from each QK
transition and is defined as:
MIN (tQKH, tQKL) - 2(tQKQ [MAX]).
Any READ burst may be followed by a subsequent
WRITE command. Figures 21 and 22 illustrate the timing requirements for a READ followed by a WRITE.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
CK#
CK
CS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
DON’T CARE
NOTE:
A: address; BA: bank address.
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 18: Basic READ Burst Timing
tCKH
tCKL
tCK
CK#
CK
tQKL
tCKQK
tQKH
QKx
QKx#
tQKVLD
tQKVLD
QVLD
Q
Q0
Q1
Q2
Q3
tQKQ
tQKQ
tQKQ
Note 1
UNDEFINED
Timing Parameters
-25
SYMBOL
tCK
-33
-5
MIN
MAX
MIN
MAX
MIN
2.5
5.7
3.3
5.7
5.0
-25
MAX UNITS
5.7
ns
-33
-5
SYMBOL
MIN
MAX
MIN
MAX
MIN
tQKQ0,
-0.2
0.2
-0.25
0.25
-0.3
MAX UNITS
0.3
ns
tCKH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
t
t
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
tQKVLD
-0.3
0.3
-0.35
0.35
-0.4
0.4
1.1
0.9
1.1
0.9
1.1
t
1.1
0.9
1.1
0.9
1.1
tCKL
CKL
tCKQK
t
QKQ
QKQ1
-0.25
0.25
-0.3
0.3
-0.5
0.5
ns
t
QKH
0.9
-0.3
0.3
-0.35
0.35
-0.4
0.4
ns
tQKL
0.9
ns
CKH
NOTE:
1. Minimum data valid window can be expressed as MIN (tQKH, tQKL) - 2 x tQKQx (MAX).
2. tQKQ0 is referenced to Q0–Q8 in x18.
t
QKQ1 is referenced to Q9–Q17 in x18.
3. tQKQ takes into account the skew between any QKx and any Q.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 19: READ Burst: BL = 2, RL = 4, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
RD
RD
RD
RD
RD
RD
RD
RD
RD
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA7
A
BA6
A
BA5
A
BA4
CK#
CK
RC = RL = 4
QKx
QKx#
QVLD
Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a
Q
DON’T CARE
UNDEFINED
Figure 20: READ Burst: BL = 4, RL = 4, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDR
A
BA0
CK#
CK
A
BA1
A
BA0
A
BA1
A
BA3
RC = RL = 4
QKx
QKx#
QVLD
Q0a Q0b Q0c Q0d Q1a Q1b Q1c Q1d Q0a
Q
DON’T CARE
UNDEFINED
NOTE:
A/BAx: Address A of bank x
RD: READ
Dxy: Data y to bank x
RC: Row cycle time
RL: READ latency
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 21: READ Followed by WRITE, BL = 2, RL = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
CMD
RD
WR
WR
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA2
D1a
D1b D2a
CK#
CK
WL = 5
RL = 4
DK#
DK
D
Q
Q0a
D2b
Q0b
QKx
QKx#
DON’T CARE
Figure 22: READ followed by WRITE, BL = 4, RL = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
CMD
RD
WR
RD
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA2
D1a
D1b D1c
CK#
CK
WL = 5
RL = 4
DK#
DK
D
Q0a Q0b Q0c
Q
Q0d
D1d
Q2a Q2b Q2c
QKx
QKx#
DON’T CARE
NOTE:
A/BAx: Address A of bank x
WR: WRITE command
Dxy: Data y to bank x
RD: READ command
Qxy: Data y from bank x
WL: WRITE latency
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
RL: READ latency
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 23: READ/WRITE Interleave: BL = 4, tRC = 4, WL = 5, Configuration 1
0
1
2
3
4
5
6
7
8
9
10
CMD
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
RD
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA1
A
BA2
CK#
CK
WL = 5
tRC = 4
D
D1a D1b D1c D1d D3a D3b D3c
D3d D1a
D
RL = 4
QKx#
QKx
Q0a Q0b Q0c Q0d Q2a Q2b Q2c Q2d Q0a Q0b Q0c Q0d Q2a
Q
UNDEFINED
DON’T CARE
Figure 24: READ/WRITE Interleave: BL = 4, tRC = 6, WL = 7, Configuration 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CMD
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
RD
RD
WR
RD
WR
RD
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA0
A
BA1
A
BA2
A
BA3
AA
BA4
BA2
A
BA5
A
BA0
A
BA1
A
BA2
CK#
CK
WL = 7
tRC = 6
D5c D5d D1a D1
D1a D1b D1c D1d D3a D3b D3c D3d D5a D5b
D
D
RL = 6
QKx#
QKx
Q
Q0a Q0b Q0c Q0d Q2a
Q0a Q0b Q0c Q0d Q2a Q2b Q2c Q2d Q4a Q4b Q4c Q4d Q2a
DON’T CARE
NOTE:
A/BAx: Address A of bank x
WR: WRITE command
Dxy: Data y to bank x
Qxy: Data y from bank x
RL: READ latency
tRC: Row cycle time
WL: WRITE latency
RD: READ command
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MT49H8M18C_2.fm - Rev. F 11/04 EN
UNDEFINED
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 25: READ/WRITE Interleave: BL = 4, tRC = 8, WL = 9, Configuration 3
0
1
2
7
8
9
10
11
12
13
14
15
16
17
CMD
RD
WR
RD
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
RD
ADDR
A
BA0
A
BA1
A
BA2
A
BA7
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
A
BA1
CK#
CK
WL = 9
tRC = 8
D1a D1b D1c D1d D3a D3b D3c D3d D5a D5b
D D5c D5d D7a D7b D7c D7
D
RL = 8
QKx#
QKx
Q
Q0a Q0b Q0c Q0d Q2a Q2b Q2c Q2d Q4a Q4b Q4c Q4d Q6a Q6b Q6c Q6d Q0a Q0b Q0c
DON’T CARE
NOTE:
A/BAx: Address A of bank x
WR: WRITE command
Dxy: Data y to bank x
Qxy: Data y from bank x
RL: READ latency
tRC: Row cycle time
WL: WRITE latency
RD: READ command
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MT49H8M18C_2.fm - Rev. F 11/04 EN
UNDEFINED
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
AUTO REFRESH Command (AREF)
Figure 26: AUTO REFRESH Command
AREF is used to perform a refresh cycle on one row
in a specific bank. The row addresses are generated by
an internal refresh counter for each bank; external
address balls are “Don’t Care.” The delay between the
AREF command and a subsequent command to the
same bank must be at least tRC.
Within a period of 32ms (tREF), the entire memory
must be refreshed. Figure 27 illustrates an example of a
continuous refresh sequence. Other refresh strategies,
such as burst refresh, are also possible.
CK#
CK
CS#
WE#
REF#
A(20:0)
BA
BA(2:0)
NOTE:
BA: Bank address.
Figure 27: AUTO REFRESH Cycle
CK#
CK
CMD
ARFx
ACy
ACx
ACy
tRC
ARFx
ACy
DON’T CARE
NOTE:
1. ACx: Any command on bank x
ARFx: Auto Refresh bank x
ACy: Any command on different bank
2. tRC is configuration-dependent. Refer to Table 8, RLDRAM Configuration Table, on page 17.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
On-Die Termination
Figure 28: On-Die TerminationEquivalent Circuit
On-die termination (ODT) is enabled by setting A9
to “1” during an MRS command. With ODT on, all the
DQs and DM are terminated to VTT with a resistance
RTT. The command, address, and clock signals are not
terminated. Figure 28 below shows the equivalent circuit of a Q driver with ODT. ODTs are dynamically
switched off during READ commands and are
designed to be off prior to the RLDRAM driving the
bus. Similarly, ODTs are designed to switch on after the
RLDRAM has issued the last piece of data. ODT at the
D inputs and DM are always on.
Table 9:
DESCRIPTION
VTT
sw
RTT
Q
Driver
On-Die Termination DC
Parameters
SYM
MIN
MAX
UNITS
NOTES
Termination
Voltage
VTT
0.95 X
VREF
1.05 X
VREF
V
1, 2
On-Die
Termination
RTT
135
165
Ω
3
NOTE:
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track
variations in the DC level of VREF.
3. The RTT value is measured at 70°C TC.
Figure 29: READ Burst with ODT: BL = 2, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
RD
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA2
CK#
CK
RL = 4
QKx
QKx#
QVLD
Q0a Q0b Q1a Q1b Q2a Q2b
Q
ODT
ODT ON
ODT OFF
DON’T CARE
NOTE:
A/BAx: address A of bank x
RD: READ
Qxy: Data y to bank x
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MT49H8M18C_2.fm - Rev. F 11/04 EN
ODT ON
UNDEFINED
RL: READ latency
28
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16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 30: READ NOP READ with ODT: BL = 2, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
RD
NOP
RD
NOP
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
CK#
CK
A
BA2
RL = 4
QKx
QKx#
QVLD
Q0a Q0b
Q
ODT
ODT ON
ODT OFF
Q2a Q2b
ODT ON
ODT ON
ODT OFF
UNDEFINED
DON’T CARE
Figure 31: READ NOP NOP READ with ODT: BL = 2, Configuration 1
0
1
2
3
4
5
6
7
8
CMD
RD
NOP
NOP
RD
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
9
CK#
CK
A
BA2
RL = 4
QKx
QKx#
QVLD
Q0a Q0b
Q
ODT
ODT ON
ODT OFF
Q2a Q2b
ODT ON
ODT OFF
DON’T CARE
ODT ON
UNDEFINED
NOTE:
A/BAx: address A of bank x
RD: READ
Qxy:Data y to bank x
RL: READ latency
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MT49H8M18C_2.fm - Rev. F 11/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Operation with Multiplexed Addresses
RLDRAM at the same time as the write command and
the first address part, Ax.
This option is available by setting bit A5 to “1” in the
mode register. Once this bit is set, the READ, WRITE,
and MRS commands follow the format described in
Figure 32. See Figure 34 on page 31 for the power-up
sequence.
In multiplexed address mode, the address can be
provided to the RLDRAM in two parts that are latched
into the memory with two consecutive rising clock
edges. This provides the advantage that a maximum SP
of 11 address balls are required to control the
RLDRAM, reducing the number of balls on the controller side. The bank addresses are delivered to the
Figure 32: Command Description in Multiplexed Address Mode
READ
WRITE
MRS
CK#
CK
CS#
WE#
REF#
A<20:0>
Ax
BA<2:0>
BA
Ay
Ax
BA
Ay
Ax
Ay
BA
DON’T CARE
NOTE:
1. Ax, Ay: Address
BA: Bank Address
2. The minimum setup and hold times of the two address parts are defined tAS and tAH.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
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©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 33: Mode Register Set Command in Multiplexed Address Mode
The addresses A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in the
multiplexed address mode.
Ax
A9
A8
A5
Ay
Impedance
On-Die
Termination Matching
On-Die
Termination
A9x
Termination
0
1
A9
A8
DLL Reset
Unused
DLL Reset
0
DLL reset (default)
1
Address
Mux
DLL enabled
Resistor
0
internal 50Ω3
(default)
1
A3
Burst Length
Configuration
Configuration
A4x A3x
Impedance
Matching
A8x
A0
Burst Length
A9y
Enabled
A3
A4
DLL Reset
Disabled (default)
A4
BL
A4y A3y A0x
RLDRAM
Configuration
0
0
2 (default)
0
0
0
12 (default)
0
1
4
0
0
1
12
1
0
82
0
1
0
2
1
1
not valid
0
1
1
3
1
0
0
reserved
A5x
Address Mux
1
0
1
reserved
0
nonmultiplexed
(default)
1
1
0
reserved
1
1
1
reserved
external
1
address multiplexed
NOTE:
1. Bits A(17:10) must be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.
Figure 34: Power-Up Sequence in Multiplexed Address Mode
The following sequence must be respected in order to power up the RLDRAM in the multiplexed address mode.
VEXT
VDD
VDDQ
VREF
VTT
CK#
CK
CMD
NOP
NOP
MRS
MRS
MRS
NOP
A1)
ADD
200µs MIN
MRS: MRS command
RFx: REFRESH Bank x
AC: any command
1 cycle
MIN
1 cycle
MIN
tMRSC
MRS
NOP
Ax2)
Ay
tMRSC
RF0
RF1
RF7
2,048 cycles 6 × 2,048
MIN
cycles MIN
AC
tRC
DON’T CARE
NOTE:
1. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is in normal mode of operation).
2. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is already in muxed address mode).
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MT49H8M18C_2.fm - Rev. F 11/04 EN
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Address Mapping
The address mapping is described in Table 10 as a
function of data width and burst length.
Table 10: Address Mapping in Multiplexed Address Mode
Note 1
ADDRESSES
DATA
BURST
WIDTH LENGTH
x18
BL = 2
BL = 4
BL = 8
x9
BL = 2
BL = 4
BL = 8
BALL
A02
A3
A4
A53
A8
A9
A10
A13
A14
A17
A18
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
A0
X
A0
X
A0
X
A0
A20
A0
X
A0
X
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A10
A19
A10
X
A10
X
A10
A19
A10
A19
A10
X
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A15
A18
A15
X
A15
A18
A15
A18
A15
A18
A15
NOTE:
1. X means “Don’t Care.”
2. Reserved for A20 expansion in multiplexed mode.
3. Reserved for A21 expansion in multiplexed mode.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Configuration Table
In this mode, the READ and WRITE latencies are
increased by one clock cycle. The RLDRAM cycle time
remains the same, as described in Table 11.
Table 11: Configuration Table In Multiplexed Address Mode
CONFIGURATION
FREQUENCY
SYMBOL
11
2
3
UNIT
tRC
4
6
8
cycles
tRL
5
7
9
cycles
t
6
8
400 MHz
300 MHz
200 MHz
10
cycles
tRC
20.0
ns
t
RL
22.5
ns
tWL
25.0
ns
WL
tRC
20.0
26.7
ns
tRL
23.3
30.0
ns
tWL
26.7
33.3
ns
30.0
40.0
ns
20.0
tRC
tRL
25.0
35.0
45.0
ns
tWL
35.0
40.0
50.0
ns
NOTE:
1. BL = 8 is not available for configuration 1.
Refresh Command in Multiplexed
Address Mode
address is required for AREF, the next command can be
applied on the following clock. The operation of the
AREF command and any other command is represented in Figure 35.
Similar to other commands, the refresh command is
executed on the next rising clock edge when in the
multiplexed address mode. However, since only bank
Figure 35: Burst Refresh Operation
0
1
2
3
4
5
6
7
8
9
10
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AC
11
CK#
CK
CMD
AC
ADDR
Ax
BADDR
BAk
Ax
Ay
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
Ay
BAk
DON’T CARE
Ax: First part Ax of address
Ay: Second part Ay of address
BAk: Bank k; k is chosen so that tRC is met
NOTE:
AREF: AUTO REFRESH
AC: Any command
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MT49H8M18C_2.fm - Rev. F 11/04 EN
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 36: WRITE Burst Basic Sequence: BL = 4, with Multiplexed Addresses,
Configuration 1, WL = 6
0
1
2
3
4
5
6
7
8
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
Ax
BA0
Ay
Ax
BA1
Ay
Ax
BA2
Ay
Ax
BA3
Ay
Ax
BA0
D0a D0b
D0c
CK#
CK
WL = 6
DKx#
DKx
D
D0d D1a
D1
Figure 37: READ Burst Basic Sequence: BL = 4, with Multiplexed Addresses,
Configuration 1, RL = 5
0
1
2
3
4
5
6
7
8
CMD
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDR
Ax
BA0
Ay
Ax
BA1
Ay
Ax
BA2
Ay
Ax
BA0
Ay
Ax
BA1
CK#
CK
RL = 5
QKx
QKx#
QVLD
Q0a Q0b Q0c Q0d Q1a Q1b Q1c
Q
DON’T CARE
UNDEFINED
NOTE:
Ax/BAk: Address Ax of bank k
Ay: Address Ay of bank k
WR: WRITE
Djk: Data k to bank j
WL: WRITE latency
Qjk: Data k to bank j
RD: READ
RL: READ Latency
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MT49H8M18C_2.fm - Rev. F 11/04 EN
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©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
IEEE 1149.1 Serial Boundary Scan (JTAG)
Figure 38: TAP Controller State
Diagram
RLDRAM incorporates a serial boundary scan test
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-2001. The TAP operates
using logic levels associated with the VDDQ supply.
RLDRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID
register.
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
0
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
Disabling the JTAG Feature
0
SHIFT-DR
It is possible to operate RLDRAM without using the
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (VSS) to prevent clocking of the device.
TDI and TMS are internally pulled up and may be
unconnected. They may alternately be connected to
VDD through a pull-up resistor. TDO should be left
unconnected. Upon power-up, the device will come up
in a reset state, which will not interfere with the operation of the device.
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
UPDATE-IR
1
0
0
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Figure 39: TAP Controller Block
Diagram
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
0
Bypass Register
7 6 5 4 3 2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
Selection
Circuitry
TDO
. 2 1 0
Identification Register
Test Data-In (TDI)
x .
.
.
. 2 1 0
TCK
TMS
TAP Controller
NOTE:
x = 112 for all configurations.
Test Data-Out (TDO)
Performing a TAP RESET
The TDO output ball is used to serially clock dataout from the registers. The output is active depending
upon the current state of the TAP state machine (see
Figure 38). The output changes on the falling edge of
TCK. TDO is connected to the least significant bit
(LSB) of any register (see Figure 39).
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MT49H8M18C_2.fm - Rev. F 11/04 EN
.
Boundary Scan Register
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 38. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most significant bit (MSB) of any register (see Figure 39).
A reset is performed by forcing TMS HIGH (VDD) for
five rising edges of TCK. This RESET does not affect the
operation of the RLDRAM and may be performed
while the RLDRAM is operating.
At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
35
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©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
TAP Registers
ter. The IDCODE is hardwired into the RLDRAM and
can be shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Definitions table.
Registers are connected between the TDI and TDO
balls and allow data to be scanned into and out of the
RLDRAM test circuitry. Only one register can be
selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
TAP Instruction Set
Overview
Many different instructions (28) are possible with
the eight-bit instruction register. All used combinations are listed in Table 17, Instruction Codes, on
page 39. These six instructions are described in detail
below. The remaining instructions are reserved and
should not be used.
The TAP controller used in this RLDRAM is fully
compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
Instruction Register
Eight-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO ball, as shown in
Figure 39. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the boardlevel serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the RLDRAM with
minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
EXTEST
The EXTEST instruction allows circuitry external to
the component package to be tested. Boundary-scan
register cells at output balls are used to apply a test
vector, while those at input balls capture test results.
Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary
scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output
driver is turned on and the PRELOAD data is driven
onto the output balls.
Boundary Scan Register
The boundary scan register is connected to all the
input and bidirectional balls on the RLDRAM. Several
balls are also included in the scan register to reserved
balls. The RLDRAM has a 113-bit register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state.
The Boundary Scan Order tables (see page 40) show
the order in which the bits are connected. Each bit corresponds to one of the balls on the RLDRAM package.
The MSB of the register is connected to TDI, and the
LSB is connected to TDO.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
HIGH-Z
Identification (ID) Register
The High-Z instruction causes the boundary scan
register to be connected between the TDI and TDO.
This places all RLDRAM outputs into a High-Z state.
The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
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MT49H8M18C_2.fm - Rev. F 11/04 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
CLAMP
must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH).
The RLDRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the
clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out
the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.
When the CLAMP instruction is loaded into the
instruction register, the data driven by the output balls
are determined from the values held in the boundary
scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.
The user must be aware that the TAP controller
clock can only operate at a frequency up to 50 MHz,
while the RLDRAM clock operates significantly faster.
Because there is a large difference between the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To ensure that the boundary scan register will capture the correct value of a signal, the RLDRAM signal
BYPASS
When the BYPASS instruction is loaded in the
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.
Reserved
These instructions are not implemented but are
reserved for future use. Do not use these instructions.
Figure 40: TAP Timing
1
2
Test Clock
(TCK)
3
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
t
TLTH
4
5
6
tTHTH
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Table 12: TAP AC Electrical Characteristics and Operating Conditions
+0°C = TC = +95°C; +1.7V = VDD = +1.9V, unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
MIN
VIH
VIL
VREF + 0.3
VSSQ - 0.3
Input HIGH (Logic 1) Voltage
Input LOW (Logic 0) Voltage
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MT49H8M18C_2.fm - Rev. F 11/04 EN
37
MAX
VDD + 0.3
VREF - 0.3
UNITS
NOTES
V
V
1, 2
1, 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 13: TAP AC Electrical Characteristics
Note 1; +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
DESCRIPTION
SYMBOL
MIN
tTHTH
20
Clock
Clock cycle time
MAX
ns
50
f
Clock frequency
UNITS
TF
MHz
Clock HIGH time
t
THTL
10
ns
10
ns
0
ns
Clock LOW time
tTLTH
Output Times
TCK LOW to TDO unknown
t
TLOX
TLOV
10
ns
TCK LOW to TDO valid
t
TDI valid to TCK HIGH
tDVTH
5
ns
TCK HIGH to TDI invalid
tTHDX
5
ns
Setup Times
TMS setup
tMVTH
5
ns
Capture setup
tCS
5
ns
Hold Times
TMS hold
tTHMX
5
ns
Capture hold
tCH
5
ns
NOTE:
1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
Table 14: TAP DC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
CONDITIONS
0V ≤ VIN ≤ VDD
Output disabled,
0V ≤ VIN ≤ VDDQ
IOLC = 100µA
IOLT = 2mA
|IOHC| = 100µA
|IOHT| = 2mA
SYMBOL
MIN
MAX
UNITS
NOTES
VIH
VIL
ILI
ILO
VREF + 0.15
VSSQ - 0.3
-5.0
-5.0
VDD + 0.3
VREF - 0.15
5.0
5.0
V
V
µA
µA
1, 2
1, 2
0.2
0.4
V
V
V
V
1
1
1
1
VOL1
VOL2
VOH1
VOH2
VDDQ - 0.2
VDDQ - 0.4
NOTE:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2.
Undershoot: VIL(AC) ≥ -0.5V for t ≤ tCK/2.
During normal operation, VDDQ must not exceed VDD.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 15: Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
abcd
Revision Number
(31:28)
Device ID
(27:12)
00jkidef10100111
00000101100
Micron JEDEC ID
Code (11:1)
ID Register Presence
Indicator (0)
1
DESCRIPTION
ab = die revision
cd = 10 for x36, 01 for x18, 00 for x9.
def = 000 for 288M, 001 for 576M, 010 for 1G.
i = 0 for common I/O, 1 for separate I/O.
jk = 00 for RLDRAM, 01 for RLDRAM II.
Allows unique identification of RLDRAM vendor.
Indicates the presence of an ID register.
Table 16: Scan Register Sizes
REGISTER NAME
BIT SIZE
Instruction
Bypass
ID
Boundary Scan
8
1
32
113
Table 17: Instruction Codes
INSTRUCTION
CODE
Extest
0000 0000
ID Code
0010 0001
Sample/Preload
Clamp
0000 0101
0000 0111
High-Z
0000 0011
Bypass
1111 1111
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MT49H8M18C_2.fm - Rev. F 11/04 EN
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
This operation does not affect RLDRAM operations.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect RLDRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Selects the bypass register to be connected between TDI and TDO. Data driven by
output balls are determined from values held in the boundary scan register.
Selects the bypass register to be connected between TDI and TDO. All outputs are
forced into high impedance state.
Places the bypass register between TDI and TDO. This operation does not affect
RLDRAM operations.
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 18: Boundary Scan (Exit) Order
BIT#
FBGA BALL
BIT#
FBGA BALL
BIT#
FBGA BALL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
K1
K2
L2
L1
M1
M3
M2
N1
P1
N3
N3
N2
N2
P3
P3
P2
P2
R2
R3
T2
T2
T3
T3
U2
U2
U3
U3
V2
U10
U10
U11
U11
T10
T10
T11
T11
R10
R10
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
R11
R11
P11
P11
P10
P10
N11
N11
N10
N10
P12
N12
M11
M10
M12
L12
L11
K11
K12
J12
J11
H11
H12
G12
G10
G11
E12
F12
F10
F10
F11
F11
E10
E10
E11
E11
D11
D10
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
–
C11
C11
C10
C10
B11
B11
B10
B10
B3
B3
B2
B2
C3
C3
C2
C2
D3
D3
D2
D2
E2
E2
E3
E3
F2
F2
F3
F3
E1
F1
G2
G3
G1
H1
H2
J2
J1
–
NOTE:
1. Any unused balls that are in the order will read as the logic level applied to the ball site. If left floating, a value of “0” is
returned.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Absolute Maximum Ratings*
*Stresses greater than those listed may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
**Junction temperature depends upon package
type, cycle time, loading, ambient temperature, and
airflow.
Storage Temperature . . . . . . . . . . . . . . . .-55°C to +150°C
I/O Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDDQ + 0.3V
Voltage on VEXT Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.8V
Voltage on VDD Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.1V
Voltage on VDDQ Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.1V
Junction Temperature** . . . . . . . . . . . . . . . . . . . . . . .110°C
Table 19: DC Electrical Characteristics and Operating Conditions
(+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
Supply Voltage
Supply Voltage
Isolated Output Buffer Supply
Reference Voltage
Termination Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Output High Current
VOH = VDDQ/2
VEXT
VDD
VDDQ
VREF
VTT
VIH
VIL
IOH
Output Low Current
VOL = VDDQ/2
IOL
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDDQ
ILC
ILI
ILO
IREF
Clock Input Leakage Current
Input Leakage Current
Output Leakage Current
Reference Voltage Current
MIN
MAX
2.38
2.63
1.7
1.9
1.4
Vdd
0.49 X VDDQ 0.51 X VDDQ
0.95 X VREF
1.05 X VREF
VREF + 0.1
VDDQ + 0.3
VSSQ - 0.3
VREF - 0.1
(VDDQ/2) /
(VDDQ/2) /
(1.15 X RQ/5) (0.85 X RQ/5)
(VDDQ/2) /
(VDDQ/2) /
(1.15 X RQ/5) (0.85 X RQ/5)
-5
5
-5
5
-5
5
-5
5
UNITS
NOTES
V
V
V
V
V
V
V
mA
1
1, 4
1, 4, 5
1–3, 8
9, 10
1, 4
1, 4
6, 7, 11
mA
6, 7, 11
µA
µA
µA
µA
NOTE:
1. All voltages referenced to VSS (GND).
2. Typically the value of VREF is expect to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in
VDDQ.
3. Peak-to-peak AC noise on VREF must not exceed ±2% VREF(dc).
4. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2.
Undershoot: VIL(AC) ≥ -0.5V for t ≤ tCK/2.
During normal operation, VDDQ must not exceed VDD.
Control input signals may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
5. VDDQ can be set to a nominal 1.5V + 0.1V or 1.8V + 0.1V supply
6. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the
device.
7. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
8. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise (non-common mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2, VREF is allowed
±2%VDDQ/2 for DC error and an additional ±2%VDDQ/2 for AC noise. This measurement is to be taken at the nearest
VREF bypass capacitor.
9. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
10. On-die termination may be selected using mode register bit 9 (see Figure 10 on page 16). A resistance RTT from each
data input signal to the nearest VTT can be enabled. RTT = 150Ω (± 10%) at 70°C TC.
11. For VOL and VOH, refer to the Spice Model fro the RLDRAM II Command Driver.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 20: AC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
CONDITIONS
SYMBOL
MIN
MAX
UNITS
Matched Impedance Mode
Matched Impedance Mode
VIH
VIL
VREF + 0.2
VSSQ - 0.3
VDDQ + 0.3
VREF - 0.2
V
V
CONDITIONS
SYMBOL
MIN
MAX
UNITS
TA = 25°C; f = 1 MHz
CI
CO
CCK
1.5
3.5
2.0
2.5
5.0
3.0
pF
pF
pF
Table 21: Capacitance
DESCRIPTION
Address/Control Input Capacitance
Input/Output Capacitance (D and Q)
Clock Capacitance
Figure 41: Output Test Conditions
Figure 42: Input Waveform
VTT
VDDQ
VIH(AC) MIN
50Ω
DQ
VSWING
VIL(AC) MAX
Test point
GND
10pF
Rise Time:
2 V/ns
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MT49H8M18C_2.fm - Rev. F 11/04 EN
42
Fall Time:
2 V/ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Table 22: IDD Operating Conditions and Maximum Limits
+0°C ≤ Tc ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise note.
MAX
DESCRIPTION
Standby
Current
CONDITIONS
t
CK = Idle
All banks idle, no inputs toggling
SYMBOL
-25
-33
-5
UNIT
ISB1 (VDD)
ISB1 (VEXT)
ISB2 (VDD)
ISB2 (VEXT)
48
26
288
26
48
26
288
26
48
26
288
26
mA
mA
Active Standby
Current
= MIN, CS# = 1
No commands, address/data change up
to once every four clock cycles
Incremental
Current
BL = 2, tCK = MIN, tRC = MIN,
1 bank active, half address changes
once per tRC, read followed by write
sequence
IDD1 (VDD)
IDD1 (VEXT)
348
41
305
36
255
36
mA
Incremental
Current
BL = 4, tCK = MIN, tRC = MIN,
1 bank active, half address changes
once per tRC, read followed by write
sequence
IDD2 (VDD)
IDD2 (VEXT)
352
48
319
42
269
42
mA
Incremental
Current
BL = 8, tCK = MIN, tRC = MIN,
1 bank active, half address changes
once per tRC, read followed by write
sequence
IDD3 (VDD)
IDD3 (VEXT)
408
55
368
48
286
48
mA
Burst
Refresh Current
tCK
= MIN, tRC = MIN
Cyclic bank refresh, data inputs are
switching
IREF1 (VDD)
IREF1 (VEXT)
680
133
530
111
367
105
mA
Distributed
Refresh Current
tCK
= MIN, tRC = MIN
Single bank refresh, half address/data
toggle
IREF2 (VDD)
IREF2 (VEXT)
325
48
267
42
221
42
mA
Operating Supply
Current Example
BL = 2, tCK = MIN, tRC = MIN, cyclic bank IDD2W (VDD)
access, half of address bits change every IDD2W (VEXT)
clock cycle, continuous data
BL = 4, tCK = MIN, tRC = MIN, cyclic bank IDD4W (VDD)
access, half of address bits change every IDD4W (VEXT)
two clock cycles, continuous data
BL = 8, tCK = MIN, tRC = MIN, cyclic bank IDD8W (VDD)
access, half of address bits change every IDD8W (VEXT)
four clock cycles, continuous data
970
100
819
90
597
69
mA
779
65
609
55
439
44
mA
668
60
525
51
364
40
mA
Operating Supply
Current Example
Operating Supply
Current Example
tCK
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MT49H8M18C_2.fm - Rev. F 11/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Figure 43: 144-Ball FBGA
10.70 CTR
10º TYP
SEATING PLANE
0.10 C
2.40 CTR
C
0.05 MAX
0.555 ±0.050
144X ∅ 0.45
DIMENSIONS APPLY TO SOLDER
BALLS POST REFLOW. THE
PRE-REFLOW BALL DIAMETER IS
0.50MM ON A 0.40MM SMD BALL PAD.
8.80
0.125 ±0.025
0.39 ±0.05
0.80 TYP
BALL A1 ID
BALL A1 ID
BALL A1
BALL A12
1.00 TYP
18.50 ±0.10
17.00
8.50 ±0.05
17.90 CTR
9.25 ±0.05
4.40 ±0.05
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2%Ag
5.50 ±0.05
11.00 ±0.10
NOTE:
1. All dimensions in millimeters.
Data Sheet Designation
No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are subject to
change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
RLDRAM is a trademark of Infineon Technologies AG in various countries, and is used by Micron under license from Infineon.
All other trademarks are the property of their respective owners.
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MT49H8M18C_2.fm - Rev. F 11/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.