Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) FEATURES 74F323 PIN CONFIGURATION • Common parallel I/O for reduced pin count • Additional serial inputs and outputs for expansion • Four operating modes: Shift left, shift right, load, and store • 3-State outputs for bus-oriented applications S0 1 20 VCC OE0 2 19 S1 OE1 3 18 DS7 I/O6 4 17 Q7 DESCRIPTION I/O4 5 16 I/O7 The 74F323 is an 8-bit universal shift/storage register with 3-State outputs. Its function is similar to the 74F299 with the exception of synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin counts. Separate serial inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. Four modes of operation are possible: Hold (store), shift left, shift right, and parallel load. I/O2 6 15 I/O5 I/O0 7 14 I/O3 Q0 8 13 I/O1 SR 9 12 CP GND 10 11 DS0 SF00888 The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load, and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F323 115MHz 55mA ORDERING INFORMATION A Low signal on SR overrides the Select and inputs and allows the flip-flops to be reset by the next rising edge of clock. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed. ORDER CODE A High signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F323N 20-pin plastic SOL N74F323D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW DS0 Serial data input for right shift 1.0/1.0 20µA/0.6mA DS7 Serial data input for left shift 1.0/1.0 20µA/0.6mA S0, S1 Mode select inputs 1.0/2.0 20µA/1.2mA CP Clock pulse input (Active rising edge) 1.0/1.0 20µA/0.6mA SR Synchronous Reset input (Active Low) 1.0/1.0 20µA/0.6mA OE0, OE1 Output Enable input (Active Low) 1.0/1.0 20µA/0.6mA Q0, Q7 Serial outputs 50/33 20µA/20mA Multiplexed parallel data inputs or 3.5/1.0 70µA/0.6mA 150/40 3.0mA/24mA I/On 3-State parallel outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state. 1990 Mar 01 1 853-0367 98987 Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) LOGIC SYMBOL 74F323 LOGIC SYMBOL (IEEE/IEC) 11 SRG8 18 9 2 DS0 4R & 1 S0 1 0 19 S1 19 1 12 CP 12 9 SR 2 OE0 3 11 7 OE1 Q0 3EN13 3 DS7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 16 17 13 M 0 3 C4/1→ /2← 8 1, 4D 3, 4D 5, 13 Z5 3, 4D 6, 13 Z6 6 VCC = Pin 20 GND = Pin 10 8 7 13 6 14 5 15 4 14 SF00889 5 15 4 16 3, 4D 18 12, 13 2, 4D Z12 17 SF00890 FUNCTION TABLE INPUTS OEn H L X ↑ = = = = SR S1 S0 CP OPERATING MODE L L X X ↑ Synchronous Reset; Q0 - Q7 = Low L H H H ↑ Parallel load; I/On → Qn L H L H ↑ Shift right; DS0 → Q0, Q0 → Q1, etc. L H H L ↑ Shift left; DS7 → Q7, Q7 → Q6, etc. L H L L X Hold H X X X X Outputs disabled (3-state) High voltage level Low voltage level Don’t care Low-to-High clock transition 1990 Mar 01 2 Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) 74F323 LOGIC DIAGRAM DS7 18 OE0 2 3 D S0 SR Q7 16 I/O7 4 I/O6 15 I/O5 5 I/O4 14 I/O3 6 I/O2 13 I/O1 CP OE1 S1 17 19 Q 1 9 CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D DS0 CP 7 I/O0 11 8 12 VCC = Pin 20 GND = Pin 10 1990 Mar 01 Q Q0 SF00883 3 Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) 74F323 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature –0.5 to +5.5 V Q0, Q7 40 mA I/On 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current Q0, Q7 –1 mA I/On –3 mA IOL Low-level output current Q0, Q7 20 mA I/On 24 mA Tamb Operating free-air temperature range 70 °C 1990 Mar 01 0 4 V V Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) 74F323 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL Q0, Q7 VOH High-level output voltage I/On VOL Low-level output voltage VIK Input clamp voltage II Input current at maximum input voltage IIH High-level input current IIL Low-level input current IIH + IOZH Off-state output current, High-level voltage applied IIL + IOZL Off-state output current Low-level voltage applied IOS Short-circuit output current3 ICC Supply current (total) LIMITS TEST CONDITIONS1 PARAMETER VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN IOH = –1mA IOH = –3mA IOL = MAX MIN ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC ±5%VCC VCC = MIN, II = IIK TYP2 MAX UNIT V 3.4 V V 3.4 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V others VCC = MAX, VI = 7.0V 100 µA I/On VCC = 5.5V, VI = 5.5V 1 mA except I/On VCC = MAX, VI = 2.7V 20 µA –1.2 mA –0.6 mA VCC = MAX, VO = 2.7V 70 µA VCC = MAX, VO = 0.5V –0.6 mA –150 mA 55 75 mA 65 90 mA S0, S1 others I/On only VCC = MAX, VI = 0.5V VCC = MAX ICCH ICCL VCC = MAX –60 ICCZ 55 85 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb =+ 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1990 Mar 01 5 Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) 74F323 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS I/O Waveform 1 Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MIN TYP 70 100 70 MAX MHz 85 115 85 MHz fMAX Maximum clock frequency tPLH tPHL Propagation delay CP to Q0 or Q7 Waveform 1 4.0 3.5 6.0 6.0 8.5 8.5 3.5 4.5 9.5 9.5 ns ns tPLH tPHL Propagation delay CP to I/On Waveform 1 4.0 5.0 6.0 6.5 9.0 9.5 4.0 4.0 10.0 10.0 ns ns tPZH tPZL Output Enable time Sn, OE to I/On Waveform 3 Waveform 4 3.5 4.0 6.0 8.0 9.0 11.0 3.5 4.0 10.0 11.5 ns ns tPHZ tPLZ Output Disable time Sn, OE to I/On Waveform 3 Waveform 4 2.5 1.5 5.0 3.0 7.5 5.5 2.5 1.5 8.0 6.5 ns ns Qn AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITIONS MIN ts(H) ts(L) Setup time, High or Low S0 or S1 to CP th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 2 6.5 6.5 7.5 7.5 ns Hold time, High or Low S0 or S1 to CP Waveform 2 0 0 0 0 ns ts(H) ts(L) Setup time, High or Low I/O0, DS0 or DS7 to CP Waveform 2 3.5 3.5 4.0 4.0 ns th(H) th(L) Hold time, High or Low I/O0, DS0 or DS7 to CP Waveform 2 0 0 0 0 ns ts(H) ts(L) Setup time, High or Low SR to CP Waveform 2 7.0 7.0 8.5 8.5 ns th(H) th(L) Hold time, High or Low SR to CP Waveform 2 0 0 0 0 ns tw(H) tw(L) CP Pulse width, High or Low Waveform 1 3.5 3.5 4.0 4.0 ns 1990 Mar 01 6 Philips Semiconductors Product specification 8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State) 74F323 AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. S0, S1, DSL, DSR, I/On, SR 1/fMAX CP VM VM ts(H) VM tW(H) tW(L) CP tPHL VM VM th(H) ts(L) VM VM th(L) VM tPLH Q0, Q7, I/On VM VM SF00885 Waveform 2. Data, Select and Reset Setup and Hold Times SF00884 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Sn, OEn VM Sn, OEn VM tPZH VM tPZL VOH -0.3V tPHZ I/On VM tPLZ I/On VM VM 0V VOL +0.3V SF00887 SF00886 Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1990 Mar 01 7