ETC NT256D64S8HA0G-8B

NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
184pin Two Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 16Mx8 SDRAM
Features
• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
Also aligns QFC transitions with clock during Read cycles
• Performance :
• Address and control signals are fully synchronous to positive
PC1600
Speed Sort
DIMM CAS Latency
f CK Clock Frequency
- 8B
clock edge
PC2100
- 75B
- 7K
2
2.5
2
100
133
133
• Programmable Operation:
Unit
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
MHz
t CK Clock Cycle
10
7.5
7.5
ns
f DQ DQ Burst Frequency
200
266
266
MHz
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Intended for 100 MHz and 133 MHz applications
• Auto Refresh (CBR) and Self Refresh Modes
• Inputs and outputs are SSTL-2 compatible
• Automatic and controlled precharge commands
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• 12/10/2 Addressing (row/column/bank)
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
• 15.6 µs Max. Average Periodic Refresh Interval
• Module has two physical banks
• Gold contacts
• Differential clock inputs
• SDRAMs in 66-pin TSOP Type II Package
• Serial Presence Detect
• Data is read or written on both clock edges
Description
NT256D64S8HA0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a dual-bank high-speed memory array. The 32Mx64 module is a two-bank DIMM that uses sixteen 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 and / or CKE1
controls all devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number
Speed
Organization
Leads
Power
32Mx64
Gold
2.5V
143MHz (7ns @ CL = 2.5 )
NT256D64S8HA0G-7K
PC2100
133MHz (7.5ns @ CL= 2 )
133MHz (7.5ns @ CL= 2.5 )
NT256D64S8HA0G -75B
PC2100
100MHz (10ns @ CL = 2 )
125MHz (8ns @ CL = 2.5 )
NT256D64S8HA0G -8B
PC1600
100MHz (10ns @ CL = 2 )
Preliminary
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Pin Description
CK0, CK1, CK2
Differential Clock Inputs
CK0 , CK1 , CK2
DQ0-DQ63
Data input/output
CKE0, CKE1
Clock Enable
DQS0-DQS7,
RAS
Row Address Strobe
DQS9-DQS16
CAS
Column Address Strobe
VDD
Power (2.5V)
WE
Write Enable
VDDQ
Supply voltage for DQs(2.5V)
S0 , S1
Chip Selects
VSS
Ground
A0-A9, A11
Address Inputs
NC
No Connect
Bidirectional data strobes
A10/AP
Address Input/Autoprecharge
SCL
Serial Presence Detect Clock Input
BA0, BA1
SDRAM Bank Address Inputs
SDA
Serial Presence Detect Data input/output
VREF
Ref. Voltage for SSTL_2 inputs
SA0-2
Serial Presence Detect Address Inputs
VDDID
VDD Identification flag.
VDDSPD
Serial EEPROM positive power supply(2.5V)
Pinout
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
1
VREF
93
VSS
32
A5
124
VSS
62
VDDQ
154
Back
RAS
2
DQ0
94
DQ4
33
DQ24
125
A6
63
WE
155
DQ45
3
VSS
95
DQ5
34
VSS
126
DQ28
64
DQ41
156
VDDQ
4
DQ1
96
VDDQ
35
DQ25
127
DQ29
65
CAS
157
S0
5
DQS0
97
DQS9
36
DQS3
128
VDDQ
66
VSS
158
S1
6
DQ2
98
DQ6
37
A4
129
DQS12
67
DQS5
159
DQS14
7
VDD
99
DQ7
38
VDD
130
A3
68
DQ42
160
VSS
8
DQ3
100
VSS
39
DQ26
131
DQ30
69
DQ43
161
DQ46
9
NC
101
NC
40
DQ27
132
VSS
70
VDD
162
DQ47
10
NC
102
NC
41
A2
133
DQ31
71
NC
163
NC
11
VSS
103
NC
42
VSS
134
NC
72
DQ48
164
VDDQ
12
DQ8
104
VDDQ
43
A1
135
NC
73
DQ49
165
DQ52
13
DQ9
105
DQ12
44
NC
136
VDDQ
74
VSS
166
DQ53
14
DQS1
106
DQ13
45
NC
137
CK0
75
CK2
167
NC
15
VDDQ
107
DQS10
46
VDD
138
CK0
76
CK2
168
VDD
16
CK1
108
VDD
47
NC
139
VSS
77
VDDQ
169
DQS15
17
CK1
109
DQ14
48
A0
140
NC
78
DQS6
170
DQ54
18
VSS
110
DQ15
49
NC
141
A10
79
DQ50
171
DQ55
19
DQ10
111
CKE1
50
VSS
142
NC
80
DQ51
172
VDDQ
20
DQ11
112
VDDQ
51
NC
143
VDDQ
81
VSS
173
NC
21
CKE0
113
NC
52
BA1
144
NC
82
VDDID
174
DQ60
22
VDDQ
114
DQ20
83
DQ56
175
DQ61
23
DQ16
115
NC
53
DQ32
145
VSS
84
DQ57
176
VSS
24
DQ17
116
VSS
54
VDDQ
146
DQ36
85
VDD
177
DQS16
25
DQS2
117
DQ21
55
DQ33
147
DQ37
86
DQS7
178
DQ62
26
VSS
118
A11
56
DQS4
148
VDD
87
DQ58
179
DQ63
KEY
KEY
27
A9
119
DQS11
57
DQ34
149
DQS13
88
DQ59
180
VDDQ
28
DQ18
120
VDD
58
VSS
150
DQ38
89
VSS
181
SA0
29
A7
121
DQ22
59
BA0
151
DQ39
90
NC
182
SA1
30
VDDQ
122
A8
60
DQ35
152
VSS
91
SDA
183
SA2
31
DQ19
123
DQ23
61
DQ40
153
DQ44
92
SCL
184
VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
Preliminary
2
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Input/Output Functional Description
Symbol
Type
CK0 , CK1, CK2
(SSTL)
CK0 , CK1 , CK2
(SSTL)
CKE0, CKE1
(SSTL)
Function
Polarity
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
edge of their associated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to the
Edge
Active
High
on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
(SSTL)
Active
Low
RAS , CAS , WE
(SSTL)
Active
Low
VREF
Supply
VDDQ
Supply
BA0, BA1
(SSTL)
S0 , S1
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock, RAS , CAS , WE define the
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
A0 - A9
A10/AP
A11
(SSTL)
-
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63,
(SSTL)
-
DQS0 - DQS7
DQS9 - DQS16
(SSTL)
Active
High
VDD , VSS
Supply
-
SDA
-
SCL
-
Preliminary
Supply
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
SA0 – SA2
VDDSPD
Data and Check Bit input/output pins operate in the same manner as on conventional
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pullup.
Serial EEPROM positive power supply.
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Functional Block Diagram ( 2 Bank, 16Mx8 DDR SDRAMs )
S1
S0
DQS0
DQS9
DQS4
DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D8
DQS1
DQS10
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D12
DQS5
DQS14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
DQS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DQS2
DQS11
DQS
D5
DQS
D13
DQS6
DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
DQS
D2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
DQS3
DQS12
DQS
D6
DQS
D14
DQS7
DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BA0-BA1
CS
D3
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
A0 - A11 : SDRAMs D0 -D15
RAS
RAS : SDRAMs D0 -D15
CAS
CAS : SDRAMs D0 -D15
CKE0
CKE0 : SDRAMs D0 -D7
CKE1
WE : SDRAMs D8 -D15
WE
WE : SDRAMs D0 -D15
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
BA0 - BA1 : SDRAMs D0 -D15
A0-A11
Notes :
1.
2.
3.
4.
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
VDDQ
VDD
VREF
VSS
VDDID
D0 - D15
D0 - D15
D0 - D15
D0 - D15
DQS
D7
DQS
D15
CK0
120 ohm
SDRAM x 4
120 ohm
SDRAM x 6
120 ohm
SDRAM x 6
CK0
CK1
Strap: see Note 4
CK1
Serial PD
SCL
WP
CK2
A0
A1
A2
SA0
SA1
SA2
SDA
CK2
DQ-to-I/O wring may be changed within a byte.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22 Ohms.
VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
Preliminary
4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Absolute Maximum Ratings
Symbol
VIN, VOUT
Parameter
Voltage on I/O pins relative to Vss
Rating
Units
-0.5 to VDDQ+0.5
V
VIN
Voltage on Input relative to Vss
-0.5 to +3.6
V
VDD
Voltage on VDD supply relative to Vss
-0.5 to +3.6
V
Voltage on VDDQ supply relative to Vss
-0.5 to +3.6
V
0 to+70
°C
VDDQ
TA
TSTG
PD
IOUT
Operating Temperature (Ambient)
-55 to +150
°C
Power Dissipation
Storage Temperature (Plastic)
16
W
Short Circuit Output Current
50
mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Symbol
Max.
Units
Notes
Input Capacitance: CK0, CK0 , CK1, CK1 , CK2, CK2
CI1
24
pF
1
Input Capacitance: A0-A11, BA0, BA1, WE , RAS , CAS
CI2
60
pF
1
Input Capacitance: CKE0, CKE1, S0 , S1
CI3
30
pF
1
Parameter
CIO1
14
pF
1,2
Input/Output Capacitance DQ0-63; DQS0-7, 9-16
1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, T A = 25 °C, V OUT (DC) = VDDQ/2 , VOUT (Peak to Peak) = 0.2V.
2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at
the board level.
Preliminary
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
DC Electrical Characteristics and Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Min
Max
Units
Notes
Supply Voltage
2.3
2.7
V
1
I/O Supply Voltage
2.3
2.7
V
1
0
0
V
/O Reference Voltage
0.49 x VDDQ
0.51 x VDDQ
V
1,2
I/O Termination Voltage (System)
VREF – 0.04
VREF + 0.04
V
1,3
VIH(DC)
Input High (Logic1) Voltage
VREF + 0.15
VDDQ + 0.3
V
1
VIL(DC)
Input Low (Logic0) Voltage
-0.3
VREF - 0.15
V
1
VIN(DC)
Input Voltage Level, CK and CK Inputs
-0.3
VDDQ + 0.3
V
1
VID(DC)
Input Differential Voltage, CK and CK Inputs
0.30
V DDQ + 0.6
V
1,4
-5
5
µA
1
-5
5
µA
1
-16.8
-
mA
1
16.8
-
mA
1
VDD
VDDQ
VSS , VSSQ
VREF
VTT
Parameter
Supply Voltage, I/O Supply Voltage
Input Leakage Current
II
Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V)
Output Leakage Current
IOZ
(DQs are disabled; 0V ≤ Vout ≤ VDDQ
Output High Current
IOH
(VOUT = VDDQ -0.373V, min VREF , min VTT )
Output Low Current
IOL
(VOUT = 0.373, max VREF , max VTT )
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,
and must track variations in the DC level of VREF .
4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
Preliminary
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS .
2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or
to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC) unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.
AC Output Load Circuits
VTT
50 ohms
Output
Timing Reference Point
VOUT
30 pF
AC Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
VIH(AC)
Input High (Logic 1) Voltage.
VREF + 0.31
-
V
1, 2
VIL(AC)
Input Low (Logic 0) Voltage.
-
VREF ?
- 0.31
V
1, 2
VID(AC)
Input Differential Voltage, CK and CK Inputs
0.62
VDDQ + 0.6
V
1, 2, 3
VIX(AC)
Input Differential Pair Cross Point Voltage, CK and CK Inputs
(0.5*VDDQ ) - 0.2
(0.5*VDDQ ) +?0.2
V
1, 2, 4
1. Input skew rate = 1V/ ns .
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same.
Preliminary
7
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Operating, Standby, and Refresh Currents
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
PC1600
PC2100
Unit
Notes
1000
1160
mA
1,2
1120
1360
mA
1,2
240
240
mA
1,2
480
560
mA
1,2
240
240
mA
1,2
800
960
mA
1,2
1640
1800
mA
1,2
1320
1680
mA
1,2
t RC = t RFC (MIN)
1840
2400
mA
1,2
t RC = 15.625 µs
252
252
mA
1,2,4
32
32
mA
1,2,3
Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;
I DD0
tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current : one bank; active / read / precharge; Burst = 2;
I DD1
tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;
address and control inputs changing once per clock cycle
I DD2P
I DD2N
I DD3P
Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)
Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE >= VIH(MIN) ;
tCK = tCK (MIN) ; address and control inputs changing once per clock cycle
Active Power-Down Standby Current : one bank active;
power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)
Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;
I DD3N
CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS
inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current : one bank; Burst = 2; reads; continuous burst;
I DD4R
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
tCK = tCK (MIN) ; IOUT = 0mA
Operating Current : one bank; Burst = 2; writes; continuous burst;
I DD4W
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
tCK = tCK (MIN)
I DD5
Auto-Refresh Current :
I DD6
Self-Refresh Current : CKE ≤ ?
0.2V
1. I DD specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns .
3. Enables on-chip refresh and address counters.
4. Current at 15.625 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 15.625 µs.
Preliminary
8
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
-7K
Parameter
-75B
-8B
Unit
Notes
+0.8
ns
1,2,3,4
+0.8
ns
1,2,3,4
0.45
0.55
tCK
1,2,3,4
Min.
Max.
Min.
Max.
Min.
Max.
DQ output access time from CK/ CK
-0.75
+0.75
-0.75
+0.75
-0.8
DQS output access time from CK/ CK
-0.75
+0.75
-0.75
+0.75
-0.8
tCH
CK high-level width
0.45
0.55
0.45
0.55
tCL
CK low-level width
tAC
tDQSCK
tCK
tCK
Clock cycle time
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1,2,3,4
CL=2.5
7
12
7.5
12
8
12
ns
1,2,3,4
CL=2
7.5
12
10
12
10
12
ns
1,2,3,4
tDH
DQ and DM input hold time
0.5
0.5
0.6
ns
tDS
DQ and DM input setup time
0.5
0.5
0.6
ns
DQ and DM input pulse width (each input)
1.75
1.75
2
ns
tDIPW
tHZ
tLZ
tDQSQ
tDQSQA
Data-out high-impedance time from
CK/ CK
Data-out low-impedance time from
CK/ CK
tHP
tQH
tDQSS
tDQSL,H
tDSS
tDSH
tMRD
tWPRES
+0.8
ns
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
0.6
ns
1,2,3,4
0.6
ns
1,2,3,4
tCK
1,2,3,4
tCK
1,2,3,4
tCK
1,2,3,4
0.5
0.5
0.5
tCH
0.5
tCH
or
or
or
tCL
tCL
tCL
tHP -
tHP -
tHP -
0.75ns
0.75ns
1.0ns
0.75
1.25
0.75
1.25
0.75
1.25
4, 5
0.35
0.35
tCK
1,2,3,4
0.2
0.2
0.2
tCK
1,2,3,4
0.2
0.2
0.2
tCK
1,2,3,4
Mode register set command cycle time
14
15
16
ns
1,2,3,4
Write preamble setup time
0
0
0
ns
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
0.40
tWPRE
Write preamble
0.25
0.25
0.25
tCK
0.9
1.1
1.1
ns
tIH
1, 2, 3,
0.35
(write cycle)
Write postamble
tIS
4, 5
tCH
tWPST
tIH
1, 2, 3,
-0.8
cycle; defined by clk high(tCH )
DQS input low (high) pulse width
1,2,3,4
+0.75
or clk low (tCL ) time
transition
,15,16
-0.75
DQS-DQ skew (DQS & all DQ signals)
Write command to 1st DQS latching
1,2,3,4
+0.75
signals)
Data output hold time from DQS
,15,16
-0.75
DQS-DQ skew (DQS & associated DQ
Minimum half clk period for any given
1,2,3,4
Address and control input hold time
(fast slew rate)
Address and control input setup time
(fast slew rate)
Address and control input hold time
(slow slew rate)
Preliminary
0.60
0.40
0.60
0.40
0.60
tCK
1, 2, 3,
4, 7
1, 2, 3,
4, 6
1,2,3,4
2, 3, 4,
9, 11,
12
2, 3, 4,
0.9
1.1
1.1
ns
9, 11,
12
2, 3, 4,
1.0
1.1
1.1
ns
10, 11,
12, 14
9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
Symbol
Parameter
-7K
Min.
-75B
Max.
Min.
-8B
Max.
Min.
Max.
Unit
-
ns
2, 3, 4,
10, 11,
12, 14
2, 3, 4,
12
0.9
1.1
tCK
1,2,3,4
0.60
0.40
0.60
tCK
1,2,3,4
120,000
50
120,000
ns
1,2,3,4
Address and control input setup time
tIS
1.0
1.0
2.2
1.1
ns
(slow slewrate)
tIPW
Input pulse width
2.2
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tRPST
Read postamble
0.40
0.60
0.40
tRAS
Active to Precharge command
45
120,000
45
Active to Active/Auto-refresh
tRC
Notes
65
65
70
ns
1,2,3,4
75
75
80
ns
1,2,3,4
20
20
20
ns
1,2,3,4
20
20
20
ns
1,2,3,4
20
20
20
ns
1,2,3,4
15
15
15
ns
1,2,3,4
15
(tWR/
tCK )
+
15
(tWR/
tCK )
+
15
(tWR/
tCK )
+
ns
1,2,3,4
command period
Auto-refresh to Active/Auto-refresh
tRFC
command period
tRCD
Active to Read or Write delay
Active to Read Command with
tRAP
Autoprecharge
tRP
Precharge command period
Active bank A to Active bank B
tRRD
command
tWR
Write recovery time
Auto precharge write recovery +
tDAL
precharge time
tWTR
Internal write to read command delay
1, 2, 3,
tCK
4, 13
(tRP/
(tRP /
(tRP /
tCK )
tCK )
tCK )
1
1
1
tCK
1,2,3,4
75
75
80
ns
1,2,3,4
200
200
200
tCK
1,2,3,4
1, 2, 3,
Exit self-refresh to non-read
tXSNR
command
tXSRD
Exit self-refresh to read command
tREFI
Average Periodic Refresh Interval
Preliminary
15.6
15.6
15.6
µs
4, 8
10
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross: the input reference level for
signals other than CK/ CK , is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS .
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
11. CK/ CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system
clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate
Delta ( tIS )
?
Delta ( tIH )
Unit
Note
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+50
0
ps
1,2
0.3 V/ns
+100
0
ps
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly
for rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
1,2
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate
Delta ( tDS )
Delta ( tDH )
Unit
Note
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+75
+75
ps
1,2
0.3 V/ns
+150
+150
ps
1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for
rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate
Delta ( tDS )
Delta ( tDH )
Unit
Note
0.0 ns/V
0
0
ps
1,2,3,4
0.25 ns/V
+50
+50
ps
1,2,3,4
0.5 ns/V
+100
+100
ps
1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly
for rising transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
Preliminary
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Serial PD Data Entry
SPD Entry Value
Description
-7K
(Hexadecimal)
-75B
-8B
-7K
-75
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM DDR
07
3
Number of Row Addresses on Assembly
12
0C
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank
2
02
6.
Data Width of Assembly
X64
40
7
Data Width of Assembly (cont’)
X64
00
8
Voltage Interface Level of this Assembly
9
SDRAM Device Cycle Time at CL=2.5
10
SDRAM Device Access Time from Clock at CL=2.5
11
DIMM Configuration Type
12
Refresh Rate/Type
13
Primary SDRAM Width
X8
08
14
Error Checking SDRAM Device Width
N/A
00
1 Clock
01
2,4,8
0E
15
SSTL 2.5V
Note
-8B
04
7ns
7.5ns
8ns
70
75
80
0.75ns
0.75ns
0.8ns
75
75
80
SDRAM Device Attributes :
Minimum Clock Delay, Random Column Access
Non-Parity
00
15.6µs / SR
80
16
SDRAM Device Attributes: Burst Length Supported
17
SDRAM Device Attributes: Number of Device Banks
18
SDRAM Device Attributes: CAS Latency
19
SDRAM Device Attributes: CS Latency
20
SDRAM Device Attributes: WE Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
23
Minimum Clock Cycle at CL=2
7.5ns
24
Maximum Data Access Time from Clock at CL=2
25
Minimum Clock Cycle Time at CL=1
26
Maximum Data Access Time from Clock at CL=1
27
Minimum Row Precharge Time (tRP)
20ns
20ns
20ns
50
50
50
28
Minimum Row Active to Row Active delay (tRRD)
15ns
15ns
15ns
3C
3C
3C
29
Minimum RAS to CAS delay (tRCD)
20ns
20ns
20ns
50
50
50
30
Minimum RAS Pulse Width (tRAS)
45ns
45ns
50ns
2D
2D
32
31
Module Bank Density
32
Address and Command Setup Time Before Clock
0.9ns
0.9ns
1.1ns
90
90
B0
33
Address and Command Hold Time After Clock
0.9ns
0.9ns
1.1ns
90
90
B0
34
Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
50
50
60
35
Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
50
50
60
36-61
4
2, 2.5
SPD Revision
63
Checksum Data
2, 2.5
0C
01
1
02
Differential Clock
20
10ns
0C
00
10ns
75
± 0.8ns
75
N/A
A0
A0
75
80
00
N/A
00
128MB
20
Undefined
0
0C
0
± 0.75ns ± 0.75ns
Reserved
62
04
2, 2.5
00
0
0
00
00
00
6D
9D
23
64-71
Manufacturer’s JEDED ID Code
0B
7F7F7F0B00000000
72
Module Manufacturing Location
N/A
00
73-90
Module Part number
91-92
Module Revision Code
93-94
Module Manufacturing Data
95-98
Module Serial Number
N/A
99-255 Reserved
1.
yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2.
ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
Preliminary
N/A
N/A
00
00
N/A
00
Year / Week Code
yy/ww
Serial Number
00
Undefined
00
00
1,2
12
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Package Dimensions
FRONT
133.35
5.25
17.80
0.700
31.75
1.250
10.0
0.394
(2x)4.00
0.157
128.95
5.077
0.098
Detail A
3.0
0.118
θ 2.50
Detail B
Side
BACK
3.99
0.157 max.
1.27+/- 0.10
0.050 +/- 0.004
Detail B
3.80
0.150
4.00
0.157
Detail A
1.00 Width
0.039
6.35
0.250
1.27 Pitch
0.05
1.80
0.071
Note : All dimensions are typical unless otherwise stated.
Unit :
Preliminary
Millimeters
Inches
13
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.