NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM 184pin Low Profile Registered DDR SDRAM MODULE Based on 32Mx8 DDR SDRAM Features • 184-Pin 1U Registered 8-Byte Dual In-Line Memory Module one-half clock post-amble • 32Mx72 Double Data Rate (DDR) SDRAM DIMM • Address and control signals are fully synchronous to positive • Performance: clock edge PC1600 Speed Sort • Programmable Operation: PC2100 - Device CAS Latency: 2, 2.5 Unit -8B -75B -7K 3 3.5 3 f CK Clock Frequency 100 133 133 MHz t CK Clock Cycle 10 7.5 7.5 ns f DQ DQ Burst Frequency 200 266 266 MHz * DIMM CAS Latency - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write • Auto Refresh (CBR) and Self Refresh Modes • Automatic and controlled precharge commands • Intended for 100 MHz and 133 MHz applications • 13/10/1 Addressing (row/column/bank) • Inputs and outputs are SSTL-2 compatible • 7.8 µs Max. Average Periodic Refresh Interval • VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2 • Serial Presence Detect • SDRAMs have 4 internal banks for concurrent operation • Gold contacts • Differential clock inputs • SDRAMs in 66-pin TSOP Type II Package • Data is read or written on both clock edges • Bi-directional data strobe with one clock cycle preamble and * One clock cycle added for registered DIMMs to account for input register. Description NT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint. The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to 266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. Clock enable CKE0 controls all devices on the DIMM. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number NT256D72S89AKGU-7K NT256D72S89AKGU-75B NT256D72S89AKGU-8B Speed 143MHz (7ns @ CL = 2.5) 133MHz (7.5ns @ CL= 2) 133MHz (7.5ns @ CL= 2.5) 100MHz (10ns @ CL = 2) 125MHz (8ns @ CL = 2.5) REV 0.2 (Preliminary) 09/2002 100MHz (10ns @ CL = 2) DDR266A PC2100 DDR266B PC2100 DDR200 PC1600 Organization Leads Power 32Mx72 Gold 2.5V 1 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Pin Description CK0, CK0 Differential Clock Inputs DQ0-DQ63 Data input/output CKE0 Clock Enable CB0-CB7 Check Bit Data Input/Output RAS Row Address Strobe DQS0-DQS17 Bidirectional data strobes CAS Column Address Strobe VDD Power (2.5V) WE Write Enable VDDQ Supply voltage for DQs(2.5V) S0 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Autoprecharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output RESET Reset pin SA0-2 Serial Presence Detect Address Inputs VREF Ref. Voltage for SSTL_2 inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply(2.5V) Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin 1 VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 Back RAS 2 DQ0 33 DQ24 63 WE 94 DQ4 125 A6 155 DQ45 3 VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ 4 DQ1 35 DQ25 65 CAS 96 VDDQ 127 DQ29 157 S0 5 DQS0 36 DQS3 66 VSS 97 DQS9 128 VDDQ 158 NC 6 DQ2 37 A4 67 DQS5 98 DQ6 129 DQS12 159 DQS14 7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS 8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 RESET 41 A2 71 NC 102 NC 133 DQ31 163 NC 11 VSS 42 VSS 72 DQ48 103 NC 134 CB4 164 VDDQ 12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52 13 DQ9 44 CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53 14 DQS1 45 CB1 75 NC 106 DQ13 137 CK0 167 NC 15 VDDQ 46 VDD 76 NC 107 DQS10 138 CK0 168 VDD 16 NC 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DQS15 17 NC 48 A0 78 DQS6 109 DQ14 140 DQS17 170 DQ54 18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55 19 DQ10 50 VSS 80 DQ51 111 NC 142 CB6 172 VDDQ 20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKE0 52 BA1 82 VDDID 113 NC 144 CB7 174 DQ60 83 DQ56 114 DQ20 84 DQ57 115 A12 22 VDDQ 23 DQ16 KEY 53 DQ32 KEY 145 VSS 175 DQ61 176 VSS DQS16 24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62 26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63 27 A9 57 DQ34 88 DQ59 119 DQS11 149 DQS13 180 VDDQ 28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0 29 A7 59 BA0 90 NC 121 DQ22 151 DQ39 182 SA1 30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2 31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD REV 0.2 (Preliminary) 09/2002 2 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Input/Output Functional Description Symbol CK0 CK0 CKE0 Type (SSTL) (SSTL) (SSTL) Function Polarity Positive Edge The positive line of the differential pair of system clock inputs which drives the input to the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising edge of their associated clocks. Negative The negative line of the differential pair of system clock inputs which drives the input to Edge Active High the on-DIMM PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the S0 (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE (SSTL) VREF Supply VDDQ Supply BA0, BA1 (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, A0 - A9 A10/AP A11, A12 AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write (SSTL) - cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63, (SSTL) - DQ0 – DQ63 CB0 – CB7 (SSTL) Active High VDD, VSS Supply DQS0 – DQS17 RESET SA0 – SA2 - SCL Supply REV 0.2 (Preliminary) 09/2002 DRAMs. Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and (SSTL) Data strobe for input and output data Positive Edge Active (LVC-MOS) Low Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA V DDSPD Data and Check Bit input/output pins operate in the same manner as on conventional This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply. 3 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Functional Block Diagram (1 Bank, 32Mx8 DDR SDRAMs) RS0 DQS0 DQS9 DQS4 DQS13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 CS DQS D4 DQS5 DQS14 DQS1 DQS10 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 CS DQS D5 DQS6 DQS15 DQS2 DQS11 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQS3 DQS12 CS DQS D6 DQS7 DQS16 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 CS DQS D7 DQS8 DQS17 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S0 BA0-BA1 A0-A12 RAS CAS CKE0 WE R E G I S T E R PCK PCK Notes : CS D8 RS0 RBA0-RBA1 RA0-RA12 RRAS RCAS RCKE0 RWE Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4 VDDSPD VDDQ VDD VREF VSS VDDID CS : SDRAMs D0-D8 BA0-BA1 : SDRAMs D0-D8 A0-A12 : SDRAMs D0-D8 RAS : SDRAMs D0-D8 CAS : SDRAMs D0-D8 CKE : SDRAMs D0-D8 WE : SDRAMs D0-D8 Serial PD RESET SCL WP A0 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/CS relationships are maintained as shown. 3. DQ/DQS resistors are 22 Ohms. 4. VDDID strap connections (for memory device VDD,VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ 5. Address and control resistors are 22 Ohms. REV 0.2 (Preliminary) 09/2002 DQS SA0 A1 A2 SA1 SA2 SDA CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams 4 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Serial Presence Detect -- Part 1 of 2 32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD SPD Entry Value Byte Description DDR266A DDR266B -7K 0 -75B Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Serial PD Data Entry (Hexadecimal) Note DDR200 -8B DDR266A DDR266B -7K -75B 128 80 256 08 SDRAM DDR 07 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 11 0A 5 Number of DIMM Bank 1 01 6. Data Width of Assembly X72 48 X72 00 SSTL 2.5V 04 7 Data Width of Assembly (cont’) 8 Voltage Interface Level of this Assembly 9 10 DDR SDRAM Device Cycle Time at CL=2.5 DDR SDRAM Device Access Time from Clock at CL=2.5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 14 15 16 17 18 7.5ns 8ns 70 75 80 0.75ns 0.75ns 0.8ns 75 75 80 ECC 02 82 Primary DDR SDRAM Width X8 08 Error Checking DDR SDRAM Device Width X8 08 1 Clock 01 2, 4, 8 0E 4 04 DDR SDRAM Device Attr: Min CLk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks Latencies Supported 2/2.5 2/2.5 2/2.5 0C 0C 19 DDR SDRAM Device Attributes: CS Latency 0 01 20 DDR SDRAM Device Attributes: WE Latency 1 02 21 DDR SDRAM Device Attributes: 22 DDR SDRAM Device Attributes: General 23 24 25 26 27 28 Minimum Clock Cycle at CL=2 Maximum Data Access Time from Clock at CL=2 Differential Clock, PLL, REGISTER 26 +/-0.2V Voltage Tolerance 00 10ns 10ns 75 A0 A0 0.75ns 0.75ns 0.8ns 75 75 80 Minimum Clock Cycle Time at CL=1 CL=1 Minimum Row Precharge Time (tRP) (tRRD) 0C 7.5ns Maximum Data Access Time from Clock at Minimum Row Active to Row Active delay -8B 7ns 7.8us / SR DDR SDRAM Device Attributes: CAS DDR200 N/A 00 N/A 00 20ns 20ns 20ns 50 50 50 15ns 15ns 15ns 3C 3C 3C 29 Minimum RAS to CAS delay (tRCD) 20ns 20ns 20ns 50 50 50 30 Minimum RAS Pulse Width (tRAS) 45ns 45ns 50ns 2D 2D 32 31 Module Bank Density 32 33 Address and Command Setup Time Before Clock Address and Command Hold Time After Clock 512MB 40 0.9ns 0.9ns 1.1ns 90 90 B0 0.9ns 0.9ns 1.1ns 90 90 B0 34 Data Input Setup Time Before Clock 0.5ns 0.5ns 0.6ns 50 50 60 35 Data Input Hold Time After Clock 0.5ns 0.5ns 0.6ns 50 50 60 Initial 00 00 00 A7 D7 5D 36-61 Reserved 62 SPD Revision 63 Checksum Data REV 0.2 (Preliminary) 09/2002 Undefined Initial Initial 00 5 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Serial Presence Detect -- Part 2 of 2 32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD SPD Entry Value Byte Description DDR266A DDR266B -7K 64-71 Manufacturer’s JEDEC ID Code 72 Module Manufacturing Location 73-90 Module Part number 91-92 Module Revision Code 93-94 Module Manufacturing Data 95-98 Module Serial Number 99-255 Reserved -75B DDR266A DDR266B -7K N/A 00 00 00 Year/Week Code yy/ww Serial Number 00 Undefined 00 ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) Note -8B 00 N/A N/A 2. DDR200 -75B 7F7F7F0B00000000 N/A N/A yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) 09/2002 -8B NANYA 1. REV 0.2 (Preliminary) Serial PD Data Entry (Hexadecimal) DDR200 00 1, 2 6 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Absolute Maximum Ratings Symbol VIN, VOUT Voltage on I/O pins relative to Vss Rating Units -0.5 to VDDQ+0.5 V VIN Voltage on Input relative to Vss -0.5 to +2.7 V VDD Voltage on VDD supply relative to Vss -0.5 to +2.7 V Voltage on VDDQ supply relative to Vss -0.5 to +2.7 V 0 to +70 °C -55 to +150 °C Power Dissipation 18 W Short Circuit Output Current 50 mA VDDQ TA TSTG PD IOUT Note: Parameter Operating Temperature (Ambient) Storage Temperature (Plastic) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Symbol Max. Units Notes Input Capacitance: CK0, CK0 CI1 7 pF 1 Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS, CKE0, S0 CI2 7 pF 1 Input Capacitance: RESET CI3 7 pF 1 Input Capacitance: SA0-SA2, SCL CI4 9 pF 1 CIO1 10 pF 1, 2 Parameter Input/Output Capacitance DQ0-63; DQS0-17, CB0-7 CIO3 11 pF Input/Output Capacitance: SDA 1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. 2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV 0.2 (Preliminary) 09/2002 7 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Min Max Units Notes Supply Voltage 2.3 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF – 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF- 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6 V 1, 4 -5 5 uA 1 -5 5 uA 1 -16.8 - mA 1 16.8 - mA 1 VDD VDDQ VSS, VSSQ VREF VTT II Parameter Supply Voltage, I/O Supply Voltage Input Leakage Current Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) Output Leakage Current IOZ (DQs are disabled; 0V ≤ Vout ≤ VDDQ Output High Current IOH (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current IOL (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 0.2 (Preliminary) 09/2002 8 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Parameter/Condition Min Max Unit Notes VIH (AC) Input High (Logic 1) Voltage. V REF + 0.31 - V 1, 2 VIL (AC) Input Low (Logic 0) Voltage. - V REF - 0.31 V 1, 2 VID (AC) Input Differential Voltage, CK and CK Inputs 0.7 V DDQ + 0.6 V 1, 2, 3 VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs (0.5*VDDQ) - 0.2 (0.5*VDDQ) + 0.2 V 1, 2, 4 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 0.2 (Preliminary) 09/2002 9 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Operating, Standby, and Refresh Currents (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Parameter/Condition PC2100 PC1600 Unit Notes (-7K/-75B) (-8K) TBD TBD mA 1, 2 TBD TBD mA 1, 2 TBD TBD mA 1, 2 TBD TBD mA 1, 2 TBD TBD mA 1, 2 TBD TBD mA 1, 2 TBD TBD mA 1, 2 TBD TBD mA 1, 2 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK I DD0 (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC I DD1 (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle I DD2P I DD2N I DD3P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ I DD3N VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address I DD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address I DD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) I DD5 Auto-Refresh Current: tRC = tRFC (MIN) TBD TBD mA 1, 2, 4 I DD6 Self-Refresh Current: CKE ≤ 0.2V TBD TBD mA 1, 2 TBD TBD mA 1, 2 Operating Current: four bank; four bank interleaving with BL = 4, address I DD7 and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Enables on-chip refresh and address counters. 4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs. REV 0.2 (Preliminary) 09/2002 10 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2) Symbol -7K Parameter -75B -8B Min. Max. Min. Max. Min. Max. Unit Notes tAC DQ output access time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1-4 tDQSCK DQS output access time from CK/CK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1-4 tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4 CL=2.5 7 12 7.5 12 8 12 ns 1-4 CL=2 7.5 12 10 12 10 12 ns 1-4 tCK tCK Clock cycle time 1-4, tDH DQ and DM input hold time 0.5 0.5 0.6 ns tDS DQ and DM input setup time 0.5 0.5 0.6 ns 1.75 1.75 2 ns 1-4 tDIPW tHZ tLZ tDQSQ tDQSQA tHP tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRES DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK +0.75 -0.75 +0.75 -0.8 +0.8 ns 1-4, 5 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1-4, 5 DQ signals) DQS-DQ skew (DQS & all DQ signals) 1-4 0.5 0.5 0.6 ns 1-4 tCK 1-4 tCK 1-4 tCK 1-4 tCH or or or clk low (tCL ) time tCL tCL tCL transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time tHP - tHP - tHP - 0.75ns 1.0ns 0.75 Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) REV 0.2 (Preliminary) 0.75 1.25 0.75 1.25 0.35 0.35 tCK 1-4 0.2 0.2 0.2 tCK 1-4 0.2 0.2 0.2 tCK 1-4 14 15 16 ns 1-4 0 0 0 ns 1-4, 7 tCK 1-4, 6 0.25 (fast slew rate) 1.25 0.35 0.40 Address and control input hold time tCH 0.75ns Write postamble 09/2002 ns or Write preamble tIH 0.6 tCH tWPRE tIS 0.5 cycle; defined by clk high (tCH ) tWPST tIH 0.5 Minimum half clk period for any given Write command to 1st DQS latching 1-4, 15, 16 -0.75 DQS-DQ skew (DQS & associated Data output hold time from DQS 15, 16 0.60 0.40 0.25 0.60 0.40 0.25 0.60 tCK 1-4 2-4, 0.9 1.1 1.1 ns 9, 11, 12 2-4, 0.9 1.1 1.1 ns 9, 11, 12 2-4, 1.0 1.1 1.1 ns 10-12, 14 11 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2) Symbol tIS Parameter Address and control input setup time (slow slewrate) -7K Min. -75B Max. Min. -8B Max. 1.0 1.0 1.1 2.2 tRPRE Read preamble 0.9 1.1 0.9 1.1 tRPST Read postamble 0.40 0.60 0.40 tRAS Active to Precharge command 45 120,000 45 tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tPDEX tXSNR command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Power down exit time Exit self-refresh to non-read command tXSRD Exit self-refresh to read command tREFI Average Periodic Refresh Interval REV 0.2 (Preliminary) 09/2002 Unit Notes ns 10-12, 14 Input pulse width Active to Active/Auto-refresh Max. 2-4, tIPW tRC Min. 2.2 2-4, - ns 0.9 1.1 tCK 1-4 0.60 0.40 0.60 tCK 1-4 120,000 50 120,000 ns 1-4 12 65 65 70 ns 1-4 75 75 80 ns 1-4 20 20 20 ns 1-4 20 20 20 ns 1-4 20 20 20 ns 1-4 15 15 15 ns 1-4 1-4 15 15 15 ns (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) tCK 1 1 1 tCK 1-4 7.5 7.5 8 ns 1-4 75 75 80 ns 1-4 200 200 200 tCK 1-4 µs 1-4, 8 7.8 7.8 7.8 1-4, 13 12 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate Delta (tIS) Delta (tIH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate Delta (tDS) Delta (tDH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 0.2 (Preliminary) 09/2002 13 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Package Dimensions FRONT 128.95 5.077 10.0 0.394 Register 43.33 1.700 131.35 5.171 (2X) 4.00 0.157 133.35 5.250 Detail B 17.80 0.700 Detail A Θ 2.5 0.098 2.3 0.091 PLL BACK SIDE 3.99 0.157 max. 4.24 0.167 (Front) Register 3.80 0.15 1.27 0.050 Detail B 4.00 0.157 Detail A 1.80 0.071 1.00 Width 0.039 1.27 Pitch 0.050 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 0.2 (Preliminary) 09/2002 14 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256D72S89AKGU 256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM Revision Log Rev Date Modification 0.1 08/2002 Preliminary Release 0.2 09/2002 Added tPDEX (Power down exit time) to AC Timing Table REV 0.2 (Preliminary) 09/2002 15 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.