P4C164/164L P4C164/P4C164L ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Output Enable and Dual Chip Enable Control Functions High Speed (Equal Access and Cycle Times) – 8/10/12/15/20/25 ns (Commercial) – 10/12/15/20/25/35 (Industrial) – 12/15/20/25/35/45 ns (Military) Single 5V±10% Power Supply Data Retention with 2.0V Supply, 10 µA Typical Current (P4C164L Military) Low Power Operation – 770mW Active –15 – 660/743 mW Active – 20 – 495/575 mW Active – 25, 35, 45 – 193/220 mW Standby (TTL Input) – 5.5mW Standby (CMOS Input) P4C164L (Military) Common Data I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 600 mil Ceramic DIP – 28-Pin 350 x 550 mil LCC – 28-Pin CERPACK DESCRIPTION The P4C164 and P4C164L are 65,536-bit ultra high-speed static RAMs organized as 8K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained with supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. In full standby mode with CMOS inputs, power consumption is only 5.5 mW for the P4C164L. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS ••• ••• ••• INPUT DATA CONTROL COLUMN I/O I/O 8 COLUMN SELECT CE 1 CE 2 WE A2 4 25 A3 5 24 A12 A 11 A4 6 23 3 WE CE 2 A0 26 VCC 3 A1 WE 27 28 26 1 25 NC A3 4 A4 6 24 A 12 A A10 A5 7 23 A 10 A6 A7 8 22 9 21 OE A9 A5 7 22 OE A6 8 21 A9 A7 9 20 A8 10 19 I/O1 I/O2 11 18 CE1 I/O 8 I/O 7 12 17 I/O 6 I/O3 13 16 GND 14 15 I/O 5 I/O 4 2 5 A8 10 20 I/O 1 11 19 I/O 2 12 13 14 15 16 18 17 CE 2 11 CE 1 I/O8 I/O7 1519C 1519B DIP (P5, D5-2, D5-1), SOJ (J5) CERPACK (F4) SIMILAR TOP VIEW •••••• 1519A OE V CC 27 I/O6 I/O 1 28 2 I/O5 A7 1 A0 A1 I/O3 •••••• 65,536-BIT MEMORY ARRAY ROW SELECT NC GND I/O4 A0 A2 The P4C164 and P4C164L are available in 28-pin 300 mil DIP and SOJ, 28-pin 600 mil ceramic DIP, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities. A8 A12 1519B LCC (L5) TOP VIEW Means Quality, Service and Speed 1Q97 91 P4C164/164L MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature GND VCC 0V 0V 0V 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% Military –55°C to +125°C –40°C to +85°C Industrial Commercial 0°C to +70°C Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter Conditions Typ. Unit CIN Input Capacitance VIN = 0V 5 pF COUT Output Capacitance VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = 18 mA VOL Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current VOH ILI –0.5(3) –0.5(3) IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. ISB1 –0.5(3) 0.8 V V 0.2 V –1.2 –1.2 V 0.4 0.4 V 0.2 2.4 –0.5(3) V 2.4 –10 –5 +10 +5 –5 n/a +5 n/a µA –10 –5 +10 +5 –5 n/a +5 n/a µA Standby Power Supply CE ≥ VIH or Mil. Current (TTL Input Levels) CE2 ≤VIL, VCC= Max Ind./Com’l. f = Max., Outputs Open ___ ___ 40 ___ ___ 40 n/a mA CE ≥ VHC or Mil. CE2 ≤VLC, VCC= Max Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ___ ___ 25 ___ ___ 1 n/a mA VCC = Max. Mil. Output Leakage Current Com’l. VCC = Max., CE = VIH, VOUT = GND to VCC ISB 0.8 P4C164L Unit Min Max 2.2 VCC +0.5 V VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 VIN = GND to VCC ILO P4C164 Min Max VCC +0.5 2.2 Test Conditions Standby Power Supply Current (CMOS Input Levels) Mil. Com’l. 30 15 n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 92 P4C164/164L POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Temperature Range Commercial Parameter Dynamic Operating Current* Industrial Military Unit –8 200 –10 180 –12 170 –15 160 –20 155 –25 150 –35 N/A –45 N/A N/A 190 180 170 160 155 150 N/A mA N/A N/A 180 170 160 155 150 145 mA mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH DATA RETENTION CHARACTERISTICS (P4C164L, Military Temperature Only) Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Min Typ.* VCC= 2.0V 3.0V Max VCC= 2.0V 3.0V 2.0 CE1 ≥ VCC – 0.2V or CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V V 10 15 200 tRC = Read Cycle Time † This parameter is guaranteed but not tested. tRC§ ns DATA RETENTION MODE 4.5V VDR ≥ 2V t CDR CE 1 CE 2 4.5V tR VDR VHC VHC VLC VLC 93 µA ns DATA RETENTION WAVEFORM VCC 300 0 *TA = +25°C § Unit P4C164/164L AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -8 -10 -12 -15 -20 -25 -35 -45 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 8 10 12 15 20 25 35 45 ns tAC Chip Enable Access Time 8 10 12 15 20 25 35 45 ns tOH Output Hold from Address Change 3 3 3 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z 5 6 7 8 8 10 15 20 ns tOE Output Enable Low to Data Valid 5 6 7 9 10 13 18 20 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time Chip Disable to Power Down Time tPD 8 12 10 2 2 2 5 0 15 2 6 7 0 0 8 10 20 2 9 0 12 2 9 0 15 35 25 12 ns 20 15 20 ns ns 0 0 20 ns 2 2 0 20 45 25 ns OE CONTROLLED)(5) READ CYCLE NO. 1 (OE t RC (9) ADDRESS t AA OE t OE t OH t OLZ (8) CE 1 CE 2 t AC t LZ t OHZ(8) (8) t HZ(8) DATA OUT Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 94 P4C164/164L READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) t RC (9) ADDRESS t AA t OH PREVIOUS DATA VALID DATA OUT DATA VALID CE1, CE2 CONTROLLED)(5,7,10) READ CYCLE NO. 3 (CE tRC CE 1 CE 2 (8,10) t AC (10) t HZ (8,10) t LZ DATA VALID DATA OUT (10) I CC VCC SUPPLY CURRENT HIGH IMPEDANCE t PD(10) t PU I SB Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. 95 P4C164/164L AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -8 -10 -12 -15 -25 -20 -35 -45 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 8 10 12 15 20 25 35 45 ns tCW Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write 6 7 8 12 15 18 25 33 ns 7 8 10 12 15 18 25 33 ns 0 0 0 0 0 0 0 0 ns 7 8 9 12 15 18 20 25 ns 0 0 0 0 0 0 0 0 ns 6 7 8 9 11 13 15 20 ns 0 0 0 0 0 0 0 0 ns tAW tAS tWP tAH tDW tDH Date Hold Time tWZ Write Enable to Output in High Z tOW Output Active 3 from End of Write 6 7 7 3 3 7 3 8 3 10 3 14 3 18 3 ns ns WE CONTROLLED)(11) WRITE CYCLE NO. 1 (WE t WC (14) ADDRESS t CW CE 1 CE 2 t AW t WR t AH t WP WE t AS t DW DATA IN DATA VALID t OW(8,13) (8) t WZ DATA OUT t DH (12) DATA UNDEFINED HIGH IMPEDANCE Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. 96 P4C164/164L CE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE t WC (14) ADDRESS t AS t CW CE 1 t AH t WR t AW CE 2 t WP WE t DW DATA IN t DH DATA VALID (12) DATA OUT(11) HIGH IMPEDANCE AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels Mode GND to 3.0V CE1 CE2 OE WE I/O Power Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V Standby X L X X High Z Standby Output Timing Reference Level 1.5V DOUT Disabled L H H H High Z Active Read L H L H DOUT Active Write L H X L High Z Active Output Load See Figures 1 and 2 +5V R TH = 166.5 Ω 480Ω D OUT DOUT 255Ω 30pF* (5pF* for t HZ ,t t LZ , OHZ VTH = 1.73 V 30pF* (5pF* for t , HZ ,t ,t LZ , OHZ, t OLZ , t WZ and t OW ) tOLZ, tWZ and t OW ) Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C164/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 97 P4C164/164L PACKAGE SUFFIX Package Suffix P J D DW L F TEMPERATURE RANGE SUFFIX Temperature Range Suffix Description Plastic DIP, 300 mil wide standard Plastic SOJ, 300 mil wide standard CERDIP, 300 mil wide CERDIP, 600 mil wide Leadless Chip Carrier (ceramic) CERPACK Description C Commercial Temperature Range, 0°C to +70°C. Industrial Temperature Range, –40˚C to +85˚C. Military Temperature Range, –55°C to +125°C. Mil. Temp. with MIL-STD-883 Class B compliance. I M MB ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4C 164 I – ss p t Temperature Range: C, I, M Package Code: P, J, D, DW, L Speed (Access /Cycle Time): 10,12, etc. Low Power Designation: Blank = None, L = Low Device Number: 164 Static RAM Prefix The P4C164 is also available to SMD-5962-38294 SELECTION GUIDE The P4C164 is available in the following temperature, speed and package options. The P4C164L is available only over the military temperature range. Temp. Range Speed Package 8 10 12 15 20 25 35 45 Com'l Plastic DIP Plastic SOJ -8PC -8JC -10PC -10JC -12PC -12JC -15PC -15JC -20PC -20JC -25PC -25JC N/A N/A N/A N/A Ind. Plastic DIP Plastic SOJ N/A N/A -10PI -10JI -12PI -12JI -15PI -15JI -20PI -20JI -25PI -25JI -35PI -35JI N/A N/A Mil. Temp. CERDIP (300 mil) CERDIP (600 mil) LCC CERPACK N/A N/A N/A N/A N/A N/A N/A N/A -12DM -12DWM -12LM -12FM -15DM -15DWM -15LM -15FM -20DM -20DWM -20LM -20FM -25DM -25DWM -25LM -25FM -35DM -35DWM -35LM -35FM -45DM -45DWM -45LM -45FM Military Proc'd* CERDIP (300 mil) CERDIP (600 mil) LCC CERPACK N/A N/A N/A N/A N/A N/A N/A N/A -35DMB -12DMB -15DMB -20DDMB -25DMB -12DWMB -15DWMB -20DWMB -25DWMB -35DWMB -35LMB -12LMB -15LMB -20LMB -25LMB -35FMB -12FMB -15FMB -20FMB -25FMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not available 98 -45DMB -45DWMB -45LMB -45FMB