PHILIPS P87CL883T

INTEGRATED CIRCUITS
DATA SHEET
P8xCL883; P8xCL884
TELX microcontrollers for CT0
handset/basestation applications
Product specification
Supersedes data of 1997 Aug 18
File under Integrated Circuits, IC17
1999 Mar 15
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING INFORMATION
5.1
5.2
Pinning
Pin description
6
FUNCTIONAL DESCRIPTION
6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.2
6.4
6.5
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.9
6.9.1
6.9.2
6.9.3
Special Function Registers (SFRs)
I/O facilities
Ports
Port I/O configuration
Alternative Port Function Register (ALTP)
Timer/event counters
Timer T2
Timer/Counter 2 Control Register (T2CON)
MSK modem
Watchdog Timer
OTP programming
OTP programming by a programmer
In-System Programming mode
Oscillator circuitry
Resonator requirements
Recommended resonator types
Emulation
Non-conformance
Programming interface/ Transparent mode
Low Voltage Detection
Edge detection on UART
7
LIMITING VALUES
8
CHARACTERISTICS
9
PACKAGE OUTLINE
10
SOLDERING
10.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
10.2
10.3
10.4
10.5
11
DEFINITIONS
12
LIFE SUPPORT APPLICATIONS
13
PURCHASE OF PHILIPS I2C COMPONENTS
2
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
1
P8xCL883; P8xCL884
FEATURES
• Full static 80C51 CPU; enhanced 8-bit architecture with:
– Minimum 6 cycles per instruction (twice as fast as a
standard 80C51 core)
– Non-page oriented instructions
• I2C-bus interface for serial transfer on two lines,
maximum 400 kHz
– Direct addressing
– Four 8-byte RAM register banks
– Stack depth limited only by available internal RAM
(maximum 256 bytes)
• Very low current consumption
– Multiply, divide, subtract and compare instructions.
• Frequency: 3.58 MHz
• Single supply voltage: 2.7 to 3.6 V
• 8-bit ports:
• Operating temperature: −25 to +70°C
• 28 pin SO package.
– P8xCL883: 3 (19 I/O lines)
– P8xCL884: 3 (18 I/O lines).
• Program Memory:
2
– P8xCL883/P8xCL884: 8-kbyte One Time
Programmable (OTP).
GENERAL DESCRIPTION
The P8xCL883/P8xCL884 are manufactured in an
advanced CMOS technology. The P8xCL883 is based on
single-chip technology and the P8xCL884 is based on
MCM (Multi-Chip-Module) technology as the EEPROM is
integrated on a separate chip.
• 256-byte RAM
• 128-byte EEPROM Data Memory, accessed internally
via I2C-bus interface (P8xCL884 only)
• Amplitude Controlled Oscillator (ACO) suitable for
quartz crystal or ceramic resonator
The P8xCL883/P8xCL884 are 8-bit microcontrollers
especially suited for low cost analog cordless telephone
applications (CT0, CT1, CT1+ standards). For this
purpose, features like DTMF, EEPROM, MSK modem and
POR/LVD are integrated on-chip.
• Improved Power-on/Power-off reset (POR) circuitry
• Low Voltage Detection (LVD) with 11 software
programmable levels
The device is optimized for low power consumption.
The P8xCL883/P8xCL884 have two software selectable
features for power reduction: Idle and Power-down modes.
In addition, all derivative blocks can switch off their clock if
they are inactive.
• Eight interrupts on Port 1:
– Edge or level sensitive triggering selectable via
software
– Power-saving use for keyboard control.
• Twenty source, twenty vector interrupt structure with two
priority levels
The instruction set of the P8xCL883/P8xCL884 is based
on that of the 80C51. The P8xCL883/P8xCL884 also
function as an arithmetic processor having facilities for
both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over
100 instructions: 49 one-byte, 46 two-byte, and
16 three-byte. Due to the missing port P2, there is no
external data or memory access and the MOVX operations
cannot be used.
• Wake-up from Power-down mode via LVD or external
interrupts at Port 1
• DTMF generator (P8xCL884 only)
• MSK modem including Manchester encoder/decoder
with 2 digital outputs for analog cordless telephones
(standards CT0/CT1/CT1+)
• Two standard 16-bit timer/event counters
This data sheet details the specific properties of the
P8xCL883/P8xCL884; for details of the
P8xCL883/P8xCL884 core and the derivative functions
see the “TELX family” data sheet and “Data Handbook
IC20; 80C51-based 8-bit Microcontrollers”.
• Additional 16-bit timer/event counter with Capture,
Compare and Auto-reload function
• Watchdog Timer
• Full duplex enhanced UART with double buffering
3
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
3
P8xCL883; P8xCL884
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
OTP TYPE
NAME
P87CL883T/000
Blank OTP
P87CL884T/000
P87CL883T/xxx
SO28
DESCRIPTION
plastic small outline package; 28 leads;
body width 7.5 mm
Factory-programmed OTP
P87CL884T/xxx
P83CL883T/xxx
Pre-programmed OTP
P83CL884T/xxx
4
VERSION
SOT136-1
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CPU
VPP
DATA
MEMORY
PROGRAM
MEMORY
OTP/ROM
ACO
VSS
TX_MUTE (6)
TONE (1)
MOUT0 (3)
DTMF
MSK MODEM
MOUT1
RAM
MOUT2
P87CL883
P87CL884
(5)
8-bit
internal bus
TELX microcontrollers for CT0
handset/basestation applications
TWO 16-BIT
TIMER/
EVENT
COUNTERS
(T0, T1)
XTAL1
XTAL2
CLK (2)
VDD
INT2 to INT9 (2)
8
BLOCK DIAGRAM
T0 (4)
MIN
Philips Semiconductors
4
RX_MUTE (6)
5
LVD
SERIAL
UART
PORT
P0
P3 (7) TXD (4)
T2 (2)
Only available on the P8xCL884.
Alternative functions of Port 1.
MOUT0 is the alternative function of P3.1.
Alternative functions of Port 3; T0 is only available on the P8xCL883.
In-circuit OTP programming.
By software, any I/O pin can be used.
Port 3: P3.0, P3.1 and P3.4; P3.4 is only available on the P8xCL883.
SDA (2) SCL (2)
T2COMP (2)
Fig.1 Block diagram.
WATCHDOG
TIMER
(T3)
RST
POR
PORENABLE
MBK981
Product specification
(1)
(2)
(3)
(4)
(5)
(6)
(7)
P1
T2EX (2)
I2C-BUS
INTERFACE
P8xCL883; P8xCL884
RXD (4)
EEPROM (1)
handbook, full pagewidth
PARALLEL
I/O PORTS
16-BIT
TIMER/EVENT
COUNTER WITH
CAPTURE/
COMPARE
(T2)
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
5
5.1
P8xCL883; P8xCL884
PINNING INFORMATION
Pinning
handbook, halfpage
P0.5
1
28 PORENABLE/VPP
P0.6
2
27 P0.4
P0.7
3
26 P0.3
P3.0/RXD/data
4
25 P0.2
P3.1/TXD/clock/MOUT0
5
24 P0.1
RST
6
23 P0.0
MIN
7
MOUT1
8
MOUT2
9
P83CL883 22 P1.7/INT9/SDA
P83CL884
21 P1.6/INT8/SCL
P87CL883
P87CL884 20 P3.4/T0 or TONE(1)
XTAL1 10
19 P1.5/INT7
XTAL2 11
18 P1.4/INT6/CLK
P1.0/INT2/T2 12
17 P1.3/INT5
P1.1/INT3/T2EX 13
16 P1.2/INT4/T2COMP
VDD 14
15 VSS
MBK005
(1) Pin 20: P3.4/T0 on the P8xCL883; TONE on the P8xCL884.
Fig.2 Pin configuration.
6
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
5.2
P8xCL883; P8xCL884
Pin description
SYMBOL
PIN
DESCRIPTION
RST
6
Active LOW reset. A LOW level on this pin for two machine cycles while the
oscillator is running, resets the device. The RST pin is also an output which can be
used to reset other ICs.
MIN
7
Digital MSK modem input.
MOUT1
8
Digital MSK modem outputs.
MOUT2
9
XTAL1
10
Crystal input. Input to the Amplitude Controlled Oscillator. Also the input for an
externally generated clock source.
XTAL2
11
Crystal output. Output of the Amplitude Controlled Oscillator. To be left
unconnected when an external oscillator clock is used.
VDD
14
Power supply.
VSS
15
Ground.
P0.0 to P0.7
23 to 27,
1 to 3
Port 0. 8-bit bidirectional I/O port. Every port pin can be used as open-drain,
standard port, high-impedance input or push-pull output, according to Section 6.2.
P1.0/INT2/T2
12
P1.1/INT3/T2EX
13
P1.2/INT4/T2COMP
16
Port 1. 8-bit bidirectional I/O port with alternative functions. Every port pin except
P1.6 and P1.7 (I2C-bus pins) can be used as open-drain, standard port,
high-impedance input or push-pull output, according to Section 6.2. Port P1.3 has
LED drive capability.
P1.3/INT5
17
P1.4/INT6/CLK
18
P1.5/INT7
19
P1.6/INT8/SCL
21
P1.7/INT9/SDA
22
P3.0/RXD/data
4
P3.1/TXD/clock/
MOUT0
5
P3.4/T0
20
Port 3 also serves the alternative functions: RXD/data is the serial port receiver
data input (asynchronous) or data I/O (synchronous); TXD/clock is the serial port
transmitter data output (asynchronous) or clock output (synchronous) or digital
MSK modem output MOUT0; T0 is an external input for Timer 0.
P3.4/T0 is only available on the P8xCL883.
TONE
20
DTMF output; TONE is only available on the P8xCL884.
PORENABLE/VPP
28
PORENABLE. Power-on reset circuit enable. If PORENABLE = 1, the internal
Power-on reset circuit is enabled. If external reset circuitry is used, it is
recommended to keep PORENABLE = 0 to reach lowest power consumption. This
pin is also used for the OTP programming voltage VPP.
Port 1 also serves the alternative functions: INT2 to INT9 interrupts; Timer T2
external inputs T2 and T2EX; Timer T2 compare output T2COMP; external clock
output CLK; I2C-bus clock SCL and data in/outputs SDA.
Port 3. 3 or 2-bit bidirectional I/O port with alternative functions. Every port pin can
be used as open-drain, standard port, high-impedance input or push-pull output,
according to Chapter 6.2.
7
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6
P8xCL883; P8xCL884
FUNCTIONAL DESCRIPTION
6.1
Special Function Registers (SFRs)
Table 1
List of SFRs
REGISTER
ADDRESS
(HEX)
RESET VALUE(1)
ADDRESS
(HEX)
RESET VALUE(1)
T2CON
C8
0000 0000
REGISTER
80C51 core
ACC
E0
0000 0000
TH2
CD
0000 0000
B
F0
0000 0000
TL2
CC
0000 0000
DPL
82
0000 0000
EEPROM interface
DPH
83
0000 0000
EECON
FB
0000 0000
PCH
no SFR
0000 0000
DTMF
PCL
no SFR
0000 0000
HGF
A2
0000 0000
PCON
87
0000 0000
LGF
A1
0000 0000
PRESC
F3
0000 0000
PSW
D0
0000 0000
SP
81
0000 0111
IEN0
A8
0000 0000
IEN1
E8
0000 0000
IEN2
F1
0000 0000
TCON
88
0000 0000
IP0
B8
0000 0000
TH0
8C
0000 0000
IP1
F8
0000 0000
TH1
8D
0000 0000
IP2
F9
0000 0000
TL0
8A
0000 0000
ISE1
E1
0000 0000
TL1
8B
0000 0000
IX1
E9
0000 0000
TMOD
89
0000 0000
IRQ1
C0
0000 0000
ALTP
A3
0000 0000
F2
0000 0000
P0
80
1111 1111
P0CFGA
8E
1111 1111
P0CFGB
8F
0000 0000
E6
XXX0 1000
P1
90
1111 1111
P1CFGA
9E
0011 1111
MCON
D3
0000 0000
P1CFGB
9F
0000 0000
MBUF
D1
XXXX XXXX
D2
XX00 0000
Interrupt logic
T0/T1
Port
LVD
LVDCON
POR/ACO
RSTAT
MSK
P3
B0
XXX1 XX11
MSTAT
P3CFGA
BE
XXX1 XX11
UART
P3CFGB
BF
XXX0 XX00
S0BUF
99
0000 0000
P4
C1
XXXX XXX0
S0CON
98
0000 0000
DB
0000 0000
TIMER2
I2C-bus interface
COMP2H
AB
0000 0000
S1ADR
COMP2L
AA
0000 0000
S1CON
D8
0000 0000
RCAP2H
CB
0000 0000
S1DAT
DA
0000 0000
RCAP2L
CA
0000 0000
S1STA
D9
1111 1000
8
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
REGISTER
ADDRESS
(HEX)
P8xCL883; P8xCL884
Each port consists of a latch (Special Function Registers
P0 to P3), an output driver and input buffer. All ports have
internal pull-ups. Figure 3b shows that the strong
transistor ‘p1’ is turned on for only one oscillator period
after a LOW-to-HIGH transition in the port latch. When on,
it turns on ‘p3’ (a weak pull-up) through the inverter IN1.
This inverter and transistor ‘p3’ form a latch which holds
the logic 1.
RESET VALUE(1)
WDT
WDCON
A5
1010 0101
WDTIM
FF
0000 0000
OTP interface
OAH
D5
X00X XXXX
OAL
D4
XXXX XXXX
ODATA
D6
XXXX XXXX
OISYS
DC
000X 0000
OTEST
D7
0000 0000
Port P1.3 has LED drive capability.
6.2.2
I/O port output configurations are determined by the
settings in port configuration SFRs. There are 2 SFRs for
each port: PnCFGA and PnCFGB, where ‘n’ indicates the
specific port number (0 to 3). One bit in each of the 2 SFRs
relates to the output setting for the corresponding port pin,
allowing any combination of the 2 output types to be mixed
on those port pins. For example, the output type of P1.3, is
controlled by the setting of bit 3 in the SFRs P1CFGA and
P1CFGB.
Reserved locations; do not write
reserved
E7, FD
−
Note
1. Where: X = undefined state or not implemented bit.
6.2
I/O facilities
6.2.1
The port pins may be individually configured via SFRs with
one of the following modes (P1.6 and P1.7 can be
open-drain or high-impedance but never have any diodes
against VDD). These modes are also shown in Fig.3.
PORTS
The P8xCL883/P8xCL884 have 19 and 18 I/O lines
respectively, treated as 19 and 18 individually addressable
bits or as three parallel 8-bit addressable ports.
The alternative functions are detailed below:
Mode 0 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; e.g. Port 0 for external memory
accesses (EA = 0) or access above the built-in
memory boundary. The ESD protection diodes
against VDD and VSS are still present; see Fig.3b.
Except for the I2C-bus pins P1.6 and P1.7, ports
which are configured as open-drain still have a
protection diode to VDD.
Port 0 Offers no alternative functions.
Port 1 Used for a number of special functions:
• P1.0 to P1.7 provides the inputs for the external
interrupts INT2 to INT9
• P1.2/T2COMP for external activation and
Compare/Auto-reload output function of Timer 2
• P1.4/CLK for the clock output
•
PORT I/O CONFIGURATION
Mode 1 Standard port; quasi-bidirectional I/O with
pull-up. The strong pull-up ‘p1’ is turned on for
only two oscillator periods after a LOW-to-HIGH
transition in the port latch. After these two
oscillator periods the port is only weakly driven
through ‘p2’ and ‘very weakly’ driven through ‘p3’
(see Fig.3b).
P1.6/SCL and P1.7/SDA for the I2C-bus interface
are real open-drain outputs or high-impedance;
no other port configurations are available.
Port 2 Not available.
Port 3 Pins can be configured individually to provide:
• P3.0/RXD/data and P3.1/TXD/clock/MOUT0
which are serial port receiver input and
transmitter output (UART)
Mode 2 High-impedance; this mode turns off all output
drivers on a port. Thus, the pin will not source or
sink current and may be used as an input-only pin
with no internal drivers for an external device to
overcome (see Fig.3c).
• P3.4/T0 as counter input; available only in
P8xCL883.
Mode 3 Push-pull; output with drive capability in both
polarities. Under this mode, pins can only be
used as outputs (see Fig.3d).
To enable a Port pin alternative function, the Port bit latch
in its SFR must contain a logic 1.
9
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
Tables 2 and 3 show the configuration register settings for
the 4 port output types.
The electrical characteristics of each output type can be
found in Chapter 8. The default port configuration after
reset is given in Table 3.
Table 2
Port Configuration Registers PnCFGA and PnCFGB (n = 0 to 3) settings
PORT OUTPUT MODE
MODE(1)
PnCFGA
PnCFGB
I2C-BUS PORTS (P1.6 AND P1.7)
NORMAL PORTS
Mode 0
0
0
open-drain
open-drain
Mode 1
1
0
quasi-bidirectional
open-drain
Mode 2
0
1
high-impedance
high-impedance
Mode 3
1
1
push-pull
open-drain
Note
1. Mode changes may cause glitches to occur during transitions. When modifying both registers, WRITE instructions
should be carried out consecutively.
Table 3
Special Function Registers for port configurations/data
REGISTER NAME
SFR ADDRESS (HEX)
STATE AFTER RESET
P0
80
1111 1111
Port P0 configuration A
P0CFGA
8E
1111 1111
Port P0 configuration B
P0CFGB
8F
0000 0000
Port P1 output data(1)
P1
90
1111 1111
Port P1 configuration A
P1CFGA
9E
0011 1111
Port P0 output
data(1)
REGISTER MNEMONIC
Port P1 configuration B
P1CFGB
9F
0000 0000
Port P3 output data(1)
P3
B0
XXX1 XX11(2)
Port P3 configuration A
P3CFGA
BE
XXX1 XX11(2)
Port P3 configuration B
P3CFGB
BF
XXX0 XX00(2)
Notes
1. This means that P0, P1.0 to P1.5 and P3 are initialized in Mode 1 (quasi-bidirectional, driving a weak HIGH) and the
I2C-bus ports P1.6 and P1.7 are initialized in Mode 0 (open-drain, not driven).
2. Port pin P3.4 is only available on P8xCL883.
10
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.2.3
P8xCL883; P8xCL884
ALTERNATIVE PORT FUNCTION REGISTER (ALTP)
This 4-bit register selects the alternative function of certain port pins.
Table 4
Alternative Port Function Register (SFR address A3H)
7
6
5
4
3
2
1
0
−
−
−
−
EMOUT0
ECLK
EMLDY
ETONE
Table 5
Description of ALTP bits
BIT
SYMBOL
DESCRIPTION
7 to 4
−
3
EMOUT0
2
ECLK
If this bit is set, P1.4 is configured to be push-pull, and P1.4 will output the system clock.
1
EMLDY
If this bit is set, P1.5 is configured to be push-pull, and P1.5 will output the digital MLDY
signal of the DTMF generator.
0
ETONE
If this bit is set, the TONE output of the DTMF generator is enabled.
These 4 bits are reserved.
If this bit is set, P3.1 will output the MOUT0 signal.
11
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
handbook, full pagewidth
VDD external
VDD
this diode is not
implemented
on the I2C-bus pins
external
pull-up
I/O pin
Q
from port latch
n
VSS
VSS
MBK004
input data
a. Open-drain.
VDD
strong pull-up
handbook, full pagewidth
1 oscillator
period
p2
p3
p1
I/O pin
Q
from port latch
n
IN1
VSS
VSS
input data
MBK001
b. Standard/quasi-bidirectional.
VDD
handbook, full pagewidth
this diode is not
implemented
on the I2C-bus pins
input data
I/O pin
VSS
MBK002
c. High-impedance.
strong pull-up
handbook, full pagewidth
VDD
VDD
p
I/O pin
Q
from port latch
n
VSS
VSS
input data
MBK003
d. Push-pull.
Fig.3 Port configuration options.
12
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.3
P8xCL883; P8xCL884
6.3.1.1
Timer/event counters
The P8xCL883/P8xCL884 contain three 16-bit timer/event
counters: Timer 0, Timer 1 and Timer 2 which can perform
the following functions:
In the Capture mode, two options may be selected by the
EXEN2 bit in T2CON:
• If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter
which upon overflowing sets the Timer 2 overflow bit
TF2, this may then be used to generate an interrupt.
• Measure time intervals and pulse durations
• Count events
• If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX causes the current
value in TL2 and TH2 to be captured into registers
RCAP2L and RCAP2H respectively. In addition, the
transition at T2EX causes the EXF2 bit in T2CON to be
set; this may also be used to generate an interrupt.
• Generate interrupt requests
• Generate output on comparator match.
In the ‘timer’ mode the register is incremented every
machine cycle.
Since a machine cycle consists of minimum 6 oscillator
periods, the maximum count rate is 1⁄6fosc.
The Capture mode is shown in Fig.4.
In the ‘counter’ mode, the register is incremented in
response to a HIGH-to-LOW transition. Since it takes one
machine cycle (minimum 6 oscillator periods) to recognize
a HIGH-to-LOW transition, the maximum count rate is
1⁄ f
6 osc. To ensure a given level is sampled, it should be held
for at least one complete machine cycle.
6.3.1.2
Compare mode
In the Compare mode, each time timer T2 is incremented,
the contents of the compare registers COMP2H and
COMP2L is compared with the new counter value of
timer T2. When a match occurs, the interrupt flag COMP in
register T2CON and port bit P1.2 are toggled. The 16-bit
value held in these registers is preset by software. The first
toggle after a chip reset will set the flag COMP.
The Compare mode is shown in Fig.4.
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
Mode 0 8-bit timer or 8-bit counter each with
divide-by-32 prescaler.
Mode 1 16-bit time-interval or event counter.
6.3.1.3
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Auto-reload mode
In the Auto-reload mode there are also two options
selected by the EXEN2 bit in T2CON:
Mode 3 Timer 0 establishes TL0 and TH0 as two
separate counters.
• If EXEN2 = 0, then when Timer 2 rolls over, it sets the
TF2 bit but also causes the Timer 2 registers to be
reloaded with the 16-bit value held in registers RCAP2L
and RCAP2H. The 16-bit value held in these registers is
preset by software.
Note that the T0 input is only available on P8xCL883.
6.3.1
Capture mode
TIMER T2
• If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX will also trigger the
16-bit reload and set the EXF2 bit.
Note that the timer T2 of the P8xCL883/P8xCL884
deviates from the timer T2 described in the “TELX
family” data sheet.
Timer T2 is a 16-bit timer/counter that can operate either
as a timer or as an event counter. These functions are
selected by the state of the C/T2 bit in the T2CON register.
Five operating modes are available:
6.3.1.4
Compare with Auto-reload mode
The Auto-reload mode can also be used together with the
Compare mode. The Auto-reload modes are shown in
Fig.5.
• Capture
• Compare
• Auto-reload
6.3.1.5
• Compare with Auto-reload
The Capture and the Compare mode of timer T2 can be
used separately or simultaneously. The function is chosen
via the bits ECOMP, CP/RL2 and TR2 in register T2CON.
• Capture and Compare.
These modes are selected via the T2CON register.
13
Capture and Compare modes
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
handbook, full pagewidth
P8xCL883; P8xCL884
COMP2L
COMP2H
COMPARATOR 1
(16 BITS)
OSC
6
port
P1.2
COMP
C/T2 = 0
TL2
(8 BITS)
C/T2 = 1
T2 pin
ECOMP
TH2
(8 BITS)
TF2
control
TR2
Timer 2
interrupt
capture
transition
detector
RCAP2L
RCAP2H
T2EX pin
EXF2
MBH998
control
EXEN2
Fig.4 Timer 2 in Capture and/or Compare mode.
handbook, full pagewidth
COMP2L
COMP2H
COMPARATOR 1
(16 BITS)
OSC
6
port
P1.2
COMP
C/T2 = 0
TL2
(8 BITS)
T2 pin
ECOMP
C/T2 = 1
TH2
(8 BITS)
TF2
control
TR2
Timer 2
interrupt
reload
transition
detector
RCAP2L
T2EX pin
RCAP2H
EXF2
MBH999
control
EXEN2
Fig.5 Timer 2 in Auto-Reload with/without Compare mode.
14
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.3.2
P8xCL883; P8xCL884
TIMER/COUNTER 2 CONTROL REGISTER (T2CON)
Table 6
Timer/Counter 2 Control Register (SFR address C8H)
7
6
5
4
3
2
1
0
TF2
EXF2
COMP
ECOMP
EXEN2
TR2
C/T2
CP/RL2
Table 7
Description of T2CON bits
BIT
SYMBOL
7
TF2
6
EXF2
Timer 2 external flag. EXF2 is set when either a capture or reload is caused by a
negative transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,
EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. EXF2 must be
cleared by software.
5
COMP
Interrupt flag. When a match between the 16-bit compare register (COMP2L and
COMP2H) and the new counter value of timer T2 occurs, the interrupt flag COMP in
register T2CON and port bit P1.2 are toggled.
4
ECOMP
Enable compare output bit. When set by software, the controller toggles port bit P1.2
(T2COMP) when a compare match occurs.
3
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
2
TR2
Timer 2 start/stop control. Control bit for Timer 2.
1
C/T2
Timer 2 timer or counter select. C/T2 = 0 selects the internal timer with a clock
frequency of 1⁄6fosc. C/T2 = 1 selects the external event counter; negative
edge-triggered.
0
CP/RL2
Table 8
DESCRIPTION
Timer 2 overflow flag. TF2 is set by a Timer 2 overflow and must be cleared by
software.
Capture/reload flag. When set captures will occur on negative transitions at T2EX, if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1.
Timer 2 operating modes
ECOMP
CP/RL2
TR2
MODE
0
0
1
16-bit Auto-reload
0
1
1
16-bit Capture
1
0
1
16-bit Compare
1
1
1
16-bit Capture and Compare
1
0
0
16-bit Compare with Auto-reload
0
0
0
off
15
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.4
P8xCL883; P8xCL884
For controlling this alternative port function the EMOUT0
bit has been added to the Alternative Port Function
Register (ALTP); see Section 6.2.3.
MSK modem
For the P8xCL883/P8xCL884, MIN is no longer the
alternative function of P4.0, but MIN is a separate pin.
The polarity of MIN can however still be programmed with
the P4.0 bit. P4.0 is a data SFR but no port logic is
connected.
6.5
Watchdog Timer
The Watchdog Timer differs from the description in the
“TELX family” data sheet in that the external EW pin does
not exist on the P8xCL883/P8xCL884.
Only the most significant bits of MOUT, i.e. MOUT2 and
MOUT1 are directly available as separate pins. In order to
be able to further increase the signal quality, the MOUT0
signal is available as an alternative port function of P3.1.
handbook, full pagewidth
internal reset
fosc
fosc
PRESCALER
13-BIT
8192
COUNTER REGISTER
8-BIT
overflow
enable
WDCON
REGISTER
WDTIM
8-BIT RELOAD REGISTER
internal bus
MBH997
Fig.6 Functional diagram of the Watchdog Timer (T3).
16
RST pin
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.6
P8xCL883; P8xCL884
6.6.2
OTP programming
6.6.1
In the In-System Programming mode the OTP can be
programmed under control of the CPU. A program to
control programming has to be available in the OTP. This
mode can be used to program several bytes in the OTP if
the chip is already in a system e.g. to store tuning
parameters.
OTP PROGRAMMING BY A PROGRAMMER
The 8 kbytes One Time Programmable (OTP) memory
can be programmed by using a programmer (OM4260)
together with a programmer adapter OM5508. Since the
memory is programmable only once, programming an
already programmed address results in a logical AND of
the old and new code. The OTP code can be read out by
the programmer for verification.
6.6.1.1
In the In-System Programming mode the complete
address space OTP can be programmed.
The user should take care not to overwrite the existing
code.
Signature bytes
The OTP memory contains three signature bytes which
can be read by the programmer to identify the device.
A special address space has been used for these bytes
which does not influence the user address space.
For In-System Programming four SFRs are used to control
the OTP.
Table 9
The values of the signature bytes are:
SFRs for In-System Programming
SFR NAME
(030H) = 15H, indicates manufactured by Philips
Semiconductors
(031H) = C5H, indicates P8xCL883/P8xCL884
(060H) = 00H, currently not used.
6.6.2.1
IN-SYSTEM PROGRAMMING MODE
DESCRIPTION
OAH
OTP Address High Register
OAL
OTP Address Low Register
ODATA
OTP Data Register
OISYS
OTP In-System Register
OTP In-System Programming Register (OISYS)
The OISYS SFR controls the In-System Programming mode. The data that has to be programmed is stored in the SFR
ODATA and the address for this data is held in the SFRs OAH and OAL.
Table 10 OTP In-System Programming Register (SFR address DCH)
7
6
5
4
3
2
1
0
−
−
−
VPon
SEC
SIG
WE
InSysMode
Table 11 Description of OISYS bits
BIT
SYMBOL
7 to 5
−
4
VPon
DESCRIPTION
These bits are reserved.
VPP status (read only).
3
−
2
SIG
Signature bytes enable.
1
WE
Write Enable, enables programming.
0
InSysMode
This bit is reserved.
In-System Programming status bit.
17
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.6.2.2
P8xCL883; P8xCL884
Mode entry
6.6.2.5
Signature bytes
The In-System Programming mode is entered by setting
the InSysMode bit of the OISYS SFR. The I2C-bus is used
for data transfer in this mode. If the I2C-bus interface is
addressed by an external master, the interface generates
an interrupt request. The interrupt handler can now read
the OISYS SFR and determine the status of the external
high voltage (VPon). If high voltage is not present the
interrupt is a standard I2C-bus interrupt.
The signature bytes can be read by setting the SIG bit of
the OISYS SFR and applying the address of the signature
byte. Applying a write pulse while the SIG bit of the OISYS
SFR is HIGH is forbidden although the contents of the
signature bytes will never be destroyed.
If high voltage is present the In-System Program interrupt
routine has to start that writes the InSysMode bit
(OISYS.0) and controls the address and data transfer.
If the VPP pin is dual-mode (e.g. PORENABLE/VPP), ICs
connected to the signal PORENABLE must be able to
withstand up to 13 V, i.e. cannot have clamping diodes or
low break-down voltages. If the pin is connected to a fixed
voltage (VDD or VSS) there must be a way of switching-off
this connection on the PCB. One possible implementation
is presented in Fig.7 where POR is enabled in normal
mode of operation (pin PORENABLE/VPP = 1 by the
pull-up), the VPP source must supply enough current in Rp
in order to guarantee a minimum 12.5 V on the
PORENABLE/VPP pin.
6.6.2.6
This paragraph is valid for version 2 (‘2’ ending on
type number). During In-System Programming the OTP
memory must be in the DC read mode. This is achieved by
writing 08H to the OTEST SFR. If the In-System
Programming mode is left, 00H must be written into the
OTEST SRF.
The program voltage must be available and stable for at
least 10 µs before the mode is entered and has to be
stable until the circuit has left the In-System Programming
mode. The high voltage can be applied for maximum
60 seconds during the complete lifetime of the circuit.
6.6.2.3
How to connect the PORENABLE/VPP pin in
the In-System Programming mode
Note that if in the application the Power-on reset is
disabled (pin PORENABLE/VPP = 0), applying a high
voltage to the PORENABLE/VPP pin will also enable the
POR circuit. This will cause a reset independent of the
actual VDD value.
Program cycle
The data and address must be supplied to the
microcontroller and the control program must write to the
SFRs: ODATA, OAH and OAL. A timer has to be initialized
for a 100 µs cycle and the WE bit of the OISYS SFR must
be set. Now the core has to be set into Idle mode. As long
as the circuit is in idle mode a programming pulse is
applied. After the interrupt request of the timer the OTP is
available for normal code fetching.
6.7
Oscillator circuitry
General information on the oscillator circuitry can be found
in the “TELX family” data sheet.
6.7.1
RESONATOR REQUIREMENTS
The address applied to the OAH and OAL SFRs must be
in the 8 kbytes address space.
For correct function of the oscillator, the values of R1 and
C0 of the chosen resonator (quartz or PXE) must be below
the line shown in Fig.8a. The value of the parallel resistor
R0 must be less than 47 kΩ.
6.6.2.4
The wiring between chip and resonator should be kept as
short as possible.
Verify for In-System Programming
Verify is done in similar way as programming. The circuit
is put into Idle mode and at the start of this mode the sense
amplifiers are switched to verify mode and a read cycle is
started. The timer must be initialized for a cycle of at least
1 µs. The address is supplied by the SFRs OAH and OAL.
The WE bit of the OISYS SFR has to be reset. The OTP
output data is latched in the ODATA SFR. After Idle mode
is finished this SFR can be read in a normal way.
To ensure that the verified data is written into the SFR it is
advised to write FFH into the ODATA SFR before a verify
is started.
6.7.2
RECOMMENDED RESONATOR TYPES
• CSA 3.58MG (supplier Murata)
• FCR3.58M5 (supplier TDK).
18
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
MDA088
500
handbook, halfpage
R1
(Ω)
400
VDD
handbook, halfpage
Rp
300
(1)
1
28
2
27
3
26
4
25
5
24
6
23
VPP pad on PCB
(2) (3)
200
100
0
7
8
9
20
10
19
11
18
12
17
13
16
14
15
20
0
P83CL883
P83CL884 22
P87CL883 21
P87CL884
40
60
Co (pF)
80
C1e and C2e are the external load capacitances; normally not needed
due to integrated load capacitances of typically 10 pF.
(1) C1e = C2e = 22 pF.
(2) C1e = C2e = 0 pF.
(3) C1e = C2e = 12 pF.
a. Resonator curves.
handbook, halfpage
MBK006
C1
L1
R1
R0
MGL137
C0
b. Resonator equivalent circuit.
Fig.7
PORENABLE/VPP connection on a PCB.
Fig.8 Resonator requirements for the ACO.
19
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
6.8
P8xCL883; P8xCL884
Emulation
The emulator for the P8xCL883/P8xCL884 uses the P87CL880 microcontroller in emulation mode. The P87CL880 is a
super-set of the P8xCL883/P8xCL884, i.e. it contains all the functions of the P8xCL883/P8xCL884 plus a number of
other additional functions. It should be noted that some functional differences between P87CL880 and
P8xCL883/P8xCL884 exist; see Table 12.
Table 12 Differences between functions existing in P87CL880 and P8xCL883/P8xCL884
FUNCTION
P87CL880
P8XCL883/P8XCL884
Timer 2
see P87CL880 specification
see P8xCL883/P8xCL884 specification
OTP Program Memory
32 kbytes AFPROM
8 kbytes EPROM or pre-programmed ROM
RAM
512 bytes
256 bytes
EW pin (Watchdog enable)
yes
no
Security concept
see P87CL880 specification
see P8xCL883/P8xCL884 specification
In-System Programming
no
yes
Reset value of SFRs
see P87CL880 specification
see P8xCL883/P8xCL884 specification
POR
hardware programmable
fixed
Frequency
DC to 12.5 MHz
3.58 MHz
Package
QFP64
SO28
6.9
6.9.1
A software workaround for this problem exists. During the
initialisation sequence:
Non-conformance
PROGRAMMING INTERFACE/TRANSPARENT MODE
• Enable LVD by writing to register LVDCON
The Transparent mode is a special operating mode of the
microcontroller used for parallel and In-System OTP
programming.
• Enable LVD interrupt by writing to register IEN2
• Clear the LVDI bit by writing to LVDCON a second time
• Set bit EA in register IEN0 (ensures LVDI to be cleared
after initialisation).
For certain combinations of data written to Port 1 (used for
control signal during parallel programming mode) the
Transparent mode may be incorrectly active during normal
operation of the microcontroller. In this case, a transition
on any of Port 0 pins can influence the read out of the
on-chip program memory, resulting in incorrect code
execution.
6.9.3
In receive mode 1, 2 and 3 it is possible that an internal
setup/hold condition of a flip-flop is violated. This results in
a not detected start bit (start condition) during receive
mode. The probability of occurrence (verified on sampling
basis) is below 3%.
To avoid this problem, the InSysMode bit in the OTP
In-System Programming Register (SFR address DCH)
must be set in the start-up sequence of the program code.
There is no workaround for this problem other than to use
the UART only in Mode 0 for reception.
Apart from preventing incorrect operation as described
above, the setting of this bit does not affect the normal
operation.
6.9.2
EDGE DETECTION ON UART
LOW VOLTAGE DETECTION
The LVDI bit (LVDCON.6) may incorrectly be set due to a
glitch on the LVD output, when the LVD is enabled, by
changing the bits LVDCON(3:0) from ‘0000’ to any value
within the range ‘0001’ to ‘0101’. If bit EA in register IEN0
is enabled, an unwanted interrupt may occur.
20
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+4.0
VI
input voltage on any pin with respect to ground (VSS)
−0.5
VDD + 0.5 V
Ptot
total power dissipation
−
800
mW
Tstg
storage temperature
−65
+150
°C
V
8 CHARACTERISTICS
VDD = 2.7 to 3.6 V; VSS = 0 V; fxtal = 3.58 MHz; Tamb = −25 to +70 °C;
Tamb (during In-System Programming) = +20 to +40 °C; all voltages with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
operating
2.7
−
3.6
V
RAM data retention in Power-down mode
1.0
−
3.6
V
In-System Programming
3.0
−
3.6
V
VPP
OTP programming voltage
IDD
operating supply current
IDD(id)
IDD(pd)
IDD(block)
12.5
−
13.0
V
VDD = 3 V; note 1
−
−
3.0
mA
VDD = 3 V; Tamb = 25 °C;
note 1; see Fig.10
−
1.8
−
mA
VDD = 3 V; note 2
−
−
0.55
mA
VDD = 3 V; Tamb = 25 °C;
note 2; see Fig.11
−
0.38
−
mA
POR and LVD enabled −
2
5
µA
POR and LVD disabled −
100
−
nA
−
460
−
µA
−
240
−
µA
MSK modem
−
140
−
µA
supply current Idle mode
supply current Power-down mode
supply current per block:
VDD = 3 V; Tamb = 25 °C;
note 3; see Fig.12
VDD = 3 V; Tamb = 25 °C;
notes 4 and 5
EEPROM erase/write
DTMF
no load on TONE output
Watchdog
−
110
−
µA
I2C-bus
−
90
−
µA
UART
−
90
−
µA
Timer T2
−
90
−
µA
Timer T0 or T1
−
5
−
µA
21
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
SYMBOL
P8xCL883; P8xCL884
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs (Ports, MIN, RST, MOUT0 to MOUT2, PORENABLE)
−
VIL
LOW-level input voltage
notes 6 and 7
0
VIH
HIGH-level input voltage
note 6
0.8VDD −
VDD
0.2VDD V
V
IIL
LOW-level input current (ports in Mode 1)
VIN = 0.4 V; note 8;
see Fig.9
−
10
50
µA
IIL(T)
LOW-level input current; HIGH-to-LOW
transition (ports in Mode 1)
VIN = 0.5VDD; note 8;
see Fig.9
−
200
1000
µA
ILI
input leakage current (ports in Mode 0 or 2) VSS ≤ VI ≤ VDD
−
−
1
µA
Port outputs (Ports, RST, MOUT0 to MOUT2)
IOL
LOW-level output current; except P1.3,
SDA, SCL and MOUT2
VOL = 0.4 V
2
−
−
mA
IOL1
LOW-level output current; P1.3 (for LED)
VOL = 0.4 V
6
−
−
mA
IOL2
LOW-level output current; SDA, SCL and
MOUT2
VOL = 0.4 V; note 9
3
−
−
mA
IOH
HIGH-level output current except P1.3;
push-pull options only
VOH = VDD − 0.4 V
2
−
−
mA
IOH1
HIGH-level output current P1.3
(for LED); push-pull options only
VOH = VDD − 0.4 V
6
−
−
mA
IOH2
HIGH-level output current MOUT2
VOH = VDD − 0.4 V
3
−
−
mA
IRST
RST pull-up transistor current
VDD = 3 V;
VOH = VDD − 0.4 V
0.05
0.2
−
µA
VDD = 3 V; VOH = VSS
−
0.6
2.5
µA
Power-on reset (POR); for the LVD (Low Voltage Detection) see note 10
VPORH
Power-on reset trip level HIGH
option 5 in “TELX family”
specification
2.13
2.37
2.61
V
VPORL
Power-on reset trip level LOW
option A in “TELX
family” specification
1.98
2.27
2.56
V
VDD = 3 V
158
181
205
mV
TONE output (note 11 and Fig.13)
VHG(rms)
HGF voltage (RMS)
VLG(rms)
LGF voltage (RMS)
125
142
160
mV
∆f/f
frequency deviation
−0.6
−
+0.6
%
VDC
DC voltage level
−
0.5VDD −
V
VG
pre-emphasis of group
1.5
2.0
2.5
dB
THD
total harmonic distortion
−
25
−
dB
erase/write time
8
10
12
ms
NE/W
erase/write cycles
105
−
−
tDR
data retention time
10
−
−
VDD = 3 V; Tamb = 25 °C;
notes 5 and 12
EEPROM (notes 5 and 13)
tE/W
Tamb = +70 °C
22
years
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
SYMBOL
P8xCL883; P8xCL884
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
In-System Programming for the OTP
tprog
program cycle time
90
100
110
µs
tver
verify cycle time
1
−
−
µs
tVpp(setup)
program voltage setup time
10
−
−
µs
tVpp(max)
maximum program voltage time
cumulative for the
product lifetime
−
−
60
s
IVpp
program voltage current
In-System Programming
−
−
40
mA
ACO (Amplitude Controlled Oscillator)
VXTAL1
external clock signal amplitude
peak-to-peak
500
−
VDD
mV
Zi(XTAL1)
input impedance on XTAL1
300
1000
−
kΩ
C1i; C2i
input capacitance on XTAL1 and XTAL2
−
10
−
pF
notes 5 and 15
Notes
1. The operating supply current is measured with all output pins disconnected; VIL = VSS; VIH = VDD; RST = VDD;
XTAL1 driven with square wave; XTAL2 not connected; fetch of NOP instructions; all derivative blocks disabled.
2. The Idle mode supply current is measured with all output pins and RST disconnected; VIL = VSS; VIH = VDD;
XTAL1 driven with square wave; XTAL2 not connected; all derivative blocks disabled.
3. The Power-down current is measured with all output pins and RST disconnected; VIL = VSS; VIH = VDD;
XTAL1 and XTAL2 not connected;.
4. The typical currents are only for the specific block. To calculate the typical power consumption of the microcontroller,
the current consumption of the CPU must be added. Example: the typical current consumption of the microcontroller
in operating mode with CPU, Watchdog and UART active can be calculated as (1.8 + 0.11 + 0.09) mA = 2.0 mA.
5. Verified on sampling basis.
6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage
below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.
7. For pin PORENABLE the VIL(max) = 0.1VDD.
8. Not valid for pins SDA, SCL, RST, MIN and PORENABLE.
9. The maximum allowed load capacitance CL is in this case limited to around 200 pF.
10. The LVD is tested according to the specification in the data sheet “TELX family; Chapter: Low Voltage Detection”.
11. Values are specified for DTMF frequencies only (CEPT CS203).
12. Related to the Low Group Frequency (LGF) component (CEPT CS203).
13. After final testing the value of each EEPROM bit is typically logic 1.
14. Can also be done by two 100 µs pulses.
15. C1i and C2i are the total internal capacitances (including gate capacitance, leadframe capacitance).
23
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
handbook, full pagewidth
P8xCL883; P8xCL884
MGL506
500 µA
I IL(T)
II
IIL
10 µA
0
0.3VDD
0.5VDD
VDD
Fig.9 Input current.
MGL627
MGL628
0.6
2.5
handbook, halfpage
handbook, halfpage
IDD
(mA)
IDD(id)
(mA)
2.2
0.5
1.9
0.4
1.6
0.3
1.3
2.2
2.6
3
3.4
0.2
2.2
3.8
4.2
VDD (V)
Fig.10 Typical operating current as a function of
VDD, Tamb = 25 °C.
2.6
3
3.4
3.8
4.2
VDD (V)
Fig.11 Typical Idle current as a function of VDD,
Tamb = 25 °C.
24
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
MDA085
4
handbook, halfpage
IDD(pd)
(µA)
(1)
3
handbook, halfpage VDD
(2)
2
DEVICE TYPE NUMBER
(1)
1
TONE
1 µF
(3)
10 kΩ
50 pF
(4)
VSS
0
0
(1)
(2)
(3)
(4)
1
2
3
VDD (V)
MGB835
4
POR and LVD enabled (Tamb = 70 °C).
POR and LVD enabled (Tamb = 25 °C).
POR and LVD disabled (Tamb = 70 °C).
POR and LVD disabled (Tamb = 25 °C).
(1) P8xCL883/P8xCL884.
Fig.12 Typical Power-down current as a function of
VDD.
Fig.13 TONE output test circuit.
25
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
9
P8xCL883; P8xCL884
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
26
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
10 SOLDERING
10.1
Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
10.2
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
10.3
10.4
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
27
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
10.5
P8xCL883; P8xCL884
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
28
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
11 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
12 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
13 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
29
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
NOTES
30
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
NOTES
31
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
465008/00/02/pp32
Date of release: 1999 Mar 15
Document order number:
9397 750 05027