PDM31096 PRELIMINARY 4 Megabit 3.3V Static RAM 512K x 8-Bit Features n n n n n High-speed access times Com’l: 8, 10, 12, 15, and 20 ns Ind’l.: 12, 15 and 20 ns Low power operation - PDM31096SA Active: 300 mA (Max) Standby: 25mW Description 1 The PDM31096 is a high-performance CMOS static RAM organized as 524,288 x 8 bits. Writing is accomplished when the write enable (WE) and chip enable CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE are both LOW. 2 The PDM31096 operates from a single +3.3V power supply and all the inputs and outputs are fully TTLcompatible. Single +3.3V (±0.3V) power supply TTL-compatible inputs and outputs Packages Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T The PDM31096 is available in a 36-pin 400-mil plastic SOJ package and a 44-pin plastic TSOP (II) package. 3 4 5 6 7 Functional Block Diagram Addresses I/O 0 • A0 • • • • • A18 Decoder • • • • • • 8 Memory Matrix 9 • • • • • Input Data Control Column I/O 10 • I/O 7 • 11 • CE • 12 WE OE Rev. 2.4 - 5/27/98 1 PDM31096 PRELIMINARY Pin Configuration TSOP (II) NC SOJ Pin Description 1 44 NC 2 43 NC A4 3 42 NC A3 4 41 A5 A2 5 40 A6 A1 6 39 A7 NC A4 1 36 NC A3 2 35 A5 A2 3 34 A6 A1 4 33 A0 5 32 CE 6 31 OE Name Description A7 A18-A0 Address Inputs A8 I/O7-I/O0 Data Inputs/Outputs A0 7 38 A8 I/O0 7 30 I/O7 OE Output Enable Input CE 8 37 OE I/O1 8 29 I/O6 I/OO WE Write Enable Input 9 36 I/O7 Vcc 9 28 Vss I/O1 10 35 I/O6 Vss 10 27 Vcc CE Chip Enable Inputs Vcc 11 34 Vss I/O2 11 26 I/O5 NC No Connect Vss 12 33 Vcc I/O3 12 25 I/O4 Power (+3.3V) Ground 32 I/O5 WE 31 I/O4 A18 13 14 24 23 A9 I/O3 13 14 VCC A10 WE 30 A9 A17 15 22 A11 VSS 15 A18 16 29 A10 A16 16 21 A12 A17 17 18 28 A11 A15 17 A13 27 A12 A14 18 20 19 A15 19 26 A13 A14 25 NC NC 20 21 24 NC NC 22 23 NC I/O2 A16 NC Truth Table(1) OE WE CE I/O MODE X X H Hi-Z Standby X X X Hi-Z Standby L H L DOUT Read X L L DIN Write H H L Hi-Z Output Disable NOTE: 1. H = VIH, L = VIL, X = DON’T CARE Absolute Maximum Ratings (1) Symbol Rating Com’l. Ind. Unit VTERM Terminal Voltage with Respect to VSS –0.5 to +4.6 –0.5 to +4.6 V TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA Tj Maximum Junction Temperature (2) 125 145 °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P is average operating power and θja the thermal resistance of the package. For this product, use the following θja value: SOJ: 59o C/W TSOP : TBD 2 Rev. 2.4 - 5/27/98 PDM31096 PRELIMINARY DC Electrical Characteristics (VCC = 3.3V ± 0.3V) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = VSS to VCC –5 5 µA ILO Output Leakage Current VCC = Max., CE = VIH VOUT = VSS to VCC –5 5 µA VIL Input Low Voltage –0.3(1) 0.8 V VIH Input High Voltage 2.2 Vcc+0.3 V VOL Output Low Voltage IOL = 8 mA, VCC = Min. — 0.4 V VOH Output High Voltage IOH = –4 mA, VCC = Min. 2.4 — V 1 2 3 NOTE:1.VIL(min) = –3.0V for pulse width less than 20 ns 4 Power Supply Characteristics Symbol Parameter ICC Operating Current CE = VIL -8 -10 Com’l. 230 Com’l. 215 -12 -15 5 -20 Com’l Ind. Com’l Ind. Com’l Ind. 200 220 160 200 120 160 Unit mA 6 f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH 50 45 40 45 35 40 30 35 mA 10 10 10 15 10 15 10 15 mA 7 f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE ≥ VCC – 0.2V 8 f=0 VCC = Max., VIN ≥ VCC – 0.2V or ≤ 0.2V 9 NOTES: All values are maximum guaranteed values. 10 Capacitance(1) (TA = +25°C, f = 1.0 MHz) Symbol Parameter Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance 8 pF 11 NOTE: 1. This parameter is determined by device characterization but is not production tested. 12 Rev. 2.4 - 5/27/98 3 PDM31096 PRELIMINARY Recommended DC Operating Conditions Symbol VCC Parameter Supply Voltage Min. Typ. Max. Unit 3.0 3.3 3.6 V VSS Supply Voltage 0 0 0 V Industrial Ambient Temperature –40 25 85 °C Commercial Ambient Temperature –0 25 70 °C AC Test Conditions Input pulse levels VSS to 3.0V Input rise and fall times 2.5 ns Input timing reference levels 1.5V Output reference levels 1.5V Output load See Figures 1 and 2 +3.3V +3.3V 317Ω DOUT DOUT 351Ω 30 pF Figure 1. Output Load Equivalent 4 317Ω 351Ω 5 pF Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Rev. 2.4 - 5/27/98 PDM31096 PRELIMINARY Read Cycle No. 1(4, 5) 1 tRC ADDR tAA 2 tOH DOUT DATA VALID PREVIOUS DATA VALID 3 Read Cycle No. 2(2, 4, 6) tRC 4 ADDR tAA tACE CE 5 tHZCE tLZCE 6 OE tLZOE tHZOE DOUT DATA VALID 7 tAOE 8 AC Electrical Characteristics Description -8* READ Cycle -10* –12 –15 9 –20 Sym Min Max Min Max Min Max Min Max Min Max Units READ cycle time tRC 8 — 10 — 12 — 15 — 20 — ns Address access time tAA — 8 — 10 — 12 — 15 — 20 ns Chip enable access time tACE — 8 — 10 — 12 — 15 — 20 ns tOH 3 — 3 — 3 — 3 — 3 — ns Output hold from address change (1,3) tLZCE 3 — 3 — 3 — 3 — 3 — ns (1,2,3) tHZCE — 4 — 5 — 6 — 7 — 7 ns Output enable access time tAOE — 4 — 5 — 6 — 7 — 8 ns Output Enable to output in low Z (1,3) tLZOE 0 — 0 — 0 — 0 — 0 — ns (1,3) tHZOE — 4 — 4 — 5 — 6 — 7 ns Chip enable to output in low Z Chip disable to output in high Z Output disable to output in high Z 10 11 12 * Vcc = 3.3V +5% Rev. 2.4 - 5/27/98 5 PDM31096 PRELIMINARY Write Cycle No. 1 (Write Enable Controlled) tWC ADDR tAW tAH tCW CE tAS tWP WE tDS DIN tDH DATA VALID tHZWE tLZWE HIGH-Z DOUT Write Cycle No. 2 (Write Enable Controlled) tWC ADDR tAW tAH tCW CE tAS tWP WE tDS DIN DOUT tDH DATA VALID HIGH-Z NOTE: Output Enable (OE) is inactive (high) 6 Rev. 2.4 - 5/27/98 PDM31096 PRELIMINARY Write Cycle No. 3 (Chip Enable Controlled) 1 tWC ADDR tAW tAH tAS tCW 2 CE 3 tWP WE tDS DIN tDH 4 DATA VALID HIGH-Z DOUT 5 NOTE: Output Enable (OE) is inactive (high) 6 AC Electrical Characteristics -8* Description WRITE Cycle Sym -10* -12 -15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units WRITE cycle time tWC 8 — 10 — 12 — 15 — 20 — ns Chip enable to end of write tCW 8 — 10 — 10 — 11 — 13 — ns Address valid to end of write tAW 8 — 10 — 10 — 11 — 13 — ns Address setup time tAS 0 — 0 — 0 — 0 — 0 — ns Address hold from end of write tAH 0 — 0 — 0 — 0 — 0 — ns Write pulse width tWP 7 — 8 — 8 — 9 — 10 — ns Data setup time tDS 5 — 6 — 7 — 8 — 9 — ns Data hold time tDH 0 — 0 — 0 — 0 — 0 — ns (1,3) tLZWE 0 — 0 — 0 — 0 — 0 — ns (1,3) tHZWE — 4 5 — 6 — 7 — 9 ns Write disable to output in low Z Write enable to output in high Z 7 -20 8 9 10 * VCC = 3.3V +5% NOTES: (For two previous Electrical Characteristics tables) 1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE. 3. This parameter is sampled. 4. WE is high for a READ cycle. 5. The device is continuously selected. All the Chip Enables are held in their active state. 6. The address is valid prior to or coincident with the latest occuring Chip Enable. Rev. 2.4 - 5/27/98 7 11 12 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com