ETC PI74ALVTC16841

PI74ALVTC16841
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2.5V 20-Bit Bus Interface
D-Type Latch with 3-State Outputs
Product Features
Product Description
• PI74ALVTC16841 is designed for low voltage operation,
VDD = 1.65V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, –32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A56)
– 56-pin 173-mil wide plastic TVSOP (K56)
Pericom Semiconductor’s PI74ALVTC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16841 features 3-State outputs designed specifically
for driving highly capacitive or relatively low-impedence loads. This
device is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The device can be used as two 10-bit latches, or one 20-bit latch. The
20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While
the latch-enable (1LE or 2LE) input is high, the Q outputs of the
corresponding 10-bit latch follows the D inputs. When LE is taken
low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place
the outputs of the corresponding 10-bit latch in either a normal logic
state (high or low logic levels) or a high-impedence state. In the highimpedence state, the outputs neither load nor drive the bus lines
significantly.
Logic Block Diagram
1OE
The output enable (OE) input does not affect the internal operation
of the latches. Old data can be retained or new data or new data can
be entered while the outputs are in the high-impedence state.
1
1LE 56
L
1D0
55
Q
2
To ensure the high-impedance state during power up or power down,
OE should be tied to VDD through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
1Q0
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data
input’s last state preventing “floating” inputs and eliminating the
need for pullup/down resistors.
D
To Nine Other Channels
2OE
28
2LE 29
L
2D0 42
Q
15
2Q0
D
To Nine Other Channels
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04/09/02
PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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Truth Table
Product Pin Description
Pin Name
nOE
Description
Output Enable Inputs (Active LOW)
nLE
nDx
nQx
GND
VDD
Latch Enable Inputs (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Inputs
Product Pin Configuration
1OE
1Q0
1
2
56
55
1LE
1D0
1Q1
GND
1Q2
3
4
5
54
53
52
1D1
GND
1D2
1Q3
VDD
51
50
49
1D3
VDD
1Q4
6
7
8
1D4
1Q5
1Q6
9
10
48
47
1D5
1D6
GND
1Q7
1Q8
11
12
13
46
45
44
GND
1D7
1D8
1Q9
2Q0
2Q1
14
15
16
43
42
41
1D9
2D0
2D1
2Q2
GND
17
18
40
39
2D2
GND
2Q3
2Q4
2Q5
19
20
21
38
37
36
2D3
2D4
2D5
VDD
35
34
33
VDD
2Q6
2Q7
22
23
24
GND
2Q8
25
26
32
31
GND
2D8
2Q9
2OE
27
28
30
29
2D9
2LE
56-Pin
A, K
Outputs
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Notes:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High-Impedance "OFF" state
2D6
2D7
2
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04/09/02
PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD ........................................................ –0.5V to 4.6V
Input Voltage Range, VI ................................................................. -0.5V to 4.6V
Output Voltage Range, VO (3-Stated) ............................... -0.5V to 4.6V
Output Voltage Range, VO(1) (Active) .................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI < 0V ......................................... -50mA
DC Output Diode Current (IOK)
VO < 0V .................................................................................... -50mA
VO > VDD .................................................................................................... ±50mA
DC Output Source/Sink Current (IOH/IOL) .......................... -64/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ............ ±100mA
Storage Temperature Range, Tstg .................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions(2)
M in.
M ax.
O perating
1.65
3.6
Data Retention O nly
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
O utput voltage
O utput current in IOH/IOL
Dt/Dv
TA
0.8
–0.3
3.6
Active State
0
VDD
O ff State
0
3.6
VDD =
VDD =
VDD =
VDD =
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
Input transistion rise or fall rate(3)
O perating free- air temperature
Units
V
–32/64
±24
±18
±6
mA
0
10
ns/V
-40
85
C
Notes:
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
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PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIK
VOH
Input Clamp Diode
HIGH Level Output Voltage
Conditions
VDD
IIK = -18mA
3.0
2.7 - 3.6
VDD – 0.2
IOH = -12mA
2.7
2.2
IOH = -18mA
M ax.
3.0
2.2
2.0
IOL = 100mA
2.7 - 3.6
0.2
IOL = 12mA
2.7
0.4
IOL = 18mA
IOL = 24mA
0.45
3.0
0.5
IOL = 64mA
0.55
II
Input Leakage Current
VI = VDD, or GND
3.6
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.7
±10
IOFF
Power- OFF Leakage Current
VI or VO £ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.8V
3.0
VI = 2.0V
VI = 0 to 3.6V
IDD
DIDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 32mA
IHOLD
Units
2.4
IOH = -32mA
LOW Level Output Voltage
Typ.
–1.2
IOH = -100mA
IOH = -24mA
VOL
M in.
3.6
VI = VDD or GND
75
–75
±500
mA
50
VDD £ (VI,VO) £ 3.6V
VIH = VDD –0.6V,
Other inputs at VDD or Gnd
4
2.7 - 3.6
±50
400
P0.2
04/09/02
PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
(continued from previous page)
DC Characteristics (2.3V ≤VDD ≤ 2.7V)
De s cription
VIK
Parame te rs
Input Clamp Diode
Conditions
IIK = –18mA
HIGH Level Output Voltage
2.3 - 2.7
IOH = –12mA
2.3
IOH = –18mA
IOL = 100mA
VOL
LOW Level Output Voltage
M in.
Typ.
2.3
IOH = –100mA
VOH
VDD
M ax.
–1.2
VDD– 0.2
1.8
1.7
2.3 - 2.7
0.2
IOL = 12mA
IOL = 18mA
0.5
2.3
0.55
II
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- State Output Leakage
VO
2.3
±10
IOFF
Power- OFF Leakage Current
VI or VO £
0
10
Bus Hold Current
A or B Outputs
VI = 0.7V
IDD
DIDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 24mA
IHOLD(1)
Units
V
= 3.6
V
3.6
2.5
VI = 1.7V
VI = VDD or GND
VDD £ (VI,VO) £ 3.6V
VIH = VDD –0.6V,
Inputs at VDD or Gnd
90
–90
40
2.3 - 2.7
A
m
A
m
±40
400
Note:
1. Not Guaranteed
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04/09/02
PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
(continued from previous page)
DC Characteristics (1.65V ≤ VDD ≤ 1.95V)
De s cription
Parame te rs
VIK
Input Clamp Diode
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
VDD
IIK = –18mA
M in.
Typ.
1.65
IOH = –100mA
M ax.
–1.2
1.65- 1.95 VDD –0.2
IOH = –6mA
1.4
V
1.65
IOL = 100mA
0.2
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
1.95
±5.0
IOZ
3- State Output Leakage
VO =
1.65
±10
IOFF
Power- OFF Leakage Current
VI = VO £
0
10
Bus Hold Current
A or B Outputs
VI = 0.4
IHOLD(1)
IDD
DIDD
Quiescent Supply Current
Increase in IDD per input
Units
V
3.6
V
3.6
1.65
VI = 1.3
VI = VDD or GND
50
A
–50
m
20
VDD £ (VI,VO) £ 3.6V
VI = VDD –06V,
Other inputs at VDD or Gnd
1.65- 1.95
±20
400
Note:
1. Not Guaranteed
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PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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AC Electrical Characteristics
W
TA = –40°C to +85°C, CL = 50pF, RL = 500
Symbol
VDD = 1.8V
±0.15V
Parame te r
VDD = 2.5V
±0.2V
VDD = 3.3V
±0.3V
M in.
M ax.
M in.
M ax.
M in.
M ax.
tPLH, tPHL
Prop Delay, D to Q
1.5
4.0
1.0
3.2
0.5
2.7
tPLH, tPHL
Prop Delay, LE to Q
2.0
5.0
1.5
4.2
1
3.1
tPZH, tPZL
Output Enable Time
2.0
5.0
1.5
4.7
1.0
3.1
tPHZ, tPLZ
Output Disable Time
2.0
5.0
1.5
4.0
1.5
3.7
tOSHL
tOSLH
Output to Output Skew(1)
0.5
0.5
Units
ns
0.5
Note
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same
direction, either HIGH or LOW (tOSHL) or LOW to HIGH (tOSLH).
AC Setup Requirements
W
TA = –40ºC to +85ºC, CL = 50pF, RL = 500
Symbol
Parame te r
VDD = 1.8V
±0.15V
VDD = 2.5V
±0.2V
VDD = 3.3V
±0.3V
Min.
Min.
Min.
Typ.
Typ.
tSU
Setup Time, D to LE
1.0
0.5
0.5
tH
Hold Time, D to LE
1.0
0.5
0.8
tW
LE Pulse Width, High
1.5
1.5
1.5
Units
Typ.
ns
Capacitance
Symbol
Parame te r
TA = +25°C
Typical
Conditions
CIN
Input Capacitance
VDD = 1.8, 2.5V or 3.3V,
VI = 0V or VDD
6
COUT
Output Capacitance
VI = 0V or VDD,
VDD = 1.8V, 2.5V or 3.3V
7
CPD
Power Dissipation
Capacitance
VI = 0V or VDD, F = 10 MHz
VDD = 1.8V, 2.5V or 3.3V
20
7
Units
pF
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04/09/02
PI74ALVTC16841
2.5V 20-Bit Bus Interface
D-Type Latch w/3-State Outputs
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Switch Position
Test Circuits and Switching Waveforms
Parameter Measurement Information (VDD = 1.65V - 3.6V)
3.3V/2.5V VDD
2 x VDD
R1
500Ω
From Output
Under Test
Open
30pF
CL
RL
500Ω
Te s t
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
GND
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
VDD
1.8V VDD
High-Low-High
Pulse
2 x VDD
VDD/2
0V
R1
1kΩ
From Output
Under Test
Open
30pF
CL
RL
1kΩ
GND
Propagation Delay
(See Note A)
VDD
VDD/2
Input
tPHL
tPLH
0V
VDD
Setup, Hold, and Release Timing
Output
VDD/2
VOL
tPHL
Data
Input
tSU
Timing
Input
tH
tPLH
VDD
VDD
VDD/2
0V
Opposite Phase
Input Transition
VDD
VDD/2
0V
VDD/2
0V
Enable Disable Timing
VDD
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one transition per
measurement.
Output
Control
(Active LOW)
VDD/2
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
0V
VDD
VDD/2
+0.15V
tPZH
VOL
tPHZ
–0.15V
VOH
VDD/2
0V
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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