ETC PI74AVC+16652A

PI74AVC+16652
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2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Description
Product Features
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16652 is a 16-bit bus transceiver and register
designed for low 1.65V to 3.6V VCC operation. It consists of D-type
flip-flops and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal storage
registers. The device can be used as two 8-bit transceivers or one
16-bit transceiver.
Complementary Output Enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select Control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A low input level selects real-time data, and a high
input level selects stored data. Circuitry used for Select Control
eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock (CLKAB
or CLKBA) inputs regardless of the levels on the Select Control or
Output Enable inputs. When SAB and SBA are in the real-time
transfer mode, it also is possible to store data without using the
internal D-type flip-lops by simultaneously enabling OEAB and
OEBA. In this configuration, each output reinforces its input. Thus,
when all other data sources to the two sets of bus lines are in the
high-impedance state, each set of bus lines remains at its last level
configuration.
To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and
OEAB should be tied to GND through a pull-down resistor; the
minimum value of the resistor is determined by the current-sinking
current sourcing capability of the driver.
• PI74AVC+16652 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
• True ±24mA Balanced Drive @ 3.3V
• IOFF supports partial power-down operation
• 3.6V I/O Tolerant Inputs and Outputs
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
• Industrial operation: –40°C to +85°C
• Available Packages:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
1OEBA
1OEAB
1CLKBA
56
1
55
1SBA
54
1CLKAB
2
1SAB
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
TO SEVEN OTHER CHANNELS
2OEBA
2OEAB
2CLKBA
29
28
30
2SBA
31
2CLKAB
27
2SAB
26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
TO SEVEN OTHER CHANNELS
1
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Pin Configuration
Product Pin Description
Pin Name
D e s cription
1OEAB
O EAB
O utput Enable Inputs (Active HIGH)
O EBA
O utput Enable Inputs (Active LO W)
xCLK AB,
xCLK BA
Clock Pulse Inputs
xSAB, xSBA
Select Control Inputs
xAx
Data Register A Inputs,
Data Register B O utputs
xBx
Data Register B Inputs,
Data Register A O utputs
GND
Ground
VCC
Power
1CLKAB
1SAB
GND
1A 1
1A 2
VCC
1A 3
1A 4
1A 5
GND
1A 6
1A 7
1A 8
2A 1
2A 2
2A 3
GND
2A 4
2A 5
2A 6
VCC
2A 7
2A 8
GND
2SAB
2CLKAB
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin
A, K
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1CLKBA
1SBA
GND
1B 1
1B 2
VCC
1B 3
1B 4
1B 5
GND
1B 6
1B 7
1B 8
2B 1
2B 2
2B 3
GND
2B 4
2B 5
2B 6
VCC
2B 7
2B 8
GND
2SBA
2CLKBA
2OEBA
Truth Table(1)
Inputs
Data I/O*
Ope ration or Function
OEAB
OEBA
CLKAB
CLKBA
SAB
SB A
A1 - A8
B1 - B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
­
­
X
X
Input
Input
Store A and B data
X
H
­
H or L
X
X
Input
Unspecified* *
H
H
­
­
X* *
X
Input
Output
L
X
H or L
­
X
X
Unspecified* *
Input
Hold A, store B
L
L
­
­
X
X* *
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real- time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real- time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
Store A, hold B
Store A in both registers
Notes:
1. H = High Voltage Level, X = Don’t Care, L = Low Voltage Level, ↑ = LOW-to-HIGH Transition
* The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input
functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
** Select control = L; clocks can occur simultaneously. Select control = H; to load both registers, clocks must be staggered.
2
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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REAL-TIME TRANSFER
BUS A to B
REAL-TIME TRANSFER
BUS B to A
BUS
BUS
BUS
BUS
A
B
A
B
OEAB OEBA
L
L
xCLKAB
X
xCLKBA
X
xSAB
X
xSBA
L
OEAB OEBA xCLKAB
H
H
X
xCLKBA
X
xSAB
L
TRANSFER STORED
DATA to A and/or B
STORAGE FROM
A,B, or A and B
BUS
BUS
BUS
BUS
A
B
A
B
OEAB OEBA xCLKAB
↑
X
H
L
X
X
↑
L
H
xCLKBA
X
↑
↑
xSBA
X
xSAB
X
X
X
OEAB OEBA xCLKAB
H
L
H or L
xSBA
X
X
X
xCLKBA
H or L
xSAB
H
xSBA
H
Note:
1. Cannot transfer data to A bus and B bus simultaneously.
3
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Supply voltage range, VCC .................................................. –0.5V to +4.6V
Input voltage range, VI .......................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, V O(1) .............. –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) .......................................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ............................................ –50mA
Output clamp current, IOK (VO <0) ...................................... –50mA
Notes:
1. Input & output negative-voltage ratings may be exceeded if the
input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V
maximum if theoutput current rating is observed.
3. package thermal impedance is calculated in accordance with
JESD 51.
Continuous output current, IO ............................................................ ±50mA
Continuous current through each VCC or GND ................. ±100mA
Package thermal impedance, qJA(3): package A .................. 64°C/W
package K ................... 48°C/W
Storage Temperature range, Tstg ..................................... –65°C to 150°C
Recommended Operating Conditions(1)
VCC
VIH
Supply Voltage
High- level Input Voltage
M in.
M ax.
Units
Operating
1.65
3.6
V
Data retention only
1.2
VCC = 1.2V
VCC
VCC = 1.65V to 1.95V
0.65 x VCC
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
VIL
Low- level Input Voltage
1.7
2
VCC = 1.2V
Gnd
VCC = 1.65V to 1.95V
VI
Input Voltage
VO
Output Voltage
IOH High- level output current
IOL
Low- level output current
∆t∆v Input transition rise or fall rate
TA
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.65V to 1.95V
–6
VCC = 2.3V to 2.7V
– 12
VCC = 3V to 3.6V
– 24
mA
VCC = 1.65V to 1.95V
6
VCC = 2.3V to 2.7V
12
VCC = 3V to 3.6V
24
VCC = 1.65V to 3.6V
5
ns/V
85
°C
Operating free- air temperature
–40
Note:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
4
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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DC Electrical Characteristics (Over Operating Range, TA = –40°C +85°C)
Te s t Conditions (1)
Parame te rs
IOH = –100µA
VOH
VCC
M in.
1.65V to 3.6V
VCC –0.2V
IOH = –6mA
VIH = 1.07V
1.65V
1.2
IOH = –12mA
VIH = 1.7V
2.3V
1.75
IOH = –24mA
VIH = 2V
3V
2.0
M ax.
Units
V
IOL = 100µA
VOL
II
0.2
IOL = 6mA
VIH = 0.57V
1.65V
0.45
IOL = 12mA
VIH = 0.7V
2.3V
0.55
IOL = 24mA
VIH = 0.8V
3V
0.8
Control Inputs
VI = VCC or GND
3.6V
±2.5
IOFF
VI or VO = 3.6V
0
±10
IOZ
VI = VCC or GND
3.6V
±10
ICC
VO = VCC or GND
3.6V
40
2.5V
4
3.3V
4
2.5V
6
3.3V
6
2.5V
8
3.3V
8
IO = 0
Control Inputs
CI
VI = VCC or GND
Data Inputs
CO
1.65V to 3.6V
Outputs
VO = VCC or GND
µA
pF
Note:
1. Typical values are measured at TA = 25°C.
5
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
VCC = 1.2V
VCC = 1.5V
±0.1V
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
M in
M in
M in
M in
M in
M ax
M ax
M ax
fclock Clock Frequency
M ax
150
tw Pulse duration,
CLK AB or
CLK BA high or low
Units
M ax
250
350
3.3
1.0
1.4
tsu Setup time,
A before CLK AB↑, or
B before CLK BA↑
1.0
1.0
1.0
0.9
0.8
th Hold time,
A after CLK AB↑, or
B after CLK BA↑
1.3
1.0
0.9
0.9
0.8
MHz
ns
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
VCC = 1.2V
Typical
VCC = 1.5V
±0.1V
M in.
M ax.
ten
tdis
M in.
M ax.
VCC = 2.5V
±0.2V
M in.
150
fmax
tpd
VCC = 1.8V
±0.15V
M ax.
250
VCC = 3.3V
±0.3V
M in.
M ax.
350
MHz
A or B
B or A
5.0
1.9
4.2
1.5
3.6
1.2
3.2
0.9
2.6
CLKAB or
CLKBA
A or B
5.5
2.0
4.0
1.9
3.8
1.3
3.5
1.0
3.2
SAB or
SBA
B or A
4.8
2.4
4.1
2.0
4.0
1.7
3.8
1.4
3.1
4.5
1.8
3.6
1.5
3.5
1.4
3.0
1.0
2.5
5.5
2.0
4.0
1.8
4.0
1.4
3.7
1.1
3.2
OE or OE A or B
Units
ns
Operating Characteristics, TA = 25°C
Te s t
Conditions
Parame te rs
Cpd Power Dissipation Capacitance
O utputs Enabled
O utputs Disabled
CL = 0pF,
f = 10 MHz
6
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
Typical
Typical
Typical
30
35
40
12
15
20
Units
pF
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V and 1.5V ± 0.1V
2xVCC
S1
2Ω
From Output
Under Test
CL = 15pF
Open
GND
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
VOL
tPHZ
VCC/2
VOH –0.1V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
7
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
2xVCC
S1
12ΩkΩ
From Output
Under Test
CL = 30
15pF
Open
GND
2Ω
1 kΩ
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.15V
VOL
tPHZ
VCC/2
VOH –0.1V
0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
8
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL =30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
9
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ±0.3V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL = 30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.3V
VOL
tPHZ
VCC/2
VOH –0.1V
0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
10
PS8550
07/31/01
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
56-Pin TSSOP (A) Package
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
56-Pin TVSOP (K) Package
56
.169
.177
4.30
4.50
0.09
0.20
.0035
.008
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Orde ring D ata
D e s cription
PI74AVC+16652A
56- pin, 240 mil wide plastic TSSO P
PI74AVC+16652K
56- pin, 173 mil wide plastic TVSO P
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
11
PS8550
07/31/01