R1LV0208BSA 2Mb Advanced LPSRAM (256k word x 8bit) R10DS0050EJ0100 Rev.1.00 2011.03.30 Description The R1LV0208BSA is a family of low voltage 2-Mbit static RAMs organized as 262,144-word by 8-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LV0208BSA has realized higher density, higher performance and low power consumption. The R1LV0208BSA is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. The R1LV0208BSA has been packaged in 32-pin sTSOP. Features • • • • • • • • Single 2.7~3.6V power supply Small stand-by current: 1µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1# and CS2 Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Orderable Part Name R1LV0208BSA-5SR#B0 R1LV0208BSA-5SI#B0 R1LV0208BSA-7SR#B0 R1LV0208BSA-7SI#B0 R1LV0208BSA-5SR#S0 R1LV0208BSA-5SI#S0 R1LV0208BSA-7SR#S0 R1LV0208BSA-7SI#S0 Access time 55 ns 70 ns 55 ns 70 ns R10DS0050EJ0100 Rev.1.00 2011.03.30 Temperature Range Package Shipping Container Quantity Tray Max. 234pcs/Tray Max. 1872pcs/Inner Box Embossed tape 1000pcs/Reel 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 8mm×13.4mm 32-pin plastic sTSOP (normal-bend type) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C PTSA0032KB-A (32P3K-B) -40 ~ +85°C Page 1 of 13 R1LV0208BSA Pin Arrangement A11 1 32 OE# A9 2 31 A10 A8 3 30 CS1# A13 4 29 DQ7 WE# 5 28 DQ6 CS2 6 27 DQ5 A15 7 26 DQ4 Vcc 8 25 DQ3 A17 9 24 GND A16 10 23 DQ2 A14 11 22 DQ1 A12 12 21 DQ0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 32-pin sTSOP Pin Description Pin name Function Vcc Vss A0 to A17 DQ0 to DQ7 CS1# Power supply Ground Address input Data input/output Chip select 1 CS2 WE# OE# Chip select 2 Write enable Output enable R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 2 of 13 R1LV0208BSA Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 256k-word x8-bit A17 DQ0 DQ DQ1 BUFFER SENSE / WRITE AMPLIFIER DQ7 COLUMN DECODER CLOCK GENERATOR WE# Vcc Vss CS1# CS2 OE# R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 3 of 13 R1LV0208BSA Operation Table CS1# CS2 WE# OE# DQ0~7 Operation X L X X High-Z Stand-by H X X X High-Z Stand-by L H L X Din Write L H H L Dout Read L H H H High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr*3 Value -0.5 to +4.6 -0.5*1 to Vcc+0.5*2 0.7 R Ver. 0 to +70 I Ver. Tstg Tbias*3 -40 to +85 -65 to 150 R Ver. I Ver. unit V V W °C °C 0 to +70 -40 to +85 °C 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +4.6V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 4 of 13 R1LV0208BSA DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 2.7 3.0 3.6 V Supply voltage Note Vss 0 0 0 V Input high voltage VIH 2.0 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.6 V 1 0 - +70 °C 2 -40 - +85 °C 2 Ambient temperature range Note R Ver. Ta I Ver. 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. DC Characteristics Parameter Input leakage current Output leakage current Average operating current Standby current Symbol Min. Typ. Max. Unit | ILI | - - 1 μA | ILO | - - 1 μA ICC1 - 15 25 mA ICC2 - 2 5 mA ISB - - 0.33 mA - 1*1 2 μA ~+25°C - - 3 μA ~+40°C - - 8 μA ~+70°C - - 10 μA ~+85°C VOH 2.4 - - V IOH = -0.5mA VOH2 Vcc - 0.5 - - V IOH = -0.05mA VOL - - 0.4 V IOL = 2mA Standby current Test conditions Vin = Vss to Vcc CS1# =VIH or CS2 =VIL or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1μs, duty =100%, II/O = 0mA CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V (1) CS1# =VIH, Others =VIH/VIL or (2) CS2 =VIL, Others =VIH/VIL ISB1 Output high voltage Output low voltage Note Vin = Vss to Vcc (1) CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 5 of 13 R1LV0208BSA Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2) Parameter Symbol Min. Typ. Max. Unit Test conditions Input capacitance C in 8 pF Vin =0V Input / output capacitance C I/O 10 pF VI/O =0V Note 1. This parameter is sampled and not 100% tested. 2. Ambient temperature range depends on R/I-version. Please see table on page 1. Note 1 1 AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.2V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ CL = 30 pF Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 6 of 13 R1LV0208BSA Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z R10DS0050EJ0100 Rev.1.00 2011.03.30 Symbol tRC tAA tACS1 tACS2 tOE tOH tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ R1LV0208BSA-5S* R1LV0208BSA-7S* Min. 55 10 10 10 5 0 0 0 Min. 70 10 10 10 5 0 0 0 Max. 55 55 55 30 20 20 20 Max. 70 70 70 35 25 25 25 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 Page 7 of 13 R1LV0208BSA Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note Symbol tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ R1LV0208BSA-5S* R1LV0208BSA-7S* Min. 55 50 50 45 0 0 25 0 5 0 0 Min. 70 55 55 50 0 0 30 0 5 0 0 Max. 20 20 Max. 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns Note 5 4 6 7 2 1,2 1,2 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#. A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low. A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode. R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 8 of 13 R1LV0208BSA Timing Waveforms Read Cycle tRC A0~17 tOH tAA tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 WE# tCHZ2 VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~7 R10DS0050EJ0100 Rev.1.00 2011.03.30 Valid Data Page 9 of 13 R1LV0208BSA Write Cycle (1) (WE# CLOCK) tWC A0~17 tCW CS1# tCW CS2 tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~7 tOW Valid Data tDW R10DS0050EJ0100 Rev.1.00 2011.03.30 tDH Page 10 of 13 R1LV0208BSA Write Cycle (2) (CS1#, CS2 CLOCK) tWC A0~17 tAW tAS tCW tWR tAS tCW tWR CS1# CS2 tWP WE# OE# VIH OE# = “H” level tDW DQ0~7 R10DS0050EJ0100 Rev.1.00 2011.03.30 tDH Valid Data Page 11 of 13 R1LV0208BSA Low Vcc Data Retention Characteristics Parameter VCC for data retention Symbol VDR Min. Typ. Max. Test conditions*2 Unit 2.0 - 3.6 V Vin ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V - 1*1 2 μA ~+25°C Vcc=3.0V, Vin ≥ 0V Data retention current Chip deselect to data retention time Operation recovery time Note - - 3 μA ~+40°C - - 8 μA ~+70°C - - 10 μA ~+85°C 0 5 - - ns ms See retention waveform. ICCDR tCDR tR (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#, DQ) can be in the high impedance state. R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 12 of 13 R1LV0208BSA Low Vcc Data Retention Timing Waveforms (1) CS1# Controlled Vcc tCDR 2.7V 2.7V tR VDR 2.2V 2.2V CS1# ≥ Vcc - 0.2V CS1# (2) CS2 Controlled Vcc tCDR CS2 2.7V 2.7V tR VDR 0.2V 0.2V 0V ≤ CS2 ≤ 0.2V R10DS0050EJ0100 Rev.1.00 2011.03.30 Page 13 of 13 Revision History R1LV0208BSA Data Sheet Rev. Date Page 1.00 2011.03.30 - Description Summary First Edition issued All trademarks and registered trademarks are the property of their respective owners. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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