Product Specification PE3239 2.2 GHz Integer-N PLL for Low Phase Noise Applications Product Description Peregrine’s PE3239 is a high performance integer-N PLL capable of frequency synthesis up to 2.2 GHz. The superior phase noise performance of the PE3239 is ideal for applications such as wireless local loop basestations, LMDS systems and other demanding terrestrial systems. Features • 2.2 GHz operation • 10/11 prescaler • Internal phase detector with charge pump • Serial programmable • Low power 20 mA at 3 V • Ultra-low phase noise • Available in 20-lead TSSOP The PE3239 features a 10/11 dual modulus prescaler, counters, phase detector and a charge pump as shown in Figure 1. Counter values are programmable through a three wire serial interface. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE3239 offers excellent RF performance with the economy and integration of conventional CMOS. Figure 1. Block Diagram Fin Fin Prescaler 10/11 Main Counter 13 Sdata Primary 20-bit 20 Latch Secondary 20-bit Latch Phase Detector 20 20 6 fr PEREGRINE SEMICONDUCTOR CORP. | PD_U PD_D Charge Pump CP 6 R Counter http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2001 Page 1 of 13 PE3239 Product Specification Figure 2. Pin Configuration VDD 1 20 fr ENH 2 19 GND S_WR 3 18 N/C Sdata 4 17 CP Sclk 5 16 VDD GND 6 15 Dout FSELS 7 14 LD E_WR 8 13 Cext VDD 9 12 GND Fin 10 11 Fin Table 1. Pin Descriptions Pin No. Pin Name Type Description 1 VDD (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required. 2 Enh Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-up resistor. 3 S_WR Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR rising edge. 4 Sdata Input Binary serial data input. Input data entered MSB first. 5 Sclk Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. 6 GND 7 FSELS Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters. Internal 70 kΩ pull-down resistor. 8 E_WR Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor. 9 VDD (Note 1) Same as pin 1. 10 Fin Input Prescaler input from the VCO. Max frequency input is 2.2 GHz. 11 Fin Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor to the ground plane. 12 GND 13 Cext Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 14 LD Output Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). 15 Dout Output Data out function, Dout, enabled in enhancement mode. 16 VDD (Note 1) Same as pin 1. Ground. Ground. Copyright Peregrine Semiconductor Corp. 2001 Page 2 of 13 File No. 70/0047~01A | UTSi CMOS RFIC SOLUTIONS PE3239 Product Specification Pin No. Pin Name 17 CP Output Charge pump current is sourced when fc leads fp and sinked when fc lags fp. 18 NC Output No connection. 19 GND 20 fr Note 1: Type Description Ground. Input Reference frequency input. VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level. Table 2. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Min Electrostatic Discharge (ESD) Precautions Max Units Supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD + 0.3 V II DC into any input -10 +10 mA IO DC into any output -10 +10 mA Storage temperature range -65 150 °C Tstg Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Table 3. Operating Ratings Symbol When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C Table 4. ESD Ratings Symbol VESD Note 1: Parameter/Conditions ESD voltage human body model (Note 1) Level Units 1000 V Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2001 Page 3 of 13 PE3239 Product Specification Table 5. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter Operational supply current; Prescaler enabled Conditions Min Typ Max Units 20 26 mA 0.3 x VDD V +1 µA VDD = 2.85 to 3.15 V Digital Inputs: S_WR, Sdata, Sclk VIH High level input voltage VDD = 2.85 to 3.15 V VIL Low level input voltage VDD = 2.85 to 3.15 V 0.7 x VDD IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V -1 0.7 x VDD V µA Digital Inputs: Enh (contains a 70 kΩ pull-up resistor) VIH High level input voltage VDD = 2.85 to 3.15 V VIL Low level input voltage VDD = 2.85 to 3.15 V V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V -100 µA VDD = 2.85 to 3.15 V 0.7 x VDD V 0.3 x VDD V +1 µA Digital Inputs: FSELS, E_WR (contains a 70 kΩ pull-down resistor) VIH High level input voltage VIL Low level input voltage VDD = 2.85 to 3.15 V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V 0.3 x VDD V +100 µA µA -1 Reference Divider input: fr IIHR High level input current VIH = VDD = 3.15 V IILR Low level input current VIL = 0, VDD = 3.15 V +100 µA µA -100 Counter output: Dout VOLD Output voltage LOW Iout = 6 mA VOHD Output voltage HIGH Iout = -3 mA 0.4 VDD - 0.4 V V Lock detect outputs: (Cext, LD) VOLC Output voltage LOW, Cext Iout = 0.1 mA VOHC Output voltage HIGH, Cext Iout = -0.1 mA VOLLD Output voltage LOW, LD Iout = 1 mA 0.4 VDD - 0.4 V V 0.4 V Charge Pump output: CP ICP – Source Drive current VCP = VDD / 2 -2.6 -2 -1.4 mA ICP – Sink Drive current VCP = VDD / 2 1.4 2 2.6 mA -1 ICPL ICP – Source VS. 1CP Sink ICP VS. VCP µA VCP = VDD / 2, TA = 25° C % 1.0 V < VCP < VDD – 1.0 V TA = 25° C 15 % 1.0 V < VCP < VDD – 1.0 V Output current magnitude variation vs. voltage Copyright Peregrine Semiconductor Corp. 2001 Page 4 of 13 1 15 Leakage current Sink vs. source mismatch File No. 70/0047~01A | UTSi CMOS RFIC SOLUTIONS PE3239 Product Specification Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units 10 MHz Control Interface and Latches (see Figures 5, 6, 7) fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tDSU Sdata set-up time to Sclk rising edge 10 ns tDHLD Sdata hold time after Sclk rising edge 10 ns tPW S_WR pulse width 30 ns tCWR Sclk rising edge to S_WR rising edge 30 ns Sclk falling edge to E_WR transition 30 ns tCE tWRC tEC S_WR falling edge to Sclk rising edge 30 ns E_WR transition to Sclk rising edge 30 ns Main Divider (Including Prescaler) Fin Operating frequency PFin Input level range External AC coupling 200 2200 MHz -5 5 dBm 20 220 MHz -5 5 dBm Main Divider (Prescaler Bypassed) Fin Operating frequency PFin Input level range External AC coupling Reference Divider fr Operating frequency (Note 3) Pfr Reference input power (Note 2) Single ended input Comparison frequency (Note 3) 100 -2 MHz dBm Phase Detector fc 20 MHz Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80mV/ns. Note 3: Parameter is guaranteed through characterization only and is not tested. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2001 Page 5 of 13 PE3239 Product Specification Typical Performance Data (VDD = 3.00V, TA = 25°C) Figure 3. Typical RF Input Sensitivity 0 -5 (dBm) -10 -15 -20 -25 -30 0 500 1000 1500 2000 2500 3000 Frequency (MHz) Figure 4. Typical Phase Noise Performance -60 -70 (dBc/Hz) -80 Frequency = 1300 MHz Reference = 10 MHz Loop Band Width = 30 kHz Comparison Frequency = 1.25MHz -90 -100 -110 -120 -130 100 1000 10000 100000 1000000 Frequency Offset (Hz) Copyright Peregrine Semiconductor Corp. 2001 Page 6 of 13 File No. 70/0047~01A | UTSi CMOS RFIC SOLUTIONS PE3239 Product Specification Functional Description The PE3239 consists of a prescaler, counters, a phase detector, charge pump and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals which direct the charge pump operation. The control logic includes a selectable chip interface. Data is written into the internal registers via the three wire serial bus. There are also various operational and test modes and a lock detect output. Figure 5. Functional Block Diagram R Counter (6-bit) fr Sdata Control Pins Control Logic fc PD_U R(5:0) Phase Detector M(8:0) PD_D Charge Pump CP A(3:0) LD Cext Modulus Select Fin Fin PEREGRINE SEMICONDUCTOR CORP. | 10/11 Prescaler M Counter (9-bit) http://www.peregrine-semi.com fp Copyright Peregrine Semiconductor Corp. 2001 Page 7 of 13 PE3239 Product Specification Main Counter Chain Register Programming The main counter chain divides the RF input frequency, Fin, by an integer derived from the user defined values in the “M” and “A” counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9 bit M counter. Setting Pre_en “low” enables the 10/11 prescaler. Setting Pre_en “high” allows Fin to bypass the prescaler and powers down the prescaler. Serial Interface Mode The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] where A ≤ M + 1, M ≠ 0 (1) When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) where A ≤ M + 1, M ≠ 0 (2) A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of “1” will result in a minimum M Counter divide ratio of “2”. Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR according to the timing diagrams shown in Figure 6. Data are transferred to the counters as shown in Table 7 on page 9. The double buffering provided by the primary and secondary registers allows for “ping-pong” counter control using the FSELS input. When FSELS is “high”, the primary register contents set the counter inputs. When FSELS is “low”, the secondary register contents are utilized. While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 6. After the falling edge of E_WR, the data provide control bits as shown in Table 8 on page 9 will have their bit functionality enabled by asserting the Enh input “low”. The output frequency of the 6 bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) where R > 0 (3) Note that programming R equal to “0” will pass the reference frequency, fr, directly to the phase detector. Copyright Peregrine Semiconductor Corp. 2001 Page 8 of 13 File No. 70/0047~01A | UTSi CMOS RFIC SOLUTIONS PE3239 Product Specification Table 7. Primary Register Programming Interface Mode Enh R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 Serial* 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 8. Enhancement Register Programming Interface Mode Enh Reserved Reserved fp Output Power down Counter load MSEL output fc output Reserved Serial* 0 B0 B1 B2 B3 B4 B5 B6 B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. MSB (first in) (last in) LSB Figure 6. Serial Interface Mode Timing Diagram Sdata E_WR tEC tCE Sclk S_WR tDSU PEREGRINE SEMICONDUCTOR CORP. | tDHLD http://www.peregrine-semi.com tClkH tClkL tCWR tPW tWRC Copyright Peregrine Semiconductor Corp. 2001 Page 9 of 13 PE3239 Product Specification Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Bit Function Bit 0 Reserved** Bit 1 Reserved** Bit 2 fp output Description Drives the M counter output onto the Dout output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 fc output Bit 7 Reserved** Drives the reference counter output onto the Dout output ** Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The signals from the phase detector couple directly to a charge pump. PD_U controls a current source at pin CP with constant amplitude and pulse duration approximately the same as PD_U. PD_D similarly drives a current sink at pin CP. The current pulses from pin CP are low pass filtered externally and then connected to the VCO tune voltage. PD_U pulses result in a current source, which increases the VCO frequency and PD_D results in a current sink, which decreases VCO frequency when using a positive Kv VCO. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Figure 7. Typical PE3239 Loop Filter Application Example Charge Pump To VCO Tune R C2 C1 Copyright Peregrine Semiconductor Corp. 2001 Page 10 of 13 File No. 70/0047~01A | UTSi CMOS RFIC SOLUTIONS PE3239 Product Specification Figure 8. Package Drawing 20-lead TSSOP (JEDEC MO-153-AC) TOP VIEW 0.65BSC 1 9 2 0 3.2 0 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 2 X 4.40±0.1 0 Ø1.00±0.1 0 1.0 0 -B- 1.0 0 1 2 3 4 5 6 7 8 9 1 0 .20 C B A 0.32 5 -A- 6.40±0.1 0 0.90±0.0 5 1.10 MAX -C- 0.10 C 0.10±0.0 5 0.30 MAX 0.10 C B A SIDE VIEW FRONT VIEW PEREGRINE SEMICONDUCTOR CORP. | 6.4 0 http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2001 Page 11 of 13 PE3239 Product Specification Table 10. Ordering Information Order Code Part Marking 3239-11 PE3239 3239-12 PE3239 3239-00 PE3239EK Description Shipping Method PE3239-20TSSOP-74A 20-lead TSSOP PE3239-20TSSOP-2000C 20-lead TSSOP 2000 units / T&R PE3239-20TSSOP-EVAL KIT Evaluation Board 1 / Box Copyright Peregrine Semiconductor Corp. 2001 Page 12 of 13 Package 74 units / Tube File No. 70/0047~01A | UTSi CMOS RFIC SOLUTIONS PE3239 Product Specification Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770 The Imperial Tower, 15th floor 1-1-1 Uchisaiawaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 03-3507-5755 Fax: 03-3507-5601 Europe Australia Peregrine Semiconductor Europe Peregrine Semiconductor Australia Aix-En-Provence Office Parc Club du Golf, bat 9 13856 Aix-En-Provence Cedex 3 France Tel 33-0-4-4239-3360 Fax 33-0-4-4239-7227 8 Herb Elliot Ave. Homebush, NSW 2140 Australia Tel: 011-61-2-9763-4111 Fax: 011-61-2-9746-1501 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents may be pending or applied for. UTSi, the Peregrine logotype, SEL Safe, and Peregrine Semiconductor Corp. are registered trademarks of Peregrine Semiconductor Corp. All PE product names and prefixes are trademarks of Peregrine Semiconductor Corp. Copyright © 2001 Peregrine Semiconductor Corp. All rights reserved. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2001 Page 13 of 13