PRODUCT SPECIFICATION PE83512 Military Operating Temperature Range DC - 1500 MHz Low Power CMOS Divide-by-4 Prescaler Product Description The PE83512 is a high-performance static CMOS prescaler with a fixed divide ratio of 4. Its operating frequency range is DC to 1500 MHz. The PE83512 operates on a nominal 3 V supply and draws only 14mA. It is packaged in a small 8-lead plastic MSOP and is ideal for frequency scaling and clock generation solutions. Features • DC to 1500 MHz operation • Fixed divide ratio of 4 • Low-power operation: 14mA typical @ 3.0 V • Ultra small package: 8-lead plastic MSOP The PE83512 is manufactured in Peregrine’s patented Ultra-Thin Silicon (UTSi ) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 2. Package Type Figure 1. Functional Schematic Diagram 3.05 2.85 8-lead MSOP 5.05 4.75 Table 1. Electrical Specifications (ZS = ZL = 50 Ω) 2.85V ≤ VDD ≤ 3.15 V; -55° C ≤ TA ≤ 125° C, unless otherwise specified Parameter Conditions Minimum Typical Maximum Units 2.85 3.0 3.15 V OUTB Disabled 7 12 mA OUTB Enabled 14 25 mA DC 1500 MHz -5 +10 dBm 0 +10 dBm 1200 MHz < Fin ≤ 1500 MHz -55°C ≤ TA ≤ 85°C +5 +10 dBm DC < Fin ≤ 1500MHz +2 Supply Voltage Supply Current 1 Input Frequency (FIN) 100 MHz ≤ Fin ≤ 1200 MHz -55°C ≤ TA ≤ 85°C Input Power (PIN) 100 MHz ≤ Fin ≤ 1200 MHz 85°C ≥ TA ≥ 125°C Output Power PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com dBm Copyright Peregrine Semiconductor Corp. 2003 Page 1 of 6 PE83512 Product Specification Figure 3. Pin Configuration Electrostatic Discharge (ESD) Precautions VDD 1 IN 2 8 GND 7 OUT When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. PE83512 N/C 3 6 CTL GND 4 5 OUTB Latch-Up Avoidance Table 2. Pin Descriptions Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Pin No. Pin Name 1 VDD Power supply pin. Bypassing is required (eg 1000 pF & 100 pF). 2 4.75 IN Input signal pin. Should be coupled with a capacitor (eg 1000 pF). Description 3 N/C No connection. This pin should be left open. 4 GND Ground pin. Ground pattern on the board should be as wide as possible to reduce ground impedance. 5 OUTB Inverted divided frequency output. This pin should be coupled with a capacitor (eg 1000 pF). 6 CTL Control pin. When grounded OUTB is enabled. 7 OUT Divided frequency output pin. This pin should be coupled with a capacitor (eg 1000 pF). 8 GND Ground Pin. Device Functional Considerations The PE83512 divides an input signal, up to a frequency of 1500 MHz, by a factor of four thereby producing an output frequency at one fourth the input frequency. To work properly at higher frequency, the input and output signals (pins 2 , 7 & optional 5) must be AC coupled via an external capacitor, as shown in the test circuit in Figure 4. The input may be DC coupled for low frequency operation with care taken to remain within the specified DC input range for the device. The ground pattern on the board should be made as wide as possible to minimize ground impedance. See Figure 7 for a layout example. OUTB Control Table 3. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Min Max Units Supply voltage 4.0 V Pin Input Power 15 dBm VIN Voltage on input VDD +0.3 V TST Storage temperature range -65 150 °C TOP Operating temperature range -55 125 °C 2000 V VESD ESD voltage (Human Body Model, MIL-STD 883) Copyright Peregrine Semiconductor Corp. 2003 Page 2 of 6 -0.3 Pin 6 controls weather OUTB is enabled or disabled. Pin 6 has an internal pull-up resistor. With no connection (floating), OUTB is disabled. By grounding pin 6, OUTB is enabled. By enabling OUTB, this part will use roughly 5 mA more current. File No. 70/0117~02A| UTSi CMOS RFIC SOLUTIONS PE83512 Product Specification Typical Performance Data: VDD = 3.0V Figure 4. Input Sensitivity Figure 5. Device Current (OUTB Enabled) Figure 6. Output Power (OUT or OUTB) PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 3 of 6 PE83512 Product Specification Figure 7. Evaluation Board Schematic Diagram J2-7 J1 C10 10 pF Figure 8. Evaluation Board Layout C2 1000 pF VDD GND IN OUT C3 1000pF C1 1000pF PE83512 N/C CTL GND OUT / J3 C4 1000pF J4 J5 Evaluation Kit Operation The PE83512 EK board was designed to ease customer evaluation of Peregrine’s high performance Military Grade divide-by-4 Prescaler. On this board, the device input (pin 2) is connected via J1 and a 50 Ω transmission line. A series capacitor (C3) provides the necessary DC block for the device input. It is important to note that the value of this capacitance will impact the performance of the device. A value of 1000 pF was found to be optimal for this board layout; other applications may require a different value. The device output (pin 7) is connected to connector J3 through a 50 Ω transmission line. A series capacitor (C1) provides the necessary DC block for the device output. Note that this capacitor must be chosen to have low impedance at the desired output frequency the device. The value of 1000pF was chosen to provide a wide operating range for the evaluation board. The board is constructed of a two-layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF Copyright Peregrine Semiconductor Corp. 2003 Page 4 of 6 transmission lines. The transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. Note that the predominate mode for these transmission lines is coplanar waveguide. J2 provides DC power to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device VDD pin (1). Two decoupling capacitors (10pF, 1000pF) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. Applications Support If you have a problem with your evaluation kit or if you have applications questions call (858) 455-0660 and ask for applications support. You may also contact us by fax or e-mail: Fax: (858) 455-0770 E-Mail: [email protected] File No. 70/0117~02A| UTSi CMOS RFIC SOLUTIONS PE83512 Product Specification Figure 9. Package Drawing 8 Lead Plastic MSOP TOP VIEW 0.65BSC .525BSC 8 7 6 5 2.45±0.10 2X 3.00±0.10 0.51±0.13 -B2 1 0.51±0.13 3 4 2.95±0.10 .25 A B C -C0.86±0.08 2.95±0.10 1.10 MAX -A0.33+0.07 -0.08 0.08 A B C 0.10 A 3.00±0.10 4.90±0.15 0.10±0.05 3.00±0.10 FRONT VIEW SIDE VIEW Table 4. Ordering Information Order Code Part Marking Description Package Shipping Method 83512-01 PE83512 PE83512-08MSOP-50A 8-lead MSOP 83512-02 PE83512 PE83512-08MSOP-2000C 8-lead MSOP 2000 units / T&R 83512-00 PE83512-EK PE83512-08MSOP-EK Evaluation Kit 1 / Box PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com 50 units / Tube Copyright Peregrine Semiconductor Corp. 2003 Page 5 of 6 PE83512 Product Specification Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770 5A-5, 5F Imperial Tower 1-1-1 Uchisiawaicho, Chiyoda-ku, Tokyo, Japan 100-011 Tel. 011-81-3-3502-5211 Fax. 011-81-3-3502-5213 Europe Peregrine Semiconductor Europe Aix-En-Provence Office Parc Club du Golf, bat 9 13856 Aix-En-Provence Cedex 3 France Tel 33-0-4-4239-3360 Fax 33-0-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com Data Sheet Identification Advance Information The information in this data sheet is believed to be reliable. However, The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising Product Specification out of the use of its products in such applications. The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice). Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending. Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright © 2002 Peregrine Semiconductor Corp. All rights reserved. Copyright Peregrine Semiconductor Corp. 2003 Page 6 of 6 File No. 70/0117~02A| UTSi CMOS RFIC SOLUTIONS