RICHTEK RT8857

RT8857/A
4/3/2/1-Phase PWM Controller with Embedded Drivers
for CPU Core Power Supply
General Description
Features
The RT8857/A is a 4/3/2/1-phase synchronous buck
controller with 2 integrated MOSFET drivers for Intel
VR11.1/VR10.x and AMD K8/K8_M2 CPUs power
application. RT8857/A uses differential inductor DCR
current sense to achieve phase current balance and active
voltage positioning. Other features include adjustable
operating frequency, adjustable soft start, power good
indication, external error-amp compensation, over voltage
protection, over current protection, VRHOT sensing and
IMON for various applications. RT8857/A comes to a small
footprint with WQFN-48L 7x7 package
z
z
z
z
z
z
z
z
z
z
z
z
ments of IPC/JEDEC J-STD-020.
EN/VTT
RoHS compliant and compatible with the current require-
VID7
(TOP VIEW)
VID6
Richtek products are :
VID5
z
VID4
VIN is the input voltage of MOSFET power stage.
Pin Configurations
VID3
z
z
VID2
Note :
z
VID1
Support VIN : 5/12V
Support VIN : 12V
z
VID0
Lead Plating System
G : Green (Halogen Free and Pb Free)
z
PSI
Package Type
QW : WQFN-48L 7x7 (W-Type)
VIDSEL
RT8857/A
`
z
VOUT
Ordering Information
12V Power Supply Voltage
4/3/2/1-Phase Power Conversion
2 Embedded MOSFET Drivers
Internal Regulated 5V Output
VID table for INTEL VR11.1/VR10.x and AMD K8/
K8_M2 CPUs
Continuous Differential Inductor DCR Current Sense
Adjustable Soft Start
Adjustable Frequency
Power Good Indication
Adjustable Over Current Protection
Over Voltage Protection
VRHOT Sensing with External Thermistor
IMON Output Current Indication
Power State Indicator (PSI)
Support MOSFET Power Stage Input Voltage (VIN)
Down to 5V (RT8857A Only)
Small 48-Lead WQFN Package
RoHS Compliant and Halogen Free
48 47 46 45 44 43 42 41 40 39 38 37
`
Suitable for use in SnPb or Pb-free soldering processes.
Applications
z
z
Desktop CPU Core Power
Low Voltage, High Current DC/ DC Converter
FBRTN
QR1
QR2
SS/EN
COMP
FB
OFS
RT
ADJ
IMAX
IMAXPSI
IMONFB
1
36
2
35
3
34
4
33
5
32
6
31
GND
7
30
8
29
9
28
10
27
49
26
11
25
12
PWRGD
BOOT1
UGATE1
PHASE1
LGATE1
VCC12
LGATE2
PHASE2
UGATE2
BOOT2
PWM3
PWM4
VCC5
TSEN
VRHOT
ISP1
ISN2
ISN1
ISP3
ISP2
ISN3
ISN4
ISP4
IMON
13 14 15 16 17 18 19 20 21 22 23 24
WQFN-48L 7x7
DS8857/A-01 April 2011
www.richtek.com
1
www.richtek.com
2
L2
L2
5V
12V
12V
VTT
PWM
GND
VCC
PWM
GND
VCC
LGATE
RT9619
PHASE
UGATE
BOOT
RT9619
LGATE
PHASE
UGATE
BOOT
NTC2
12V
12V
5V
PWM4
14
ISP4
15 ISN4
25
2 QR1
17 ISP3
16 ISN3
26 PWM3
3 QR2
48 VOUT
11 IMAXPSI
24 VCC5
7 OFS
8
RT
EN/VTT
GND Exposed Pad (49)
FBRTN 1
SS/EN 4
3
VCC12 1
COMP 5
ISP2 18
19
ISN2
FB 6
PHASE2 29
3
LGATE2 0
ISP1 21
ISN1 20
38 to 45
VID[7:0]
37
EN/VTT
47
PSI
PWRGD 36
2
BOOT2 7
2
UGATE2 8
RT8857/A
22
VRHOT
23
TSEN
3
9 ADJ
BOOT1 5
UGATE1 34
12 IMONFB
13
PHASE1 33
IMON
3
LGATE1 2
10 IMAX
12V
VIN
VIN
L2
L1
NTC1
LOAD
VCORE
RT8857/A
Typical Application Circuit
DS8857/A-01 April 2011
RT8857/A
Table 1. VR11.1 VID CodeTable
VID7 VID6 VID5 VID4 VID3 VID 2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
0
0
0
0
0
0
0
OFF
0
0
1
0
0
0
1
1
1.39375
0
0
0
0
0
0
0
1
OFF
0
0
1
0
0
1
0
0
1.38750
0
0
0
0
0
0
1
0
1.60000
0
0
1
0
0
1
0
1
1.38125
0
0
0
0
0
0
1
1
1.59375
0
0
1
0
0
1
1
0
1.37500
0
0
0
0
0
1
0
0
1.58750
0
0
1
0
0
1
1
1
1.36875
0
0
0
0
0
1
0
1
1.58125
0
0
1
0
1
0
0
0
1.36250
0
0
0
0
0
1
1
0
1.57500
0
0
1
0
1
0
0
1
1.35625
0
0
0
0
0
1
1
1
1.56875
0
0
1
0
1
0
1
0
1.35000
0
0
0
0
1
0
0
0
1.56250
0
0
1
0
1
0
1
1
1.34375
0
0
0
0
1
0
0
1
1.55625
0
0
1
0
1
1
0
0
1.33750
0
0
0
0
1
0
1
0
1.55000
0
0
1
0
1
1
0
1
1.33125
0
0
0
0
1
0
1
1
1.54375
0
0
1
0
1
1
1
0
1.32500
0
0
0
0
1
1
0
0
1.53750
0
0
1
0
1
1
1
1
1.31875
0
0
0
0
1
1
0
1
1.53125
0
0
1
1
0
0
0
0
1.31250
0
0
0
0
1
1
1
0
1.52500
0
0
1
1
0
0
0
1
1.30625
0
0
0
0
1
1
1
1
1.51875
0
0
1
1
0
0
1
0
1.30000
0
0
0
1
0
0
0
0
1.51250
0
0
1
1
0
0
1
1
1.29375
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
0
1
0
0
1.28750
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
0
1
0
1
1.28125
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0
1.27500
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
0
1
1
1
1.26875
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
0
0
1.26250
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
0
0
1
1.25625
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
0
1
0
1.25000
0
0
0
1
1
0
0
0
1.46250
0
0
1
1
1
0
1
1
1.24375
0
0
0
1
1
0
0
1
1.45625
0
0
1
1
1
1
0
0
1.23750
0
0
0
1
1
0
1
0
1.45000
0
0
1
1
1
1
0
1
1.23125
0
0
0
1
1
0
1
1
1.44375
0
0
1
1
1
1
1
0
1.22500
0
0
0
1
1
1
0
0
1.43750
0
0
1
1
1
1
1
1
1.21875
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
0
0
0
1.21250
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
0
0
1
1.20625
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
0
1
0
1.20000
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
0
0
1
1
1.19375
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
0
1
0
0
1.18750
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
0
1
0
1
1.18125
To be continued
DS8857/A-01 April 2011
www.richtek.com
3
RT8857/A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
1
0
0
0
1
1
0
1.17500
0
1
1
0
1
0
1
0
0.95000
0
1
0
0
0
1
1
1
1.16875
0
1
1
0
1
0
1
1
0.94375
0
1
0
0
1
0
0
0
1.16250
0
1
1
0
1
1
0
0
0.93750
0
1
0
0
1
0
0
1
1.15625
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
1
0
1
0
1.15000
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
1
0
1
1
1.14375
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
0
0
1
1
0.89375
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
0
1
0
0
0.88750
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
0
1
0
1
0.88125
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
0
1
1
0
0.87500
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
0
1
1
1
0.86875
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
0
0
0
0.86250
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
1
1
0
1.07500
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
1
1
1
1.06875
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
1
0
0
0
1.06250
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
1
0
0
1
1.05625
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
1
0
1
0
1.05000
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
1
0
1
1
1.04375
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
1
1
0
0
1.03750
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
1
1
0
1
1.03125
1
0
0
0
0
0
0
1
0.80625
0
1
0
1
1
1
1
0
1.02500
1
0
0
0
0
0
1
0
0.80000
0
1
0
1
1
1
1
1
1.01875
1
0
0
0
0
0
1
1
0.79375
0
1
1
0
0
0
0
0
1.01250
1
0
0
0
0
1
0
0
0.78750
0
1
1
0
0
0
0
1
1.00625
1
0
0
0
0
1
0
1
0.78125
0
1
1
0
0
0
1
0
1.00000
1
0
0
0
0
1
1
0
0.77500
0
1
1
0
0
0
1
1
0.99375
1
0
0
0
0
1
1
1
0.76875
0
1
1
0
0
1
0
0
0.98750
1
0
0
0
1
0
0
0
0.76250
0
1
1
0
0
1
0
1
0.98125
1
0
0
0
1
0
0
1
0.75625
0
1
1
0
0
1
1
0
0.97500
1
0
0
0
1
0
1
0
0.75000
0
1
1
0
0
1
1
1
0.96875
1
0
0
0
1
0
1
1
0.74375
0
1
1
0
1
0
0
0
0.96250
1
0
0
0
1
1
0
0
0.73750
0
1
1
0
1
0
0
1
0.95625
1
0
0
0
1
1
0
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4
1 0.73125
To be continued
DS8857/A-01 April 2011
RT8857/A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
1
0
0
0
1
1
1
0
0.72500
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
1
1
1
0.71875
1
1
1
1
1
1
1
0
OFF
1
0
0
1
0
0
0
0
0.71250
1
1
1
1
1
1
1
1
OFF
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
DS8857/A-01 April 2011
www.richtek.com
5
RT8857/A
Table 2. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
1
0
1
0
1
1
1.60000V
0
1
0
1
0
1
0
1.59375V
0
1
0
1
1
0
1
1.58750V
0
1
0
1
1
0
0
1.58125V
0
1
0
1
1
1
1
1.57500V
0
1
0
1
1
1
0
1.56875V
0
1
1
0
0
0
1
1.56250V
0
1
1
0
0
0
0
1.55625V
0
1
1
0
0
1
1
1.55000V
0
1
1
0
0
1
0
1.54375V
0
1
1
0
1
0
1
1.53750V
0
1
1
0
1
0
0
1.53125V
0
1
1
0
1
1
1
1.52500V
0
1
1
0
1
1
0
1.51875V
0
1
1
1
0
0
1
1.51250V
0
1
1
1
0
0
0
1.50625V
0
1
1
1
0
1
1
1.50000V
0
1
1
1
0
1
0
1.49375V
0
1
1
1
1
0
1
1.48750V
0
1
1
1
1
0
0
1.48125V
0
1
1
1
1
1
1
1.47500V
0
1
1
1
1
1
0
1.46875V
1
0
0
0
0
0
1
1.46250V
1
0
0
0
0
0
0
1.45625V
1
0
0
0
0
1
1
1.45000V
1
0
0
0
0
1
0
1.44375V
1
0
0
0
1
0
1
1.43750V
1
0
0
0
1
0
0
1.43125V
1
0
0
0
1
1
1
1.42500V
1
0
0
0
1
1
0
1.41875V
1
0
0
1
0
0
1
1.41250V
1
0
0
1
0
0
0
1.40625V
1
0
0
1
0
1
1
1.40000V
1
0
0
1
0
1
0
1.39375V
1
0
0
1
1
0
1
1.38750V
1
0
0
1
1
0
0
1.38125V
1
0
0
1
1
1
1
1.37500V
1
0
0
1
1
1
0
1.36875V
1
0
1
0
0
0
1
1.36250V
To be continued
www.richtek.com
6
DS8857/A-01 April 2011
RT8857/A
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
0
1
0
0
0
0
1.35625V
1
0
1
0
0
1
1
1.35000V
1
0
1
0
0
1
0
1.34375V
1
0
1
0
1
0
1
1.33750V
1
0
1
0
1
0
0
1.33125V
1
0
1
0
1
1
1
1.32500V
1
0
1
0
1
1
0
1.31875V
1
0
1
1
0
0
1
1.31250V
1
0
1
1
0
0
0
1.30625V
1
0
1
1
0
1
1
1.30000V
1
0
1
1
0
1
0
1.29375V
1
0
1
1
1
0
1
1.28750V
1
0
1
1
1
0
0
1.28125V
1
0
1
1
1
1
1
1.27500V
1
0
1
1
1
1
0
1.26875V
1
1
0
0
0
0
1
1.26250V
1
1
0
0
0
0
0
1.25625V
1
1
0
0
0
1
1
1.25000V
1
1
0
0
0
1
0
1.24375V
1
1
0
0
1
0
1
1.23750V
1
1
0
0
1
0
0
1.23125V
1
1
0
0
1
1
1
1.22500V
1
1
0
0
1
1
0
1.21875V
1
1
0
1
0
0
1
1.21250V
1
1
0
1
0
0
0
1.20625V
1
1
0
1
0
1
1
1.20000V
1
1
0
1
0
1
0
1.19375V
1
1
0
1
1
0
1
1.18750V
1
1
0
1
1
0
0
1.18125V
1
1
0
1
1
1
1
1.17500V
1
1
0
1
1
1
0
1.16875V
1
1
1
0
0
0
1
1.16250V
1
1
1
0
0
0
0
1,15625V
1
1
1
0
0
1
1
1.15000V
1
1
1
0
0
1
0
1.14375V
1
1
1
0
1
0
1
1.13750V
1
1
1
0
1
0
0
1.13125V
1
1
1
0
1
1
1
1.12500V
1
1
1
0
1
1
0
1.11875V
To be continued
DS8857/A-01 April 2011
www.richtek.com
7
RT8857/A
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
1
1
1
0
0
1
1.11250V
1
1
1
1
0
0
0
1.10625V
1
1
1
1
0
1
1
1.10000V
1
1
1
1
0
1
0
1.09375V
1
1
1
1
1
0
1
OFF
1
1
1
1
1
0
0
OFF
1
1
1
1
1
1
1
OFF
1
1
1
1
1
1
0
OFF
0
0
0
0
0
0
1
1.08750V
0
0
0
0
0
0
0
1.08125V
0
0
0
0
0
1
1
1.07500V
0
0
0
0
0
1
0
1.06875V
0
0
0
0
1
0
1
1.06250V
0
0
0
0
1
0
0
1.05625V
0
0
0
0
1
1
1
1.05000V
0
0
0
0
1
1
0
1.04375V
0
0
0
1
0
0
1
1.03750V
0
0
0
1
0
0
0
1.03125V
0
0
0
1
0
1
1
1.02500V
0
0
0
1
0
1
0
1.01875V
0
0
0
1
1
0
1
1.01250V
0
0
0
1
1
0
0
1.00625V
0
0
0
1
1
1
1
1.00000V
0
0
0
1
1
1
0
0.99375V
0
0
1
0
0
0
1
0.98750V
0
0
1
0
0
0
0
0.98125V
0
0
1
0
0
1
1
0.97500V
0
0
1
0
0
1
0
0.96875V
0
0
1
0
1
0
1
0.96250V
0
0
1
0
1
0
0
0.95625V
0
0
1
0
1
1
1
0.95000V
0
0
1
0
1
1
0
0.94375V
0
0
1
1
0
0
1
0.93750V
0
0
1
1
0
0
0
0.93125V
0
0
1
1
0
1
1
0.92500V
0
0
1
1
0
1
0
0.91875V
0
0
1
1
1
0
1
0.91250V
0
0
1
1
1
0
0
0.90625V
0
0
1
1
1
1
1
0.90000V
To be continued
www.richtek.com
8
DS8857/A-01 April 2011
RT8857/A
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
0
1
1
1
1
0
0.89375V
0
1
0
0
0
0
1
0.88750V
0
1
0
0
0
0
0
0.88125V
0
1
0
0
0
1
1
0.87500V
0
1
0
0
0
1
0
0.86875V
0
1
0
0
1
0
1
0.86250V
0
1
0
0
1
0
0
0.85625V
0
1
0
0
1
1
1
0.85000V
0
1
0
0
1
1
0
0.84375V
0
1
0
1
0
0
1
0.83750V
0
1
0
1
0
0
0
0.83125V
DS8857/A-01 April 2011
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9
RT8857/A
Table 3. Output Voltage Program (K8)
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage DACOUT
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.200
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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10
DS8857/A-01 April 2011
RT8857/A
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
0
1
1
1.0750
0
1
0
1
0
0
1.0500
0
1
0
1
0
1
1.0250
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
0
1
1
0
1
1
0.8750
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
To be continued
DS8857/A-01 April 2011
www.richtek.com
11
RT8857/A
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
www.richtek.com
12
DS8857/A-01 April 2011
RT8857/A
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
FBRTN
Negative Remote Sense Pin of Output Voltage.
2
QR1
Quick Response Setting Pins for Load Transition.
3
QR2
Quick Response Setting Pins for Load Transition.
4
SS/EN
5
COMP
Output of error-amp and input of PWM comparator.
6
FB
Inverting input of error-amp.
7
OFS
Connect this pin to GND or 5V by a resistor to set no-load offset voltage.
8
RT
Connect this pin to GND by a resistor to adjust frequency.
9
ADJ
Connect this pin to GND by a resistor to set load line.
10
IMAX
11
IMAXPSI
OCP Setting in Power Saving Mode.
12
IMONFB
Current Monitor Gain/Offset Adjustment.
13
IMON
Current Monitor Output.
Connect this pin to GND by a capacitor to adjust soft start time.
Pull this pin to GND to disable controller.
Negative input of OCP comparator. (Positive input of OCP comparator
is ADJ).
14, 17, 18, 21
ISP4, ISP3, ISP2, ISP1 Positive current sense pin of channel 1, 2, 3 and 4.
15, 16, 19, 20
ISN4, ISN3, ISN2, ISN1 Negative current sense pin of channel 1, 2, 3 and 4.
22
VRHOT
Temperature Monitor Output.
23
TSEN
Temperature Sense Input.
24
VCC5
5V LDO Output for System Power Supply.
25, 26
PWM4, PWM3
PWM Output for Channel 4 and Channel 3.
27, 35
BOOT2, BOOT1
Bootstrap Supply for Channel 2 and Channel 1.
28, 34
UGATE2, UGATE1
Upper Gate Driver for Channel 2 and Channel 1.
29, 33
PHASE2, PHASE1
Switching Node of Channel 2 and Channel 1.
30, 32
LGATE2, LGATE1
Lower Gate Driver for Channel 2 and Channel 1.
31
VCC12
IC Power Supply. Connect to 12V.
36
PWRGD
Power Good Indicator.
37
EN/VTT
VTT Voltage Detector Input.
VID7 to VID0
Voltage Identification Input for DAC.
PSI
Power Status Indicator II.
38 to 45
47
48
VOUT
Feedback of Regulated Output.
46
VIDSEL
VID DAC Selection Pin.
49
(Exposed pad)
The exposed pad must be soldered to a large PCB and connected to
GND
VID Table Selection
VIDSEL VID [7]
GND for maximum power dissipation.
Table
VTT
X
VR11
GND
X
VR10.x
VCC5
VTT
K8
VCC5
GND
K8_M2
DS8857/A-01 April 2011
www.richtek.com
13
RT8857/A
Function Block Diagram
Modulator
Waveform
Generator
RT
VCC12
Power-On
Reset
POR
5V
Regulator
COMP
VCC5
EA
+
FB
BOOT1
Offset
OFS
UGATE1
MOSFET
Driver
+
PHASE1
-
LGATE1
+
OV
+
150mV
BOOT2
+
-
Transient
Response
Enhancement
VOUT
QR1/QR2
OE
SS/EN
EN/VTT
+
UGATE2
PHASE2
LGATE2
+
PWM3
OV
OC
VIDOFF
POR
MOSFET
Driver
Soft Start
and
Fault
Logic
OE
+
PWM4
-
OE
PSI
+
VID
Table
Generator
-
I_SEN2
+
FBRTN
-
+
VIDSEL
VID7 to VID0
-
-
I_SEN3
+
+
-
OC
-
www.richtek.com
14
+
IMONFB
GND
CH1
Current
SENSE
CH2
Current
SENSE
ISP1
ISN1
ISP2
ISN2
AVG
ADJ
IMAX/
IMAXPSI
I_SEN1
+
850mV
Load Current
Monitor
Temperature
Monitor
IMON
TSEN
I_SEN4
CH3
Current
SENSE
CH4
Current
SENSE
ISP3
ISN3
ISP4
ISN4
VRHOT
DS8857/A-01 April 2011
RT8857/A
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
(Note 1)
Supply Input Voltage -------------------------------------------------------------------------------------------- −0.3V to 15V
BOOTx to PHASEx --------------------------------------------------------------------------------------------- −0.3V to 15V
BOOTx to GND
DC ------------------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 200ns ------------------------------------------------------------------------------------------------------------ −0.3V to 42V
PHASEx to GND
DC ------------------------------------------------------------------------------------------------------------------- −2V to 15V
< 200ns ------------------------------------------------------------------------------------------------------------ −5V to 30V
Input/Output Voltage -------------------------------------------------------------------------------------------- −0.3V to (VCC5 +0.3)V
Power Dissipation, PD @ TA = 25°C
WQFN−48L 7x7 -------------------------------------------------------------------------------------------------- 3.226W
Package Thermal Resistance (Note 2)
WQFN−48L 7x7, θJA -------------------------------------------------------------------------------------------- 31°C/W
Junction Temperature ------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------- 260°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
z
z
z
(Note 4)
Supply Voltage, VCC12 ---------------------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range ---------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------- 0°C to 70°C
Electrical Characteristics
(VCC12 = 12V, VGND = 0V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
10.8
12
13.2
V
--
6
--
mA
4.75
5.0
5.25
V
10
--
--
mA
VCC12 Supply Input
VCC12 Supply Voltage
VCC12
VCC12 Supply Current
ICC
VCC5 Power
VCC5 Supply Voltage
VCC5
ILOAD = 10mA
(Note 5)
VCC5 Output Sourcing
Power-On Reset
IVCC5
VCC12 Rising Threshold
V VCC12TH
VCC12 Rising
9.2
9.6
10.0
V
VCC12 Hysteresis
V VCC12HY
VCC12 Falling
--
0.9
--
V
--
VTT
(Note 6)
--
V
0.80
0.85
0.90
V
--
100
--
mV
Load Current Monitor
IMON Maximum Output
Voltage
EN/VTT
EN/VTT Rising Threshold
V ENVTT
Enable Hysteresis
V ENVTTHY EN/VTT Falling
EN/VTT Rising
To be continued
DS8857/A-01 April 2011
www.richtek.com
15
RT8857/A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1V to 1.6V
−0.5
--
+0.5
%
0.8V to 1V
−5
--
+5
mV
0.5V to 0.8V
−8
--
+8
mV
Reference Voltage accuracy
DAC Accuracy
Error Amplifier
DC Gain
ADC
No Load
--
80
--
dB
Gain-Bandwidth
GBW
CLOAD = 10pF
--
10
--
MHz
Slew Rate
Output voltage range
SR
VCOMP
CLOAD = 10pF
10
0.5
--
-3.6
V/us
V
Max Current
IEA_SLEW
Slew
300
--
--
uA
PWRGD Low Voltage
VPGOOD
IPWRGD = 4mA
--
--
0.4
V
Soft-Start Delay
TD1
--
2
--
ms
V BOOT Duration
TD3
--
0.8
--
ms
PWRGD Delay
TD5
Measured the time form VBOOT change
to PWRGD = 1
--
1.6
--
ms
Max Current
IGMMAX
VCSP = 1.3V
Sink Current from CSN
100
--
--
uA
Input Offset Voltage
VOSCS
−2
0
+2
mV
Running Frequency
fOSC
RRT = 40kΩ
270
300
330
kHz
RT Pin Voltage
Ramp Slope
VRT
VRAMP
RRT = 40kΩ
RRT = 40kΩ
0.76
--
0.8
22
0.84
--
V
%/V
Soft Start Current
ISS1
Slew
12
16
20
uA
VID Change Current
Gate Driver
ISS2
Slew
120
160
200
uA
UGATE Drive Source
RUGATEsr
--
1
--
Ω
UGATE Drive Sink
RUGATEsk
--
1
--
Ω
LGATE Drive Source
RLGATEsr
BOOT − PHASE = 8V
250mA Source Current
BOOT − PHASE = 8V
250mA Sink Current
VLGATE = 8V
--
1
--
Ω
LGATE Drive Sink
RLGATEsk
250mA Sink Current
--
0.8
--
Ω
Over-Voltage Threshold
VOVP
Sweep FB Voltage, V FB − VEAP
125
150
175
mV
Over-Current Threshold
VOCP
Sweep IMAX Voltage, VIMAX − V ADJ
−10
0
+10
mV
--
15
--
ns
--
10
--
ns
Power Sequence
Current Sense Amplifier
Soft Start
Protection
Dynamic Characteristic
UGATE Rise Time
trUGATE
UGATE Fall Time
tfUGATE
LGATE Rise Time
trLGATE
--
15
--
ns
LGATE Fall Time
tfLGATE
--
10
--
ns
Ciss = 3000p
To be continued
www.richtek.com
16
DS8857/A-01 April 2011
RT8857/A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
1/2VTT +
12.5mV
--
V
Input Threshold
VID7 to VID0,
VID7 to 0,
VIDSEL Rising Threshold VIDSEL
VID7 to VID0 Rising,
VIDSEL Rising
VID7 to VID0 Hysteresis
VID7 to 0_Hy VID7 to VID0 Falling
--
25
--
mV
PSI Rising Threshold
VPSI
--
1/2VTT +
12.5mV
--
V
PSI Rising
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of
JEDEC thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Test condition : RT8857/A normal operating, an extra static DC current load 10mA applying at VCC5 pin.
Note 6. The maximum output voltage of power monitor will be restricted by EN/VTT pin input voltage.
DS8857/A-01 April 2011
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17
RT8857/A
Application Information
Frequency vs. RRT
RT8857/A is a 4/3/2/1-phase synchronous buck DC/DC
converter with 2 embedded MOSFET drivers. The internal
VID DAC is designed to interface with the Intel VR11.x/
10.x and AMD K8/K8_M2 compatible CPUs.
During start-up, RT8857/A will detect VCC12, VCC5 and
VTT. When VCC12 > 9.6V, VCC5 > 4.6V and VTT > 0.85V,
POR will go high. POR (Power On Reset) is the internal
signal to indicate all powers are ready to let RT8857/A
and the companioned MOSFET drivers work properly.
When POR = L, RT8857/A will try to turn off both high
side and low side MOSFETs.
1000
Frequency (kHz)
Power Ready Detection
1200
800
600
400
200
0
0
40
80
120
160
200
240
280
RRT (k
ohm)
(kΩ)
VCC12
9.6V
VCC5
+
+
4.6V
V TT
0.85V
CMP
POR
+
Figure 2. RRT vs Phase Switching Frequency
CMP
CMP
POR : Power On Reset
-
Soft Start
Output current of OPSS (ISS) is limited and variant
V DAC
OPSS
+
-
SSQ
Figure 1. Circuit for Power Ready Detection
SS
Phase Detection
The number of operational phases is determined by the
internal circuitry that monitors the ISNn voltages during
start up. Normally, the RT8857/A operates as a 4-phase
PWM controller. Pull ISN4 and ISP4 to VCC5 programs
3-phase operation, pull ISN3 and ISP3 to VCC5 programs
2-phase operation, and pull ISN2 and ISP2 to VCC5
programs 1-phase operation. RT8857/A detects the voltage
of ISN4, ISN3 and ISN2 at POR rising edge. At the rising
edge, RT8857/A detects whether the voltage of ISN4, ISN3
and ISN2 are higher than “VCC5 − 1V” respectively to
decide how many phases should be active. Phase
detection is only active during start up. When POR = H,
the number of operational phases is determined and
latched. The unused PWM pins can be connected to 5V
or GND or left floating.
C SS
+-
EAP
(ErrorAmp positive input)
ADJ
R ADJ
NTC
Figure 4. Circuit for Soft Start and Dynamic VID
The VOUT start-up time is set by a capacitor from the SS
pin to GND. In power_on_reset state (POR = L), the SS
pin is held at GND. After power_on_reset stae (POR = H)
and an extra delay 1600us, VSS and VSSQ begin to rise till
VSSQ = VBOOT. When VSSQ = VBOOT, RT8857/A stays in
this state for 800us waiting for valid VID code sent by
CPU. After receiving valid VID code, VOUT continues
ramping up or down to the voltage specified by VID code.
Before PWRGD = H, output current of OPSS (ISS) is
limited to 8uA (ISS1). When PWRGD = H, ISS is limited to
80uA (ISS2). The soft start waveform is shown in Figure 5.
Phase Switching Frequency
The phase switching frequency of the RT8857/A is set by
an external resistor connected from the RT pin to GND.
The frequency follows the graph in Figure 2.
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18
DS8857/A-01 April 2011
RT8857/A
Output Voltage Differential Sensing
VTT
0.85V
VCC12
9.6V
The RT8857/A uses differential sensing by a high gain
low offset ErrorAmp. The CPU voltage is sensed between
VCC5
4.6V
the FB and FBRTN pins. A resistor (RFB) connects FB pin
VDAC
SS
SSQ
VBOOT
SS
SSQ
T1
PWRGD
T2
T3
T4
T5
No-Load Offset
Figure 5. Soft Start Waveforms
VOUT will trace VEAP which is equal to “VSSQ − VADJ”.
VADJ is a small voltage signal which is proportional to
IOUT. This voltage is used to generate loadline and will be
described later. T1 is the delay time from power_on_reset
state to the beginning of VOUT rising.
T1 = 1600μs + 0.6V x CSS / ISS1
and the positive remote sense pin of the CPU (VCCP).
FBRTN pin connects to the negative remote sense pin of
CPU (VCCN) directly. The ErrorAmp compares EAP (=
VDAC −VADJ) with the VFB to regulate the output voltage.
(1)
In Figure 6, IOFSN or IOFSP are used to generate no-load
offset. Either IOFSN or IOFSP is active during normal operation.
It should be noted that users can only enable one polarity
of no-load offset. Do not connect OFS pin to GND and to
VCC5 at the same time. Connect a resistor from OFS pin
to GND to activate IOFSN. IOFSN flows through RADJ from
ADJ pin to GND. In this case, negative no-load offset voltage
(VOFSN) is generated.
T2 is the soft start time from VOUT = 0 to VOUT = VBOOT.
VOFSN = IOFSN x RADJ = 0.8 x RADJ/ROFS
T2 = VBOOT x CSS / ISS1
Connect a resistor from OFS pin to VCC5 to activate IOFSP.
IOFSP flows through RFB from the VCCP to FB pin. In this
case, positive no-load offset voltage (VOFSP) is generated.
(2)
T3 is the dwelling time for VOUT = VBOOT. T3 = 800us.
T4 is the soft start time from VOUT = VBOOT to VOUT = VDAC.
T4 ~= |VDAC - VBOOT| x CSS/ISS1
(3)
T5 is the power good delay time, T5 ~= 1600us.
Dynamic VID
The RT8857/A can accept VID input changing while the
controller is running. This allows the output voltage (VOUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, VOUT should follow VDAC which is a staircase
waveform. In RT8857/A, as mentioned in soft start session,
VDAC slew rate is limited by ISS2/CSS when PWRGD = H.
This slew rate limiter works as a low pass filter of VDAC
and makes the bandwidth of VDAC waveform finite. By
smoothening VDAC staircase waveform, VOUT will no longer
overshoot or undershoot. On the other hand, CSS will
increase the settling time of VOUT during VID OTF. In most
cases, 1nF to 30nF ceramic capacitor is suitable for CSS.
DS8857/A-01 April 2011
(4)
When positive no-load offset is selected, the RT8857/A
will generate another internal 8uA current source to
eliminate dead zone problem of droop function. This 8uA
current will be injected into ADJ resistors, producing a
small initial negative no-load offset. Therefore, when OFS
pin is connected to VCC5 through a resistor, the positive
no-load offset can be calculated as :
VOFSP = IOFSP × RFB − 8uA × RADJ
R
= 6.4 × FB − 8uA × R ADJ
ROFS
(5)
RT8857/A provides wide range no-load positive offset for
over-clocking applications. The IOFSP capability can supply
from 30uA to 640uA, which means in Equation (5), ROFS
can range from 240kΩ to 10kΩ. Other resistances of ROFS
exceeding this range can also provide no-load positive
offset but cannot be guaranteed by Equation (5).
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19
RT8857/A
C2
C FB
R FB
VCCP
(Positive remote
sense pin of CPU)
C1
R1
FB
IOFSP
+
(Negative remote
sense pin of CPU)
VCCN
Output Current Sensing
V DAC
+EAP
EA
+
COMP
to the equation below :
L/DCR = RS x CS
-
FBRTN
The RT8857/A provides low input offset current-sense
amplifier (CSA) to monitor the output current of every
channel. Output current of CSA (IX[n]) is used for channel
current balance and active voltage position. In this inductor
current sensing topology, RS and CS must be set according
IOFSN
R ADJ
ADJ
(6)
Then the output current of CSA will follow the equation
below :
IX = [IL x DCR − VOFS-CSA + 235n x (RCSP − RCSN)]
Figure 6. Circuit for VOUT Differential Sensing and No
Load Offset
Load Transient Quick Response
RT8857/A utilizes a new quick response feature to supply
heavy load current demand during instantaneous load
application transient. RT8857/A detects load transient and
reacts via VOUT pin. When VOUT drops during load
application transient,the quick response comparator will
send asserted signals to turn on high side MOSFETs and
turn off low side MOSFETs. The LA1 signal, which is a
weaker quick response signal, will turn on only arbitrary
two channels', high side MOSFETs while turning off low
side MOSFETs also. The LA2 signal , which is a stronger
quick response signal, will turn on all channel's high side
MOSFETs while turning off low side MOSFETs also.
Therefore, the influence of total quick response function
of RT8857/A is adjustable, and the magnitude of quick
response is flexible via fine-tuning the resistors connected
to pin QR1 and QR2.
IOUT
V OUT
/RCSN
(7)
235nA is typical value of CSA input offset current.
VOFS-CSA is the input offset voltage of CSA. VOFS-CSA of
RT8857/A is smaller than +/- 1mV. Usually, “VOFS-CSA +
235n x (RCSP − RCSN)” is negligible except at very light
load and the equation can be simplified as the equation
below :
IX = IL x DCR/RCSN
(8)
Loadline
Output current of CSA is summed and averaged in
RT8857/A. Then 0.5Σ(IX[n]) is sent to ADJ pin. Because
ΣIX[n] is a PTC (Positive Temperature Coefficient) current,
an NTC (Negative Temperature Coefficient) resistor is
needed to connect ADJ pin to GND. If the NTC resistor is
properly selected to compensate the temperature
coefficient of IX[n], the voltage on ADJ pin will be
proportional to IOUT without temperature effect. In RT8857/
A, the positive input of ErrorAmp is “VDAC − VADJ”. VOUT
will follow “VDAC − VADJ”, too. Thus, the output voltage
decreasing linearly with IOUT is obtained. The loadline is
defined as
LL(loadline) = ΔVOUT/ΔIOUT = ΔVADJ/ΔIOUT
= 0.5 x DCR x RADJ/RCSN
(9)
Briefly, the resistance of RADJ sets the resistance of
loadline. The temperature coefficient of RADJ compensates
the temperature effect of loadline.
QR2
QR1
Current Balance
Figure 7
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20
In Figure 8, IX[n] is the current signal which is proportional
to current flowing through channel n. In Figure 9, the
DS8857/A-01 April 2011
RT8857/A
current error signals IERRn (= IX[n] − AVG(IX[n])) are used
to raise or lower the internal sawtooth waveforms
(RAMP[1] to RAMP[n]) which are compared with ErrorAmp
output (COMP) to generate PWM signal. The raised
sawtooth waveform will decrease the PWM duty of the
corresponding channel while the lowered will increase.
Eventually, current flowing through each channel will be
balanced.
CSA: Current Sense Amplifier
ISP
DCR
RS
CS
I2
IOUT , total
Constant ratio
I1
I2
IOUT , total
R ISP
+
235nA
V OFS_CSA
IX
L
I1
Constant difference
+
ISN
-
R ISN
Figure 10. Channel Current vs. Total Current
235nA
Over Current Protection (OCP)
Figure 8. Circuit for Channel Current Sensing
COMP
RAMP[1]
Interleaved
RAMP[n]
+
-
+
CMP
-
BUF
PWM[1]
IERR[1] x RCB
+
-
+
CMP
-
BUF
PWM[n]
IERR[n] x RCB
Figure 9. Circuit for Channel Current Balance
Channel Current Adjust
If channel current is not balanced due to asymmetric PCB
layout of power stage, external resistors can be adjusted
to correct current imbalance. Figure 10 shows two types
of current imbalance, constant ratio type and constant
difference type.
If the initial current distribution is constant ratio type,
according to Equation (8), reduce RCSN[1] can reduce IL[1]
and improve current balance. If the initial current distribution
is constant difference type, according to Equation (7),
increase RCSP[1] can reduce IL[1] and improve current
balance.
DS8857/A-01 April 2011
RT8857/A provides sing phase OCP and multi-phase OCP
according to the operation condition. In Figure 11, single
phase OCP (IMAXPSI) and multi-phase OCP (IMAX)
thresholds can be set by external resistors :
R2 + R3
R1 + R2 + R3
R3
VIMAXPSI = VCC5 ×
R1 + R2 + R3
VIMAX = VCC5 ×
(10)
(11)
Once VADJ is larger than the negative input of CP
comparator, OCP will be triggered and latched, and
RT8857/A will turn off both high side and low side
MOSFETs of all channels. A 20us delay after OCP
detection is used to prevent false trigger.
Over Voltage Protectiom (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds “VEAP + 150mV”, OVP
is triggered and latched. RT8857/A will try to turn on low
side MOSFET and turn off high side MOSFET to protect
CPU. A 20us delay is used in OVP detection circuit to
prevent false trigger.
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21
RT8857/A
VCC5
V CC5
R1
0.28 x V CC5
R1
IMAX
R2
OCP
+
IMAXPSI
+
TSEN
-
S
Q
-
R NTC
VRHOT
R
+
R3
-
ADJ
0.33 x V CC5
Figure 11. Over Current Protection
Figure 13. Thermal Monitoring
Output Current Monitoring (IMON)
Power State Indicator (PSI)
RT8857/A senses load current and output a voltage signal
to indicated the instantaneous load current status. Since
the sensed total current is injected into the resistors
connected to ADJ pin, ADJ voltage than is used for IMON
function as shown in Figure 12. Through the resistor
network R1, R2 and R3, IMON voltage will be proportional
to ADJ pin voltage according to the Equation :
VIMON =
R3
× VADJ − R3 × VTT
R1 // R2 // R3
R1
(12)
VTT
ADJ
IMONFB
+
R3
R1
VTT
R2
IMON
Figure 12. Output Current Monitoring
Thermal Monitoring (VRHOT)
RT8857/A provides thermal monitoring function via sensing
TSEN pin voltage. Through the voltage divider R1 and RNTC,
the voltage of TSEN is typically set to be higher than
0.33 x VCC5 when ambient temperature is lower than
VRHOT assertion target. When ambient temperature rises,
TSEN voltage will fall, and VRHOT signal will be set to
high if TSEN voltage drops below 0.28 x V CC5 .
Accordingly, VRHOT will be reset to low once TSEN
voltage rises above 0.33 x VCC5. Correctly choose the
resistance of R1 and RNTC can assert and de-assert VRHOT
accurately at target ambient temperature.
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22
The RT8857/A supports PSI# function for VR11.1 CPUs
and platform users. The RT8857/A will monitor PSI pin
input voltage to change the operating state. When PSI is
high (higher than 1/2 VTT + 12.5mV), the RT8857/A
operates as a full-channel interleaving PWM controller and
all channels are active. When input voltage is low (lower
than VTT + 12.5mV), the RT8857/A will change to single
phase operation mode and only channel 1 is active. Since
channel 2 includes embedded driver, the RT8857/A will
automatically disable channel 2 by forcing UGATE2 and
LGATE2 into high impedance state when input voltage is
low. The RT8857/A will also disable channel 3 and channel
4 by sending continuous tri-state signals (~2.5V) from
PWM3 and PWM4 to external drivers when input voltage
is low. Therefore, 2 external drivers which support tri-state
shutdown should be used if PSI function is considered,
and the RT9619 is recommended to be the external drivers
for VR11.1 compatibility.
During PSI asserted period, e.g., input voltage is low, if
the RT8857/A receives dynamic VID change command,
the RT8857/A will enter interleaving mode operation and
all channels will be activated. PSI command will be ignored
during dynamic VID operation, and PSI will be blanked for
about 100us after dynamic VID change is completed.
Loop Compensation
The RT8857/A is a synchronous Buck converter with two
control loops : voltage loop and current balance loop. Since
the function of the current balance loop is to maintain the
current balance between each active channel, its influence
to converter stability will be negligible compared with the
voltage feedback loop. Therefore, to compensate the
DS8857/A-01 April 2011
RT8857/A
voltage loop will be the main task to maintain converter
stability.
C2
R2
C1
The converter duty-to-output transfer function Gd is :
R1
VOUT
D
Gd =
1+
S
R L
C
+
(13)
S2
⎛ 1 ⎞
⎜
⎟
⎝ LC ⎠
EA
+
+ V REF
-
2
Figure 14. Type-II Compensation
and the modulator gain of the converter is :
(14)
Where VOUT is the output voltage of the converter, R is
the loading resistance, L and C are the output inductance
and capacitance, and VP is the peak-to-peak voltage of
ramp applied at modulator input. The overall loop gain after
compensation can be described as :
Loop Gain = T = Gd x Fm x A
(15)
Where A denotes as compensation gain. To compensate
a typical voltage mode buck converter, there are two
ordinary compensation schemes, well known as type-II
compensator and type-III compensator. The choice of using
type-II or type-III compensator will be up to platform
designers, and the main concern will be the position of
the capacitor ESR zero and mid-frequency to highfrequency gain boost. Typically, the ESR zero of output
capacitor will tend to stabilize the effect of output LC double
poles, hence the positon of the output capacitor ESR zero
in frequency domain may influence the design of voltage
loop compensation. If FZERO,ESR is <1/2FCO where FCO
denotes cross-over frequency, type-II compensation will
be sufficient for voltage stability. If FZERO,ESR is > 1/2FCO
(or higher gain and phase margin is required at midfrequency to high-frequency), then type-III compensation
may be a better solution for voltage loop compensation.
A typical type-II compensation network is shown in
Figure 14.
R1 can be determined independently from DC
considerations. Normally choose R1 that the current
passing by will be around 1mA. Therefore,
R1 =
VREF
1mA
(16)
Then determine R2 by the boosted gain of loop gain at
crossover :
R2 = R1×
2
VP
VIN(MAX)
⎛ FZERO, ESR ⎞
FCO
×⎜
×
⎟
F
F
LC
ZERO, ESR
⎝
⎠
(17)
Where VIN(MAX) is the max input voltage of power stage,
VP is the peak-to-peak voltage of ramp applied at modulator
input, FZERO,ESR is the frequency of output capacitor ESR
zero, and FLC is the frequency of output LC :
FZERO, ESR =
FLC =
1
2π × RESR × C
(18)
1
2π × LC
(19)
After determining the phase margin at crossover
frequency, the position of zero and pole produced by
type-II compensation network, FZ and FP, can then be
determined. The bode plot of type-II compensation is
shown in Figure15, where
Gain (dB)
Fm = 1
VP
FZ
FP
Frequency (Hz)
Figure 15. Bode Plot of Type-II Compensation
DS8857/A-01 April 2011
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23
RT8857/A
1
2π × R2 × C1
1
FP =
2π × R2 × (C1 // C2)
FZ =
(20)
After determining desired phase margin, according to the
following Equation :
(21)
F
F
tan-1 ⎛⎜ CO ⎞⎟ − tan-1 ⎛⎜ Z ⎞⎟ ≥ P.M. + 45 D
2
⎝ FZ ⎠
⎝ FCO ⎠
and
FZ can be determined by the following Equation :
-1 ⎛ FCO
tan ⎜
⎝ FZ
⎞ − tan-1 ⎛ FZ
⎟
⎜F
⎠
⎝ CO
⎞ ≥ 90D
⎟
⎠
FP =
⎛
⎞
FCO
+P.M. − tan-1 ⎜
⎟
F
ZERO,
ESR
⎝
⎠
(22)
By properly choosing FZ to fit equation (22), C1 can then
be determined by :
1
(23)
C1 =
2π × R2 × FZ
and C2 can be determined by :
1
C2 =
F2
2π × R2 × CO − 1
FZ
C1
(24)
FZ and FP can be determined by choosing proper FCO to
FZ ratio to meet Equation (25). Again, R1 can be determined
by the Equation (16).
R2 can be determined by the following Equation :
R2 = R1×
C3
R2
R1
(27)
Other component values of the Type-III compensation can
then be calculated as :
1
2π × R2 × FZ
1
C2 =
2π × R2 × FP − 1
C1
1
C3 =
2π × R1× FZ
1
R3 =
2π × C3 × FP
C1
(28)
(29)
(30)
(31)
EA
+
For best performance of the RT8857/A, the following
guidelines must be strictly followed :
`
Input bulk capacitors and MLCCS have to be put near
high side MOSFETs. The connection plane of input
capacitors and high side MOSFETs then can be kept as
square as possible.
`
The shape of phase planes (the connection plane
between high side MOSFETs, low side MOSFETs and
output inductors) have to be as square as possible. Long
traces, thin bars or separated islands must be avoided
in phase planes.
`
Keep snubber circuits or damping elements near its
objects. Phase RC snubbers have to be close to low
side MOSFETs, UGATE damping resistors have to be
close to high side MOSFETs, and boot to phase damping
resistors have to be close to high side MOSFETs and
phase planes. Also keep the traces of these snubbers
circuits as short as possible.
+ V REF
-
Figure 16. Type-III Compensation
F P = F P1 = F P2
Gain (dB)
2
F
F
× ⎛ CO ⎞ × Z
VIN(MAX) ⎜⎝ FLC ⎟⎠ FCO
VP
Layout Considerations
C2
F Z = F Z1 = F Z2
Frequency (Hz)
Figure 17. Bode Plot of the Type-III Compensation
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24
(26)
C1 =
A typical type-III compensation contains two zeros and
two poles where the extra one zero and one pole compared
with type-II compensation are added for stabilizing the
system when ESR zero is relatively far from LC double
poles in frequency domain. Figure16. and Figure.17 shows
the typical circuit and bode plot of the type-III compensation.
R3
FCO 2
FZ
(25)
DS8857/A-01 April 2011
RT8857/A
`
The area of VIN plane (power stage 12V VIN) and VOUT
plane (output bulk capacitors and inductors connection
plane) have to be as wide as possible. Long traces or
thin bars must be avoided in these planes. The plane
trace width must be wide enough to carry large input/
output current (40mil/A).
`
The following traces have to be wide and short : UGATE,
LGATE, BOOT, PHASE, and VCC12. Make sure the
width of these traces are wide enough to carry large
driving current(at least 40mil).
`
The voltage feedback loop contains two traces, VCC
and VSS, which are Kelvin sensed from CPU socket or
output capacitors. These two traces are suggested above
10mil width and put away from high (di/dt) switching
elements such as high side MOSFETs, low side
MOSFETs, phase plane etc. The circuit elements of
voltage feedback loop, such as feedback loop short
resistors and voltage loop compensation RCs, have to
be kept near the RT8857/A and also away from switching
elements.
`
The current sense mechanism of the RT8857/A is fully
differential Kelvin sense. Therefore, the current sense
loops of the RT8857/A contain two traces : the positive
traces(ISP1 to ISP4) come from the positive node of
output inductors(the node connecting phase plane) and
the negative traces (ISN1 to ISN4) come from the
negative node of output inductors(the node connecting
output plane).
DO NOT connect the current sense traces from phase
plane or output plane. Only connect these traces from
both sides of output inductors can achieve the goal of
precise Kelvin sense. The current sense feedback loops
have to be routed away from switching elements, and
the current sense RC elements have to be put near
their respective ISN or ISP pins of the RT8857/A and
also away from noise switching elements. At lease 10
mil width is suggested for current sense feedback loops.
DS8857/A-01 April 2011
www.richtek.com
25
RT8857/A
Outline Dimension
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
6.950
7.050
0.274
0.278
D2
5.050
5.250
0.199
0.207
E
6.950
7.050
0.274
0.278
E2
5.050
5.250
0.199
0.207
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 48L QFN 7x7 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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26
DS8857/A-01 April 2011