SAMSUNG S6B0796

S6B0796
240 SEG / COM DRIVER FOR STN LCD
January, 2000
Ver. 1.0
Prepared by: Gyeong-Nam, Kim
[email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
S6B0796 Specification Revision History
Version
2
Content
0.0
l
Original
0.1
l
p6, p16 revision
1.0
l
p4 Introduction revision.
Date
June.1999
August.1999
January. 2000
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................4
FEATURES ..........................................................................................................................................................4
BLOCK DIAGRAM ...............................................................................................................................................5
PAD CONFIGURATION (TBD) .............................................................................................................................6
PAD CENTER COORDINATES............................................................................................................................7
PIN DESCRIPTION ..............................................................................................................................................9
FUNCTIONAL DESCRIPTION............................................................................................................................10
BLOCK FUNCTION.....................................................................................................................................10
PIN FUNCTION...........................................................................................................................................11
FUNCTIONAL OPERATIONS......................................................................................................................15
SPECIFICATIONS..............................................................................................................................................18
ABSOLUTE MAXIMUM RATINGS...............................................................................................................18
RECOMMENDED OPERATING CONDITIONS ...........................................................................................18
DC CHARACTERISTICS.............................................................................................................................19
AC CHARACTERISTICS .............................................................................................................................21
PRECAUTION ....................................................................................................................................................28
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS ........................................................................29
TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS......................................30
CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS .........................................................................31
3
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
INTRODUCTION
The S6B0796 is a 240-outputs segment/common driver LSI for graphic dot-matrix liquid
crystal display systems. It is fabricated by low power CMOS high voltage process technology.
This device consists of 240-bits bi-directional shift register, 240-bits data latch and 240-bits
driver. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit
parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are
bi-directional, four data shift directions are pin-selectable.
FEATURES
Both Segment Mode and Common Mode
- Supply voltage for LC driver: +15.0 to +32.0V
- Number of LC driver outputs: 240
- Low output impedance
- Low power consumption
- Supply voltage for the logic system: +2.4V to +5.5V
- CMOS silicon gate process (P-type Silicon Substrate)
- Package: 268-pin TCP (Tape Carrier Package) or Gold bumped chip
Segment Mode
- Shift clock frequency: 20MHz (Max) (Vdd=+5V±10%)
12MHz (Max) (Vdd=+2.4V to +4.5V)
- Adopts a data bus system
- 4- / 8-bit parallel input modes are selectable with a mode (MD) pin
- Automatic transfer function of an enable signal
- Automatic counting function which, in the chip select, causes the internal clock to be stopped
by automatically counting 240 of input data
- Line latch circuit reset function when DISPOFFB active
Common Mode
- Shift clock frequency: 4.0MHz (Max) (vdd=+2.4V to +5.5V)
- Built-in 240-bits bi-directional shift register (divisible into 120-bits ×2)
- Available in a single mode (240-bits shift register)
or in a dual mode (120-bits shift register ×2)
- Shift register circuit reset function when DISPOFFB active
4
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
BLOCK DIAGRAM
V OR
V 12R V 43R
268
FR
DISPOFFB
260
257
267
266
V 5L
265
LEVEL
SHIFTER
Y1
Y2
1
2
Y 239 Y 240
239
240
240 BITS 4-LEVEL DRIVER
240
EIO1
259
EIO2
247
258
XCK
256
L/R
261
MD
262
S/C
246
V 5L
243
V 43L
242
V 12L
241
V OL
240 BITS LEVEL SHIFTER
ACTIVE
CONTROL
240
240 BITS LINE LATCH/SHIFTER
REGISTER
16
LP
244
CONTROL
LOGIC
16
16
16
16
16
16
16
8BITS*2
DATA
LATCH
DATA LATCH CONTROL
8
SP CONVERSION & DATA CONTROL
(4 to 8 or 8to 8)
248
249
250
251
252
253
254
255
D I0 D I1 D I2 D I3 DI4 DI5 DI6 DI7
245
264
V DD
V SS
Figure 1. Block Diagram
5
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
PAD CONFIGURATION
240
1
ððððððððððððððððððððð - - - - - - - - - - ðððððððððððððððððððð
ð
ð
241
Y
ð
ð
S6B0796
(TOP VIEW, Pads Up)
X
ð
ð
(0,0)
245
288
ðððððððððððððð ---------- ððððððððððððð
Figure 2. S6B0796 Chip Configuration
Table 1. S6B0796 Pad Dimensions
Item
Pad NO.
Chip size
-
Pad pitch
Bumped pad size
6
X
Y
16200
1100
1 to 240
65 (Min.)
241 to 292
260 (Min.)
1 to 240
43
108
241 to 244
289 to 292
76
73
58
76
245 to 288
Bumped pad height
Size
1 to 292
14 (Typ.)
Unit
µm
ð
ð
244
292
289
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NAME
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
X
7767.5
7702.5
7637.5
7572.5
7507.5
7442.5
7377.5
7312.5
7247.5
7182.5
7117.5
7052.5
6987.5
6922.5
6857.5
6792.5
6727.5
6662.5
6597.5
6532.5
6467.5
6402.5
6337.5
6272.5
6207.5
6142.5
6077.5
6012.5
5947.5
5882.5
5817.5
5752.5
5687.5
5622.5
5557.5
5492.5
5427.5
5362.5
5297.5
5232.5
5167.5
5102.5
5037.5
4972.5
4907.5
4842.5
4777.5
4712.5
4647.5
4582.5
Y
NO
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NAME
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
Y81
Y82
Y83
Y84
Y85
Y86
Y87
Y88
Y89
Y90
Y91
Y92
Y93
Y94
Y95
Y96
Y97
Y98
Y99
Y100
X
4517.5
4452.5
4387.5
4322.5
4257.5
4192.5
4127.5
4062.5
3997.5
3932.5
3867.5
3802.5
3737.5
3672.5
3607.5
3542.5
3477.5
3412.5
3347.5
3282.5
3217.5
3152.5
3087.5
3022.5
2957.5
2892.5
2827.5
2762.5
2697.5
2632.5
2567.5
2502.5
2437.5
2372.5
2307.5
2242.5
2177.5
2112.5
2047.5
1982.5
1917.5
1852.5
1787.5
1722.5
1657.5
1592.5
1527.5
1462.5
1397.5
1332.5
Y
NO
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
NAME
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
Y135
Y136
Y137
Y138
Y139
Y140
Y141
Y142
Y143
Y144
Y145
Y146
Y147
Y148
Y149
Y150
X
1267.5
1202.5
1137.5
1072.5
1007.5
942.5
877.5
812.5
747.5
682.5
617.5
552.5
487.5
422.5
357.5
292.5
227.5
162.5
97.5
32.5
-32.5
-97.5
-162.5
-227.5
-292.5
-357.5
-422.5
-487.5
-552.5
-617.5
-682.5
-747.5
-812.5
-877.5
-942.5
-1007.5
-1072.5
-1137.5
-1202.5
-1267.5
-1332.5
-1397.5
-1462.5
-1527.5
-1592.5
-1657.5
-1722.5
-1787.5
-1852.5
-1917.5
Y
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
7
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
NO
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
8
NAME
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y172
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Y193
Y194
Y195
Y196
Y197
Y198
Y199
Y200
X
-1982.5
-2047.5
-2112.5
-2177.5
-2242.5
-2307.5
-2372.5
-2437.5
-2502.5
-2567.5
-2632.5
-2697.5
-2762.5
-2827.5
-2892.5
-2957.5
-3022.5
-3087.5
-3152.5
-3217.5
-3282.5
-3347.5
-3412.5
-3477.5
-3542.5
-3607.5
-3672.5
-3737.5
-3802.5
-3867.5
-3932.5
-3997.5
-4062.5
-4127.5
-4192.5
-4257.5
-4322.5
-4387.5
-4452.5
-4517.5
-4582.5
-4647.5
-4712.5
-4777.5
-4842.5
-4907.5
-4972.5
-5037.5
-5102.5
-5167.5
Y
NO
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
NAME
Y201
Y202
Y203
Y204
Y205
Y206
Y207
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
V0L
V12L
V43L
V5L
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
X
-5232.5
-5297.5
-5362.5
-5427.5
-5492.5
-5557.5
-5622.5
-5687.5
-5752.5
-5817.5
-5882.5
-5947.5
-6012.5
-6077.5
-6142.5
-6207.5
-6272.5
-6337.5
-6402.5
-6467.5
-6532.5
-6597.5
-6662.5
-6727.5
-6792.5
-6857.5
-6922.5
-6987.5
-7052.5
-7117.5
-7182.5
-7247.5
-7312.5
-7377.5
-7442.5
-7507.5
-7572.5
-7637.5
-7702.5
-7767.5
-7969
-7969
-7969
-7969
-7460
-7200
-6940
-6680
-6420
-6160
Y
NO
NAME
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
395
344.5
93.5
-127.5
-348.5
-419
-419
-419
-419
-419
-419
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
DUMMY
VDD
VDD
VDD
VDD
VDD
SC
EIO2
D I0
D I1
D I2
D I3
D I4
D I5
D I6
D I7
XCK
D ISPOFFB
LP
EIO1
FR
LR
MD
NC
VSS
VSS
VSS
VSS
VSS
VSS
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
V5R
V43R
V12R
V0R
X
-5900
-5640
-5380
-5120
-4860
-4600
-4340
-4080
-3820
-3560
-3300
-3040
-2780
-2520
-2260
-2000
1770
2030
2290
2550
2810
3070
3330
3590
3850
4110
4370
4630
4890
5150
5410
5670
5930
6190
6450
6710
6970
7230
7969
7969
7969
7969
Y
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-419
-348.5
-127.5
93.5
344.5
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1 to 240
Y1 – Y240
O
LC driver output
241, 292
V0L, V0R
-
Power supply for LC driver
242, 291
V12L, V12R
-
Power supply for LC driver
243, 290
V43L, V43R
-
Power supply for LC driver
244, 289
V5L, V5R
-
Power supply for LC driver
272
L/R
I
Display data shift direction selection
252 to
256
VDD
-
Power supply for logic system(+2.4 to +5.5V)
257
S/C
I
Segment mode/common mode selection
258
EIO2
I/O
Input/output for chip select or data of shift register
259 to
265
DI0 – DI6
I
Display data input for segment mode
266
DI7
I
Display data input for segment mode/Dual mode data input
267
XCK
I
Display data shift clock input for segment mode
268
DISPOFFB
I
Control input for deselect output level
269
LP
I
Latch pulse input/shift clock input for shift register
270
EIO1
I/O
Input/output for chip select or data of shift register
271
FR
I
AC-converting signal input for LC driver waveform
273
MD
I
Mode selection input
275 to
280
VSS
-
Ground(0V)
Table 3 Pin Description
9
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
FUNCTIONAL DESCRIPTION
BLOCK FUNCTION
. Active Control
In case of segment mode, controls the selection or deselection of the chip. Following a LP
signal, and after the chip select signal is input, a select signal is generated internally until 240
bits of data have been read in. Once data input has been completed, a select signal for
cascade connection is output, and the chip is deselected. In case of common mode, controls
the input/output data of bidirectional pins.
. SP Conversion & Data Control
In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode
into latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch
circuit, after that they are put on the internal data bus 8 bits at a time.
. Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic, for every 16 bits of data read in, the
selection signal shifts one bit based on the state of the control circuit.
. Data Latch
In case of segment mode, latches the data on the data bus. The latched state of each LC
driver output pin is controlled by the control logic and the data latch control, 240 bits of data are
read in 30 sets of 8 bits.
. Line Latch / Shift Register
In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched on the falling edge of the LP signal, and output to the level shifter block.
In case of common mode, shifts data from the data input pin on the falling edge of the LP
signal.
. Level Shifter
The logic voltage signal is level-shifted to the LC driver voltage level, and output to the driver
block.
. 4-level Driver
Driver the LC driver output pins from the line latch/shift register data, selecting one of 4 levels
(V0, V12, V43, V5) based on the S/C, FR and DISPOFFB signals.
. Control logic
Controls the operation of each block. In case of segment mode, when a LP signal has been
input, all blocks are reset and the control logic waits for the selection signal output from the
active control block. Once the selection signal has been output, operation of the data latch and
data transmission are controlled, 240 bits of data are read in, and the chip is deselected. In
case of common mode, controls the direction of data shift.
10
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
PIN FUNCTION
Segment mode
Symbol
Function
VDD
Logic system power supply pin connects to +2.4 to +5.5V
VSS
Ground pin connects to 0 V
V0R, V0L
V12R , V12L
V43R , V43L
V5R , V5L
DI0 – DI7
XCK
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS ≤ V5 < V43 < V12 < V0.
. To further reduce the difference between the output waveforms of LC driver
output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43, 5)
Input pin for display data
. In 4-bit parallel input mode, input data into the 4 pins DI0 – DI3.
Connect DI4 – DI7 to VSS or VDD.
. In 8-bit parallel input mode, input data into the 8 pins DI0 – DI7.
Clock input pin for taking display data
. Data is read on the falling edge of the clock pulse.
LP
Latch pulse input pin for display data
. Data is latched on the falling edge of the clock pulse.
L/R
Direction selection pin for reading display data
. When set to VSS level “L”, data is read sequentially from Y240 to Y1.
. When set to VDD level H”, data is read sequentially from Y1 to Y240.
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins (Y1 - Y240) are set to level
V5.
DISPOFFB . While set to “L”, the contents of the line latch are reset, but read the display
data in the data latch regardless of condition of DISPOFFB.
When the DISPOFFB function is canceled, the driver outputs deselect level
(V12 or V43), then outputs the contents of the data latch on the next.
Falling edge of the LP. That time, if DISPOFFB removal time can not keep regulation what is
shown AC characteristics (page 21), can not output the reading data correctly.
11
240 SEG / COM DRIVER FOR STN LCD
S6B0796
FR
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. Normally, inputs a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the line
latch output signal and the FR signal.
Table of truth values is shown in table 4.
MD
Mode selection pin
. When set to VSS level “L”, 8-bit parallel input mode is set.
. When set to VDD level “H”, 4-bit parallel input mode is set.
. The relationship between the display data and driver output pins is shown
in table 5.
S/C
Segment mode/common mode selection pin
. When set to VDD level ‘H”, segment mode is set.
EIO1
EIO2
Input / output pin for chip selection
. When L/R input is at VSS level ‘L”, EIO1 is set for output, and EIO2 is set for
input.
. When L/R input is at VDD level ‘H”, EIO1 is set for input, and EIO2 is set for
output.
. During output. set to “H” while LP*XCLKB is ‘H” and after 240-bits of data
have been read, set to “L” for one cycle (from falling edge to falling edge of
XCK), after which it returns to “H”.
. During input, after the LP signal is input, the chip is selected while EI is set
to “L”. After 240-bits of data have been read, the chip is deselected.
Y1 – Y240
12
PRELIMINARY SPEC. VER. 1.0
LC driver output pins
. Corresponding directly to each bit of the data latch, one level(V0, V12, V43,
or V5) is selected and output.
Table of truth values is shown in table 4.
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
Common Mode
Symbol
Function
VDD
Logic system power supply pin connects to +2.4 to +5.5V
VSS
Ground pin connects to 0 V
V0R, V0L
V12R , V12L
V43R , V43L
V5R , V5L
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS<V43<V12<V0.
. To further reduce the difference between the output waveforms of LC driver
output pins Y1 and Y240, externally connect ViR and ViL(i=0, 12, 43, 5)
EIO1
Bidirectional shift register shift data input/output pin
. Output pin when L/R is at VSS level “L”, input pin when L/R is at VDD level
“H”.
. When EIO1 is used as input pin, it will be pull-down.
. When EIO1 is used as output pin, it won’t be pull-down.
EIO2
Bidirectional shift register shift data input/output pin
. Input pin when L/R is at VSS level “L”, output pin when L/R is at VDD level
“H”.
. When EIO2 is used as input pin, it will be pull-down.
. When EIO2 is used as output pin, it won’t be pull-down.
LP
Bidirectional shift register shift clock pulse input pin
. Data is shifted on the falling edge of the clock pulse.
L/R
Bidirectional shift register shift direction selection pin
. Data is shifted from Y240 to Y1 when set to VSS to level “L”, and data is
shifted from Y1 to Y240 when set to VDD level “H”.
13
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins(Y1-Y240) are set to level
V5.
DISPOFFB
. While set to “L”, the contents of the shift resister are reset not reading data.
When the DISPOFFB function is canceled, the driver outputs deselect
Level(V12 or V43), and the shift data is reading on the falling edge of the LP.
That time, if DISPOFFB removal time can not keep regulation what is
shown AC characteristics (page 26), the shift data is not reading correctly.
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
FR
. Normally, input a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the shift
register output signal and the FR signal.
Table of truth values is shown in table 4.
Mode selection pin
MD
. When set to VSS level “L”, Single mode operation is selected, when set to
VDD level “H”, Dual mode operation is selected.
Dual Mode data input pin
. According to the data shift direction of the data shift register, data can be
DI7
input starting from the 121st bit.
When the chip is used as Dual mode, DI7 will be pull-down.
When the chip is used as Single mode, DI7 won’t be pull-down.
Segment mode/common mode selection pin
S/C
. When set to VSS level ‘L”, common mode is set.
Not used
DI0 – DI6
. Connect DI0 – DI6 to VSS or VDD. Avoiding floating.
Not used
XCK
. XCK is pull-down in common mode, so connect to VSS or open.
LC driver output pins
Y1 – Y240 . Corresponding directly to each bit of the shift register, one level(V0, V12,
V43, or V5) is selected and output. Table of truth values is shown in table 4.
14
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
FUNCTIONAL OPERATIONS
TRUTH TABLE (Table 4)
Segment Mode
FR
Latch data
DISPOFFB
Driver output voltage level (Y1 – Y240)
L
L
H
V43
L
H
H
V5
H
L
H
V12
H
H
H
V0
x
x
L
V5
Here, VSS≤V5<V43<V12<V0, H : VDD (+2.4V to +5.5V), L : VSS(0V), x : Don’t care
Common Mode
FR
Latch data
DISPOFFB
Driver output voltage level (Y1 – Y240)
L
L
H
V43
L
H
H
V0
H
L
H
V12
H
H
H
V5
x
x
L
V5
Here, VSS≤V5<V43<V12<V0, H : VDD (+2.4V to +5.5V), L : VSS(0V), x : Don’t care
NOTE : There are two kinds of power supply (logic level voltage, LC drive voltage) for LCD
driver, please supply regular voltage which assigned by specification for each power
pin. That time ‘Don’t care” should be fixed to ‘H” or “L “, avoiding floating.
15
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
RELATIONSHIP BETWEEN THE DISPLAY DATA AND DRIVER OUTPUT PINS (Table 5)
Segment Mode
(a) 4-bit Parallel Mode
MD
H
H
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Figure of clock
Data
Input
1st
2nd
3rd
..
58th
59th
60th
DI0
Y237
Y233
Y229
..
Y9
Y5
Y1
DI1
Y238
Y234
Y230
..
Y10
Y6
Y2
DI2
Y239
Y235
Y231
..
Y11
Y7
Y3
DI3
Y240
Y236
Y232
..
Y12
Y8
Y4
DI0
Y4
Y8
Y12
..
Y232
Y236
Y240
DI1
Y3
Y7
Y11
..
Y231
Y235
Y239
DI2
Y2
Y6
Y10
..
Y230
Y234
Y238
DI3
Y1
Y5
Y9
..
Y229
Y233
Y237
(a) 8-bit Parallel Mode
MD
L
L
16
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Figure of clock
Data
Input
1st
2nd
3rd
..
28th
29th
30th
DI0
Y233
Y225
Y217
..
Y17
Y9
Y1
DI1
Y234
Y226
Y218
..
Y18
Y10
Y2
DI2
Y235
Y227
Y219
..
Y19
Y11
Y3
DI3
Y236
Y228
Y220
..
Y20
Y12
Y4
DI4
Y237
Y229
Y221
..
Y21
Y13
Y5
DI5
Y238
Y230
Y222
..
Y22
Y14
Y6
DI6
Y239
Y231
Y223
..
Y23
Y15
Y7
DI7
Y240
Y232
Y224
..
Y24
Y16
Y8
DI0
Y8
Y16
Y24
..
Y224
Y232
Y240
DI1
Y7
Y15
Y23
..
Y223
Y231
Y239
DI2
Y6
Y14
Y22
..
Y222
Y230
Y238
DI3
Y5
Y13
Y21
..
Y221
Y229
Y237
DI4
Y4
Y12
Y20
..
Y220
Y228
Y236
DI5
Y3
Y11
Y19
..
Y219
Y227
Y235
DI6
Y2
Y10
Y18
..
Y218
Y226
Y234
DI7
Y1
Y9
Y17
..
Y217
Y225
Y233
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
Table 5 (Continued)
Common Mode
MD
L/R
Data transfer direction
EIO1
EIO2
DI7
L
L(shift to left)
Y240 → Y1
Output
Input
X
(Single)
H(shift to right)
Y1 → Y240
Input
Output
X
Output
Input
Input
Input
Output
Input
H
(Dual)
L(shift to left)
H(shift to right)
Y240 → Y121
Y120 → Y1
Y1 → Y120
Y121 → Y240
Here, L : VSS(0V), H : VDD(+2.4V to +5.5V), X : Don’t care
NOTE: “Don’t care” should be fixed to “H” or “L”, avoid floating.
17
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 6. Absolute Maximum Ratings
Parameter
Supply voltage (1)
Symbol
VDD
Conditions
Applicable pins
Ta=25 °C
Referenced to
VSS(0V)
VDD
Ratings
Unit
-0.3 to +6.5
V
-0.3 to +35
V
V0
V0L, V0R
V12
V12L, V12R
-0.3 to V0+0.3
V
V43
V43L, V43R
-0.3 to V0+0.3
V
V5
V5L, V5R
-0.3 to V0+0.3
V
Input voltage
V1
DI0 –DI7, XCK, LP, L/R,
MD, S/C, EIO1, EIO2,
DISPOFFB
-0.3 to VDD+0.3
V
Storage temperature
TSTG
-45 to 125
°C
Supply voltage (2)
RECOMMENDED OPERATING CONDITIONS
Table 7. Recommended Operating Conditions
Parameter
Symbol
Supply voltage (1)
VDD
Supply voltage (2)
V0
Operating temperature
TOPR
Conditions
Referenced to
VSS(0V)
Applicable pins
Min.
VDD
V0L, V0R
NOTE: Ensure that voltage are set such that VSS≤V5<V43<V12<V0
18
Typ.
Max.
Unit
+2.4
+5.5
V
+15
+32
V
-20
+85
°C
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
DC CHARACTERISTICS
DC CHARACTERISTICS(Table 8)
Segment Mode
Parameter
(VSS=V5=0V, VDD=+2.4 to 5.5V, V0=+15 to +32V, Ta=-20~85°C)
Symbol
Conditions
Applicable pins
Min.
Typ.
VIH
Input voltage
Output voltage
Input leakage
current
DI0 -DI7, XCK, LP, L/R,
FR, MD, S/C,EIO1, EIO2,
DISPOFFB
VIL
VOH
IOH=-0.4mA
VOL
IOL=+0.4mA
ILIH
VI=VDD
ILIL
VI=VSS
|∆VON|
V0=+30V
=0.5V
V0=+20V
EIO1, EIO2
Max.
0.8VDD
Unit
V
0.2VDD
VDD-0.4
V
V
+0.4
V
+10
uA
-10
uA
1.5
2.0
kΩ
2.0
2.5
DI0 -DI7, XCK, LP, L/R,
FR, MD, S/C,EIO1, EIO2,
DISPOFFB
Output
resistance
RON
Stand-by
current
ISTB
*1
VSS
75.0
uA
IDD1
*2
VDD
2.0
mA
IDD2
*3
VDD
12.0
mA
I0
*4
V0
1.5
mA
Consumed
current(1)
(Deselection)
Consumed
current(2)
Y1- Y240
(Selection)
Consumed
current
NOTES: *1 VDD=+5V, V0=+32V, VI=VSS
*2 VDD=+5V, V0=+32V, fXCK=20MHz, No-load, EI=VDD
The input data is turned over by data taking clock (4-bit parallel input mode)
*3 VDD=+5V, V0=+32V, fXCK=20MHz, No-load, EI=VSS
The input data is turned over by data taking clock (4-bit parallel input mode)
*4 VDD=+5V, V0=+32V, fXCK=20MHz, fLP=25.6 kHz, fFR=80Hz, No-load
The input data is turned over by data taking clock (4-bit parallel input mode)
19
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
Table 8 (Continued)
Common Mode
Parameter
(VSS=V5=0V, VDD=+2.4 to 5.5V, V0=+15 to +32V, Ta=-20~85°C)
Symbol
Conditions
Applicable pins
Min.
Typ.
DI0 -DI7, XCK, LP, L/R,
FR, MD, S/C,EIO1, EIO2,
DISPOFFB
VIH
Input voltage
Output voltage
Input leakage
current
VIL
VOH
IOH=-0.4mA
VOL
IOL=+0.4mA
ILIH
VI=VDD
ILIL
VI=VSS
|∆ON|
V0=+30V
=0.5V
V0=+20V
EIO1, EIO2
Max.
0.8VDD
Unit
V
0.2VDD
VDD-0.4
V
V
+0.4
V
DI0 –DI6, LP, L/R, FR,
MD, S/C, DISPOFFB
+10
uA
DI0 -DI7, XCK, LP, L/R,
FR, MD, S/C,EIO1, EIO2,
DISPOFFB
-10
uA
1.5
2.0
kΩ
2.0
2.5
Output
resistance
RON
Input pulldown current
IPD
VI=VDD
XCK, EIO1, EIO2, DI7
100.0
uA
Stand-by
current
ISTB
*1
VSS
75.0
uA
Consumed
current(1)
IDD
*2
VDD
120.0
uA
V0
240.0
uA
Y1 – Y240
Consumed
I0
*2
current(2)
NOTES: *1 VDD=+5V, V0=+32V, VI=VSS
*2 VDD=+5V, V0=+32V, fLP=25.6kHz, fFR=80Hz
case of 1/320 duty operation, No-load
20
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
AC CHARACTERISTICS
SEGMENT MODE AC CHARACTERISTICS(Table 9)
Segment Mode 1
(VSS=V5=0V, VDD=+4.5 to +5.5V, V0=+15 to +32V, Ta=-20~85°C)
Parameter
Symbol Conditions
Min.
Typ.
Shift clock period
*1
TR, TF≤10 ns
Unit
50
ns
TWCKH
15
ns
TWCKL
15
ns
Data setup time
TDS
10
ns
Data hold time
TDH
12
ns
Latch pulse “H” pulse width
TWLPH
15
ns
Shift clock rise to latch pulse rise time
TLD
0
ns
30
ns
Shift clock “H” pulse width
Shift clock “L” pulse width
Shift clock fall to latch pulse fall time
TWCK
Max.
TSL
Latch pulse rise to shift clock rise time
TLS
25
ns
Latch pulse fall to shift clock fall time
TLH
25
ns
Input signal rise time *2
TR
50
ns
Input signal fall time *2
TF
50
ns
Enable setup time
TS
10
ns
DISPOFFB removal time
TSD
100
ns
DISPOFFB “L” pulse width
TWDL
1.2
us
Output delay time (1)
TD
CL=15pF
30
ns
Output delay time (2)
TPD1,
TPD2
CL=15pF
1.2
us
Output delay time (3)
TPD3
CL=15pF
NOTES: *1 Take the cascade connection into consideration.
1.2
us
*2 (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation.
21
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
Table 9 (Continued)
Segment Mode 2
Parameter
(VSS=V5=0V, VDD=+3.0V to +4.5V, V0=+15 to +32V, Ta=-20~85°C)
Symbol Conditions
Min.
Typ.
Shift clock period
*1
TR, TF≤10 ns
Unit
66
ns
TWCKH
23
ns
TWCKL
23
ns
Data setup time
TDS
15
ns
Data hold time
TDH
23
ns
Latch pulse “H” pulse width
TWLPH
30
ns
Shift clock rise to latch pulse rise time
TLD
0
ns
50
ns
Shift clock “H” pulse width
Shift clock “L” pulse width
Shift clock fall to latch pulse fall time
TWCK
Max.
TSL
Latch pulse rise to shift clock rise time
TLS
30
ns
Latch pulse fall to shift clock fall time
TLH
30
ns
Input signal rise time *2
TR
50
ns
Input signal fall time *2
TF
50
ns
Enable setup time
TS
15
ns
DISPOFFB removal time
TSD
100
ns
DISPOFFB “L” pulse width
TWDL
1.2
us
Output delay time (1)
TD
CL=15pF
41
ns
Output delay time (2)
TPD1,
TPD2
CL=15pF
1.2
us
Output delay time (3)
TPD3
CL=15pF
NOTES: *1 Take the cascade connection into consideration.
1.2
us
*2 (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation.
22
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
Table 9 (Continued)
Segment Mode 3
Parameter
(VSS=V5=0V, VDD=+2.4V to +3.0, V0=+15 to +32V, Ta=-20~85°C)
Symbol Conditions
Min.
Typ.
Shift clock period
*1
TR, TF≤10 ns
Unit
82
ns
TWCKH
28
ns
TWCKL
28
ns
Data setup time
TDS
20
ns
Data hold time
TDH
23
ns
Latch pulse “H” pulse width
TWLPH
30
ns
Shift clock rise to latch pulse rise time
TLD
0
ns
65
ns
Shift clock “H” pulse width
Shift clock “L” pulse width
Shift clock fall to latch pulse fall time
TWCK
Max.
TSL
Latch pulse rise to shift clock rise time
TLS
30
ns
Latch pulse fall to shift clock fall time
TLH
30
ns
Input signal rise time *2
TR
50
ns
Input signal fall time *2
TF
50
ns
Enable setup time
TS
15
ns
DISPOFFB removal time
TSD
100
ns
DISPOFFB “L” pulse width
TWDL
1.2
us
Output delay time (1)
TD
CL=15pF
57
ns
Output delay time (2)
TPD1,
TPD2
CL=15pF
1.2
us
Output delay time (3)
TPD3
CL=15pF
NOTES: *1 Take the cascade connection into consideration.
1.2
us
*2 (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation.
23
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
Timing Characteristics of Segment Mode (Figure 3)
TWLPH
LP
TSL
TLS
TLD
TLH
TWCKH
TWCKL
XCK
TR
TF
TDS
TWCK
DI0 - DI7
LAST DATA
DISPOFFB
TDH
TOP DATA
TWDL
TSD
LP
(*)
XCK
1
2
n
TS
EI
TD
EO
(*) n : 4 - bit parallel mode 60
8 - bit parallel mode 30
24
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
Figure 3. (Continued)
FR
TPD1
LP
TPD2
DISPOFFB
TPD3
Y1 ~Y240
[L/R="L"]
25
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
COMMON MODE AC CHARACTERISTICS (Table 10)
Common Mode
(VSS=V5=0V, VDD=+2.4V to +4.5V, V0=+15 to +32V, Ta=-20~85°C)
Parameter
Symbol
Condition
Min.
Shift clock period
TWLP
TR, TF≤20ns
250
ns
Shift clock “H” pulse width
TWLPH
VDD=+5.0V±10%
15
ns
VDD=+2.5V~+4.5V
30
ns
Data setup time
TSU
30
ns
Data hold time
TH
50
ns
Input signal rise time
TR
50
ns
Input signal fall time
TF
50
ns
DISPOFFB removal time
TSD
100
ns
DISPOFFB ‘L” pulse width
TWDL
1.2
us
Output delay time (1)
TDL
CL=15pF
200
ns
Output delay time (2)
TPD1,TPD2
CL=15pF
1.2
us
Output delay time (3)
TPD3
CL=15pF
1.2
us
Timing Characteristics of Common Mode (Figure 4)
TWLP
LP
TR
TWLPH
TSU
TF
TH
EIO2
(DI7)
TDL
EIO1
DISPOFFB
26
TWDL
TSD
Typ.
Max.
Unit
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
Figure 4. (Continued)
FR
TPD1
LP
TPD2
DISPOFFB
TPD3
Y1~ Y240
[L/R="L"]
27
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
PRECAUTION
. PRECAUTION WHEN CONNECTING OR DISCONNECTING THE POWER
This LSI has a high-voltage LC driver, so it may be permanently damaged by a high current
which may flow if a voltage is supplied to the LC driver power supply while the logic system
power supply is floating. The detail is as follows.
. When connecting the power supply, connect the LC drive power after connecting the logic
system power. Furthermore, when disconnecting the power, disconnect the logic system
power after disconnecting the LC driver power.
. We recommend you connecting the serial resistor (50~100Ω) or fuse to the LC drive power
V0 of the system as a current limiter. And set up the suitable of the resistor in consideration of
LC display grade.
And when connecting the logic power supply, the logic condition of this LSI inside is
insecurity. Therefore connect the LC driver power supply after resetting logic condition of this
LSI inside on DISPOFFB function. After that, cancel the DISPOFFB function after the LC
driver power supply has become stable. Furthermore, when disconnecting the power, set the
LC drive output pins to level V5 on DISPOFFB function. After that, disconnect the logic
system power after disconnecting the LC drive power. When connecting the power supply,
show the following recommend sequence.
VDD
VDD
VSS
VDD
DISPOFFB
VSS
V0
V0
VSS
Figure 5.
28
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS
(a) CASE OF L/R = "L"
top data
last data
Y1
Y240
EIO 2
Y1
Y240
EIO 1
EIO 2
EIO 1
L/R
X
C
K
L
P
M
D
F
R
D D
I -I
O O
0
7
Y1
Y240
EIO 2
EIO 1
L/R
X
C
K
XCK
LP
MD
FR
DIO 0
- DIO 7
L
P
M
D
F
R
D D
I -I
O O
0
7
L/R
X
C
K
L
P
M
D
F
R
D D
I -I
O O
0
7
8
VSS
(b) CASE OF L/R = "H"
VDD
8
DIO 0
- DIO 7
FR
MD
LP
XCK
X
C
K
L
P
M
D
F
R
D D
I -I
O O
0
X
C
K
L
P
M
D
F
R
0
7
EIO 1
Y1
EIO 2
Y240
X
C
K
7
EIO 1
EIO 2
Y1
Y240
top data
L
P
M
D
F
R
D D
I -I
O O
0
L/R
L/R
VSS
D D
I -I
O O
7
L/R
EIO 1
Y1
EIO 2
Y240
last data
Figure 6.
29
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT
DRIVERS
FR
LP
XCK
TOP DATA
DI0 -DI 7 n 1 2
device A
LAST DATA
(*)
n12
device B
n12
n12
device C
EI
(device A)
device D
Low
EO
(device A)
EO
(device B)
EO
(device C)
(*) n:4-bit parallel mode 60
8-bit parallel mode 30
Figure 7.
30
n12
S6B0796
PRELIMINARY SPEC. VER. 1.0
240 SEG / COM DRIVER FOR STN LCD
CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS
(a) SINGLE MODE(SHIFTING TOWARD LEFT)
first
last
Y1
Y240
DI
EIO 2
D
I
EIO 1
L
P
7
M
D
D
I
S
P
O
F
F
B
F
R
Y1
Y240
EIO 2
EIO 1
L/R
D
I
L
P
7
M
D
D
I
S
P
O
F
F
B
F
R
Y1
Y240
EIO 2
EIO 1
L/R
D
I
L
P
7
M
D
D
I
S
P
O
F
F
B
F
R
L/R
VSS
(VDD)
LP
VSS
FR
DISPOFFB
VSS
(b) SINGLE MODE(SHIFTING TOWARD RIGHT)
VDD
DISPOFFB
FR
VSS
LP
VSS
(VDD)
D
I
7
DI
EIO 1
Y1
L
P
M
D
F
R
D
I
S
P
O
F
F
B
D
I
L
P
M
D
F
R
7
L/R
EIO 2
Y240
EIO 1
D
I
S
P
O
F
F
B
D
I
7
L/R
EIO 2
Y1
Y240
EIO 1
Y1
L
P
M
D
F
R
D
I
S
P
O
F
F
B
L/R
EIO 2
Y240
last
first
Figure 8.
31
240 SEG / COM DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0796
(c) DUAL MODE(SHIFTING TOWARD LEFT)
first1
last1 first2
Y1
Y240
DI1
EIO 2
D
I
7
EIO 1
L
P
M
D
F
R
D
I
S
P
O
F
F
B
Y240
last2
Y1
Y121 Y120
EIO 2
EIO 1
L/R
D
I
7
L
P
M
D
F
R
D
I
S
P
O
F
F
B
Y1
Y240
EIO 2
EIO 1
L/R
D
I
7
L
P
M
D
F
R
L/R
D
I
S
P
O
F
F
B
VSS
(VDD)
LP
VSS
FR
DISPOFFB
VDD
VSS
DI2
(d) DUAL MODE(SHIFTING TOWARD RIGHT)
DI2
VDD
VDD
DISPOFFB
FR
VSS
LP
VSS
(VDD)
D
I
7
DI1
EIO 1
Y1
L
P
M
D
F
R
D
I
S
P
O
F
F
B
D
I
L
P
M
D
F
R
7
L/R
EIO 2
Y240
EIO 1
Y1
D
I
S
P
O
F
F
B
D
I
7
L/R
EIO 2
Y120
Y121
Y240
EIO 1
Y1
L
P
M
D
F
R
D
I
S
P
O
F
F
B
L/R
EIO 2
Y240
last2
first1
last1 first2
Figure 9.
32