SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V. The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ IEEE 1149.1 (JTAG) Compliant Bus LVDS Signaling Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ±100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 pF typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin LQFP package and BGA package ■ High impedance Bus pins on power off (VCC = 0V) Simplified Functional Diagram 10124201 Connection Diagrams TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 101242 www.national.com SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN December 2006 SCAN92LV090 10124202 Top View Order Number SCAN92LV090VEH See NS Package Number VEH064DB 10124216 Top View Order Number SCAN92LV090SLC See NS Package Number SLC64A www.national.com 2 Pin Name TQFP Pin # BGA Pin # Input/Output Descriptions DO+/RI+ 27, 31, 35, 37, 41, 45, A7, B8, C6, D5, D8, E6, 47, 51, 55 F7, G5, G6 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO−/RI− 26, 30, 34, 36, 40, 44, B5, B6, C7, D6, E5, E8, 46, 50, 54 F6, G8, H7 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, A2, A4, C3, C4, D2, E3, 60, 62 G3, G4, H3 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, A3, B3, C1, C2, D4, E4, 61, 63 F4, G1, H2 O TTL Receiver Output. RE 17 H1 I Receiver Enable TTL Input (Active Low). DE 16 G2 I Driver Enable TTL Input (Active High). GND 4, 5, 9, 14, 25, 56 B1, B4, D3, E1, F2, H5 Power Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 10, 15, 24, 57, 64 A1, A5, F1, F3, H4 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 28, 33, 43, 49, 53 A8, C5, D7, F5, G7 Power Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AVCC 29, 32, 42, 48, 52 A6, B7, C8, H6, H8 Power Analog VCC (must connect to VCC on PC board). These pins connected internally. TRST 39 F8 I Test Reset Input to support IEEE 1149.1 (Active Low) TMS 38 E7 I Test Mode Select Input to support IEEE 1149.1 TCK 1 B2 I Test Clock Input to support IEEE 1149.1 TDI 8 D1 I Test Data Input to support IEEE 1149.1 TDO 11 E2 O Test Data Output to support IEEE 1149.1 3 www.national.com SCAN92LV090 Pinout Description SCAN92LV090 θjc Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 sec.) Absolute Maximum Ratings (Notes 2, 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Enable Input Voltage (DE, RE) Driver Input Voltage (DIN) Receiver Output Voltage (ROUT) Bus Pin Voltage (DO/RI±) 4.0V 260°C Recommended Operating Conditions −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to +3.9V Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature Maximum Input Edge Rate ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25°C LQFP 1.74 W Derate LQFP Package 13.9 mW/°C θja 10.9°C/W +150°C −65°C to +150°C Min 3.0 0.0 −40 (Note 6)(20% to 80%) Data Control Max 3.6 2.4 +85 Units V V °C 1.0 3.0 Δt/ΔV ns/V ns/V 71.7°C/W DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol Parameter Conditions Pin RL = 27Ω, Figure 1 VOD Output Differential Voltage DO+/RI+, DO−/RI− ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS Offset Magnitude Change VOH Driver Output High Voltage RL = 27Ω VOL Driver Output Low Voltage IOSD Output Short Circuit Current VOD = 0V, DE = VCC, Driver outputs (Note 10) shorted together VOH Voltage Output High (Note 11) RL = 27Ω VID = +300 mV Typ Max Units 240 300 460 mV 27 mV 1.1 1.3 1.5 V 5 10 mV 1.4 1.65 V 0.95 IOH = −400 µA 1.1 |36| |65| mA V Inputs Open VCC−0.2 V Inputs Terminated, RL = 27Ω VCC−0.2 V Voltage Output Low IOL = 2.0 mA, VID = −300 mV IOD Receiver Output Dynamic Current (Note 10) VID = 300mV, VOUT = VCC−1.0V VTH Input Threshold High DE = 0V, VCM = 1.5V VTL Input Threshold Low VCMR Receiver Common Mode Range IIN Input Current VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ROUT V VCC−0.2 VOL 0.05 −110 VID = −300mV, VOUT = 1.0V DIN, DE, RE, TCK, TRST, TMS, TDI DIN, DE, RE 4 V mA 110 mA +100 mV −100 mV |VID|/2 DE = 0V, RE = 2.4V, VIN = +2.4V or 0V 0.075 |75| |75| DO+/RI+, DO−/RI− VCC = 0V, VIN = +2.4V or 0V www.national.com Min 2.4 − | VID|/2 V −25 ±1 +25 µA −20 ±1 +20 µA 2.0 VCC V GND 0.8 V −20 ±10 +20 µA −20 ±10 +20 µA −1.5 −0.8 V Parameter Conditions Pin Min Typ Max Units IIH Input High Current VIN = VCC TDI, TMS, TCK, TRST -20 +20 µA IILR Input Low Current VIN = GND, VCC = 3.6v TDI, TMS, TRST -25 -115 µA IIL Input Low Current VIN = GND TCK -20 +20 µA ICCD Power Supply Current No Load, DE = RE = VCC, Drivers Enabled, Receivers DIN = VCC or GND Disabled 50 80 mA Power Supply Current DE = RE = 0V, VID = ±300mV Drivers Disabled, Receivers Enabled 50 80 mA Power Supply Current, DE = 0V; RE = VCC, Drivers and Receivers TRI- DIN = VCC or GND STATE® 50 80 mA Power Supply Current, Drivers and Receivers Enabled 160 210 mA 180 230 mA +20 µA ICCR ICCZ ICC ICCS IOFF VCC DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω Power Supply Current DE = VCC; RE = 0V, (SCAN Test Mode), Drivers DIN = VCC or GND, and Receivers Enabled RL = 27Ω, TAP in any state other than Test-Logic-Reset Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) DO+/RI+, DO−/RI− COUTPUT Capacitance @ Bus Pins DO+/RI+, DO−/RI− 5 pF COUTPUT Capacitance @ ROUT ROUT 7 pF −20 AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol Parameter Conditions Min Typ Max Unit s 1.0 1.8 2.6 ns 1.8 2.6 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS RL = 27Ω, Figure 2, Figure 3 CL = 10 pF tPHLD Differential Prop. Delay High to Low (Note 8) tPLHD Differential Prop. Delay Low to High (Note 8) tSKD1 Differential Skew |tPHLD–tPLHD| (Note 9) tSKD2 Chip to Chip Skew (Note 12) 1.6 ns tSKD3 Channel to Channel Skew (Note 13) 0.25 0.55 ns tTLH Transition Time Low to High 0.5 1.2 ns tTHL Transition Time High to Low 0.5 1.2 ns tPHZ Disable Time High to Z 3 8 ns tPLZ Disable Time Low to Z 3 8 ns tPZH Enable Time Z to High 3 8 ns tPZL Enable Time Z to Low 3 8 ns RL = 27Ω, Figure 4, Figure 5 CL = 10 pF 1.0 120 ps DIFFERENTIAL RECEIVER TIMING REQUIREMENTS 5 www.national.com SCAN92LV090 Symbol SCAN92LV090 Symbol Parameter tPHLD Differential Prop. Delay High to Low (Note 8) tPLHD Differential Prop Delay Low to High (Note 8) tSDK1 Differential Skew |tPHLD–tPLHD| (Note 9) tSDK2 Chip to Chip Skew (Note 12) tSDK3 Channel to Channel skew (Note 13) tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low Conditions Figure 6, Figure 7 CL = 35 pF Min Typ Max Unit s 2.0 2.4 3.9 ns 2.0 2.4 3.9 ns 210 RL = 500Ω, Figure 8, Figure 9 CL = 35 pF ps 1.9 ns 0.35 0.7 ns 1.5 2.5 ns 1.5 2.5 ns 4.5 10 ns 3.5 8 ns 3.5 8 ns 3.5 8 ns SCAN CIRCUITRY TIMING REQUIREMENTS RL = 500Ω, CL = 35 pF fMAX Maximum TCK Clock Frequency 25.0 75.0 MHz tS TDI to TCK, H or L 1.5 ns tH TDI to TCK, H or L 1.5 ns tS TMS to TCK, H or L 2.5 ns tH TMS to TCK, H or L 1.5 ns tW TCK Pulse Width, H or L 10.0 ns tW TRST Pulse Width, L 2.5 ns tREC Recovery Time, TRST to TCK 2.0 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. Note 3: All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V. Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs. Note 8: Propagation delays are guaranteed by design and characterization. Note 9: tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions. Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. Note 11: VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied. Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, common edge. www.national.com 6 General application guidelines and hints may be found in the following application notes: AN-808, AN-1108, AN-977, AN-971, and AN-903. There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible. • Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors. In addition, randomly distributed by-pass capacitors should be used. • Use the termination resistor which best matches the differential impedance of your transmission line. • Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches. • Isolate TTL signals from Bus LVDS signals MEDIA (CONNECTOR or BACKPLANE) SELECTION: • Use controlled impedance media. The backplane and connectors should have a matched differential impedance. MODE SELECTED DE RE H DRIVER MODE H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L TABLE 2. Transmitter Mode INPUTS DE OUTPUTS DIN DO+ DO− H H L L H H H L H 0.8V< DIN <2.0V X X L X Z Z TABLE 3. Receiver Mode INPUTS OUTPU T RE (RI+) – (RI−) L L (< −100 mV) L L H (> +100 mV) H L −100 mV < VID < +100 mV X H X Z X = High or Low logic state L = Low state Z = High impedance state H = High state Test Circuits and Timing Waveforms 10124203 FIGURE 1. Differential Driver DC Test Circuit 10124204 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit 7 www.national.com SCAN92LV090 TABLE 1. Functional Table Applications Information SCAN92LV090 10124205 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms 10124206 FIGURE 4. Driver TRI-STATE Delay Test Circuit 10124207 FIGURE 5. Driver TRI-STATE Delay Waveforms www.national.com 8 SCAN92LV090 10124208 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit 10124214 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms 10124215 FIGURE 8. Receiver TRI-STATE Delay Test Circuit 10124211 FIGURE 9. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations 9 www.national.com SCAN92LV090 10124212 Bi-Directional Half-Duplex Point-to-Point Applications 10124213 Multi-Point Bus Applications www.national.com 10 SCAN92LV090 Instruction Register Scan Chain Definition Description of Boundary-Scan Circuitry The SCAN92LV090 features two unique Scan test modes, each which requires a unique BSDL model depending on the level of test access and fault coverage goals. In the first mode (Mode0), only the TTL Inputs and Outputs of each transceiver are accessible via a 1149.1 compliant protocol. In the second mode (Mode1), both the TTL Inputs and Outputs and the differential LVDS I/Os are included in the Scan chain. All test modes are handled by the ATPG software, and BSDL selection should be invisible to the user. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. 10124210 MSB → LSB (Mode0) Instruction Code Bypass Register Scan Chain Definition Logic 0 Instruction 00000000 EXTEST 10000010 SAMPLE/PRELOAD 10000111 CLAMP 00000110 HIGHZ All Others BYPASS MSB → LSB (Mode1) Instruction Code 10124209 The INSTRUCTION register is an eight-bit register which captures the value 00111101. 10124221 Instruction 10011001 EXTEST 10010010 SAMPLE/PRELOAD 10001111 CLAMP 00000110 HIGHZ All Others BYPASS 10124220 Mode 0 Boundary Scan Register Configuration (Refer to the BSDL for exact register order) Mode 1 Boundary Scan Register Configuration (Refer to the BSDL for exact register order) 11 www.national.com SCAN92LV090 Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead Molded LQFP Package Order Number SCAN92LV090VEH NS Package Number VEH064DB 64-Lead Ball Grid Array Package Order Number SCAN92LV090SLC NS Package Number SLC64A www.national.com 12 SCAN92LV090 Notes 13 www.national.com SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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