SHF-0189 SHF-0189Z Product Description Sirenza Microdevices’ SHF-0189 is a high performance AlGaAs/GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Pb RoHS Compliant & Green Package 0.05 - 6 GHz, 0.5 Watt GaAs HFET Output power at 1dB compression for the SHF-0189 is +27 dBm when biased for Class AB operation at 8V,100mA. The +40 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. The matte tin finish on Sirenza’s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU Product Features Directive 2002/95. This package is also manufactured with green molding • Now available in Lead Free, RoHS compounds that contain no antimony trioxide nor halogenated fire retarCompliant, & Green Packaging dants. • High Linearity Performance at 1.96 GHz +27 dBm P1dB +40 dBm Output IP3 +16.5 dB Gain • High Drain Efficiency • See App Note AN-031 for circuit details Gain, Gmax (dB) Typical Gain Performance (8V,100mA) 35 30 25 Gmax 20 15 10 5 Gain Applications • Analog and Digital Wireless Systems • 3G, Cellular, PCS • Fixed Wireless, Pager Systems 0 -5 0 S ym b o l 1 2 3 4 5 6 Frequency (GHz) 7 8 T e s t C o n d it io n s , 2 5 C V D S = 8 V , ID Q = 1 0 0 m A D e v ic e C h a r a c t e r is t ic s Test F re q u e n c y U n its M in Typ M ax Z S= Z S*, Z L= Z L* 0 .9 0 G H z 1 .9 6 G H z dB - 2 3 .3 2 0 .1 - Z S= Z L= 5 0 O hm s 0 .9 0 G H z 1 .9 6 G H z dB A p p li c a t i o n C i r c u i t 0 .9 0 G H z 1 .9 6 G H z dB m - 1 8 .6 1 6 .7 - A p p li c a t i o n C i r c u i t 0 .9 0 G H z 1 .9 6 G H z dB m - 40 40 - A p p li c a t i o n C i r c u i t 0 .9 0 G H z 1 .9 6 G H z dB m - 2 7 .2 2 7 .5 - 1 .9 6 G H z dB - 3 .2 384 ( u n le s s o t h e r w is e n o t e d ) G m ax S 21 M a x i m u m A v a i la b le G a i n In s e r t i o n G a i n [1 ] [2 ] G a in P o w e r G a in O IP 3 O u t p u t T h i r d O r d e r In t e r c e p t P o i n t P 1dB O u tp u t 1 d B C o m p r e s s i o n P o i n t [2 ] [2 ] N F N o is e F ig u re A p p li c a t i o n C i r c u i t ID S a tu r a te d D r a i n C u r r e n t V m T r a n c o n d u c ta n c e V P P i n c h - O f f V o lt a g e S S g V [1 ] G S G a t e - S o u r c e B r e a k d o w n V o lt a g e B V G D G a t e - D r a i n B r e a k d o w n V o lt a g e T h e rm a l R e s i s ta n c e V O p e r a t i n g V o lt a g e D S ID Q P D IS S O p e r a tin g C u rr e n t P o w e r D i s s i p a ti o n [3 ] [3 ] 294 144 198 252 V - 3 .0 -1 .9 -1 .0 IG S = 1 . 2 m A , d r a i n o p e n V - -1 7 -1 5 IG D = 1 . 2 m A , V V - -2 2 -1 7 C /W - 80 - V - - 8 .0 m A - - 160 W - - 0 .8 V B V R th 204 [1 ] [1 ] , V D S P G S = 0V 2 0 .2 m A D S P , V 1 8 .4 1 4 .7 m S D S = V 1 6 .6 D = V S = - 0 .2 5 V G S D = 2 . 0 V , ID S = 0 . 6 m A S G S = - 5 .0 V ju n c t i o n - t o - le a d d ra in -s o u rc e d ra in -s o u rc e , q u ie s c e n t [3 ] o [1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain TJ<150C at TL=85C. VDS * IDQ<0.8W is recommended for continuous reliable operation. The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-101240 Rev E SHF-0189 0.5 Watt HFET Absolute Maximum Ratings Parameter MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the bias condition should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (°C) TL = Lead Temperature (pin 4) (°C) RTH = Thermal Resistance (°C/W) Symbol Value Unit Drain Current IDS 200 mA Forward Gate Current IGSF 1.2 mA Reverse Gate Current IGSR 1.2 mA Drain-to-Source Voltage VDS +9.0 V Gate-to-Source Voltage VGS <-5 or >0 V RF Input Power PIN 200 mW Operating Lead Temperature TL See Graph °C Storage Temperature Range Tstor -40 to +150 °C Power Dissipation P DISS See Graph W TJ +165 °C Channel Temperature Total Dissipated Power (W) MTTF @ TJ=150C exceeds 1E7 hours Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. Power Derating Curve 1.50 12345678 12345678 12345678 12345678 This area not recommended 12345678 12345678 for continuous reliable operation. 1.25 1.00 0.75 0.50 Operational (Tj<150C) 0.25 ABS MAX (Tj<165C) 0.00 -40 -15 10 35 60 85 Lead Temperature (C) 110 135 160 Typical Performance - Engineering Application Circuits (See App Note AN-031) Freq (MHz) V DS (V) IDQ (mA) P1dB (dBm) OIP3* (dBm) Gain (dB) S11 (dB) S22 (dB) NF (dB) 4.7 900 8 100 27.2 40 18.6 -25 -13 1960 8 100 27.6 40 16.7 -20 -8 3.2 2140 8 100 27.5 40 15.2 -24 -14 3.8 2450 8 100 27.3 40 15.2 -16 -14 3.1 * POUT= +15dBm per tone, 1MHz tone spacing Data above represents typical performance of the application circuits noted in Application Note AN-031. Refer to the application note for additional RF data, PCB layouts, and BOMs for each application circuit. The application note also includes biasing instructions and other key issues to be considered. For the latest application notes please visit our site at www.sirenza.com or call your local sales representative. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-101240 Rev E SHF-0189 0.5 Watt HFET De-embedded S-Parameters (ZS=ZL=50 Ohms, VDS=8V, IDS=100mA, 25° C) -10 -15 -20 -25 -30 -35 -40 -45 -50 Isolation Gmax Gain 0 1 2 3 4 5 6 7 Isolation (dB) Gain, Gmax (dB) Gain & Isolation 35 30 25 20 15 10 5 0 -5 8 Frequency (GHz) S11 vs Frequency S22 vs Frequency 1.0 1.0 6 GHz 2.0 0.5 2.0 0.5 4 GHz 0.2 0.2 5.0 3 GHz 0.0 0.2 0.5 1.0 2.0 5.0 8 GHz 6 GHz 8 GHz 5.0 0.0 inf 0.2 4 GHz 0.5 1.0 2.0 5.0 inf 3 GHz 2 GHz 0.2 2 GHz S22 0.2 5.0 5.0 1 GHz S11 0.5 2.0 0.5 2.0 1 GHz 1.0 1.0 Note: S-parameters are de-embedded to the device leads with ZS=Z L=50Ω. The data represents typical performace of the device. De-embedded s-parameters can be downloaded from our website (www.sirenza.com). DC-IV Curves 0.35 0.3 IDS (A) 0.25 0.2 VGS = -2.0 to 0V, 0.2V steps T=25° C 0.15 0.1 0.05 0 0 1 2 3 4 5 6 7 8 VDS (V) 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-101240 Rev E SHF-0189 0.5 Watt HFET Pin Description Gate 2 Source 3 Drain 4 Source Description RF Input Part Number Reel Size Devices/Reel SHF-0189 7" 1000 SHF-0189Z 7" 1000 Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. RF Output Same as Pin 2 Part Symbolization The part will be symbolized with the “H1” designator and a dot signifying pin 1 on the top surface of the package. Mounting and Thermal Considerations It is very important that adequate heat sinking be provided to minimize the device junction temperature. The following items should be implemented to maximize MTTF and RF performance. 1. Multiple solder-filled vias are required directly below the ground tab (pin 4). [CRITICAL] 2. Incorporate a large ground pad area with multiple platedthrough vias around pin 4 of the device. [CRITICAL] 3. Use two point board seating to lower the thermal resistance between the PCB and mounting plate. Place machine screws as close to the ground tab (pin 4) as possible. [RECOMMENDED] 4. Use 2 ounce copper to improve the PCB’s heat spreading capability. [RECOMMENDED] Package Dimensions 3 .161 .016 .177 .068 .019 .118 1 2 Function 1 4 Pin # Part Number Ordering Information .096 .041 .015 .059 Recommended Mounting Configuration for Optimum RF and Thermal Performance DIMENSIONS ARE IN INCHES H1Z 2 3 1 2 H1 1 1 1 4 3 SHF-0x89 4 2 Plated Thru Holes (0.020" DIA) 2 3 Ground Plane 3 Machine Screws Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-101240 Rev E