SPICE Device Model Si6966EDQ Vishay Siliconix N-Channel 2.5-V (G-S) MOSFET, ESD Protected CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70074 22-Oct-04 www.vishay.com 1 SPICE Device Model Si6966EDQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 0.923 V On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 4.5 V 120 A VGS = 4.5 V, ID = 5.2 A 0.02 VGS = 2.5 V, ID = 4.5 A 0.027 Static Drain-Source On-State Resistancea Forward Transconductancea Schottky Diode Forward Voltagea rDS(on) gfs VSD VDS = 10 V, ID = 5.2 A 19.5 IS = 1.25 A, VGS = 0 V 0.65 IS = 1.25 A, VGS = 0 V, Tj = 125°C 0.57 Ω S V Dynamicb Total Gate Chargeb Qg b Gate-Source Charge b Qgs 13.4 VDS = 15 V, VGS = 4.5 V, ID = 5.2 A 2.1 Gate-Drain Charge Qgd 5.7 Turn-On Delay Timeb td(on) 0.35 Rise Timeb Turn-Off Delay Timeb tr td(off) Fall Timeb tf Source-Drain Reverse Recovery Time trr VDD = 10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 4.5 V, RG = 6 Ω nC 76 131 ns 290 IF = 1.25 A, di/dt = 100 A/µs 210 Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70074 22-Oct-04 SPICE Device Model Si6966EDQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 70074 22-Oct-04 www.vishay.com 3