SM9403BM DVDRAM Servo-amplifier LSI NIPPON PRECISION CIRCUITS INC. OVERVIEW The SM9403BM is a DVDROM and DVDRAM servo preprocessor LSI, designed for double-speed format DVDROM and DVDRAM drives. The SM9403BM is fabricated using a BiCMOS process, and incorporates an analog signal processing circuit that generates signals needed by the digital servo processor, a DPD signal processing circuit (DVDROM), and a CAPA (Complementary Allocated Pit Address) detection circuit (DVDRAM) all in a single chip. It operates from a single 5 V supply, and is available in 36-pin plastic SSOP packages. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ APPLICATIONS ■ ■ Double-speed DVDROM drives Double-speed DVDRAM drives ORDERING INFORMATION D e vice P ackag e SM9403BM 36-pin SSOP 36-pin SSOP (Top View) NC 1 36 DPDG NC 2 35 DPDI FER 3 34 DEFECT FHOLD 4 33 DGND FSUB 5 32 SCLK ISET 6 31 SDATA DPDD 7 30 SENB DPDC 8 29 DVCC DPDB 9 28 CAPSEEK DPDA 10 27 CAPSEL AGND 11 26 CAPIN MMTI 12 25 AVCC CAPAN 13 24 CAPOUT CAPAP 14 23 CAPAREA CAPLFC 15 22 TRP TSUB 16 21 TROFF THOLD 17 20 VREF2 TRE 18 19 VREF4 NPC ■ DPD signal processor Tracking error signal output Focus error signal output Tracking error signal sample-and-hold Focus error signal sample-and-hold CAPA detection function Track count pulse generator Off-track detection 2V and 4V reference voltage generator Serial interface for setting internal parameters Sleep-mode function Single 5 V supply 36-pin plastic SSOP SM9403BM ■ PINOUT NIPPON PRECISION CIRCUITS—1 SM9403BM PACKAGE DIMENSIONS (Unit: mm) 15.20 to 15.40 0 to 8° 0.85 0.51 ± 0.20 45° 10.11 to 10.51 7° 7.40 to 7.60 R0.63 to 0.89 0.51 to 1.01 7° 0.63 ± 0.10 0.23 to 0.32 0.10 to 0.30 2.44 to 2.64 0.80 0.29 to 0.39 BLOCK DIAGRAM AGND AVCC VREF2 VREF4 DEFECT DPDI DPDG FER FHOLD FSUB DVCC DGND Voltage reference S/H LPF * SCLK DPDA DPDB Equalizer Delay Serial interface Phase comparator DPDC DPDD LPF SDATA SENB ISET SWB TSUB LPF S/H SWA Track Pulse Generator * THOLD TRE TRP TROFF * CAPAP CAPAN Analog signal processor CAPSEEK CAPSEL CAPAREA CAPOUT CAPIN MMTI CAPLFC VREF2 S/H control Mono-multiviblator NIPPON PRECISION CIRCUITS—2 SM9403BM PIN DESCRIPTION Number Name I/O 1 1 NC O No connection 2 NC O No connection 3 FER O Focus error signal output 4 FHOLD – Focus error hold capacitor connection 5 FSUB I Focus error signal input 6 ISET I DPD signal equalizer, reference current set resistor connection 7 DPDD I DPD signal input D 8 DPDC I DPD signal input C 9 DPDB I DPD signal input B 10 DPDA I DPD signal input A 11 AG N D – Analog circuit ground 12 MMTI I M o n o - m ultivibrator time-constant set resistor connection 13 C A PA N I ID data signal differential inverting input 14 C A PA P I ID data signal differential non-inverting input 15 CAPLFC – Slice-level detect capacitor connection 16 TSUB I Tracking error signal input 17 THOLD – Tracking error hold capacitor connection 18 TRE O Tracking error signal output 19 VREF4 O 4V reference voltage output 20 VREF2 O 2V reference voltage output 21 TROFF O Off-track detect signal output. LOW when off-track. 22 TRP O Track count pulse output. HIGH-level pulse for land to outer tracking. 23 C A PA R E A O ID interval detect signal output. ID interval detected when HIGH. 24 CAPOUT O Outer offset ID detect signal output. Outer offset ID interval detected when HIGH. 25 AV C C – Analog circuit pow er supply 26 CAPIN O Inner offset ID detect signal output. Inner offset ID interval detected when HIGH. 27 CAPSEL Ipd ID interval signal input. ID interval selected when HIGH. 28 CAPSEEK Ipd Seek operation signal input. Seek operation selected when HIGH. 29 DV C C – Logic circuit pow er supply 30 SENB I Serial interface enable input. Enabled when HIGH. 31 S D ATA I/O 32 SCLK I Serial interface clock input 33 DGND – Logic circuit ground 34 DEFECT Ipd 35 DPDI I DPD signal hold delay set resistor connection 36 DPDG I DPD signal phase difference to voltage converter coefficient set resistor connection Function Serial interface data input/acknowledge output Defect position signal input. Defect position indicated when HIGH. 1. I = input, Ipd = Input with built-in pull-down resistor, I/O = input/output (N-channel open-drain when output), O = output NIPPON PRECISION CIRCUITS—3 SM9403BM SPECIFICATIONS Absolute Maximum Ratings GND = 0 V P arameter Symbol Condition Rating Unit Supply voltage range VCC −0.5 to 7.0 V Input voltage range V IN − 0.5 to V C C + 0.5 V Operating temperature range T opr 0 to 70 °C Storage temperature range T stg −40 to 125 °C Pow er dissipation PD 250 mW Soldering temperature T sld 260 °C Soldering time tsld 10 s Rating Unit Recommended Operating Conditions GND = 0 V P arameter Symbol Condition Specifications supply voltage range VCC 4.75 to 5.25 V Operating supply voltage range VCC 4.5 to 5.5 V Operating temperature range T opr 0 to 70 °C Recommended External Components Pin No. Pin name Component Tolerance 4 FHOLD 1000pF capacitor K (±10%) ISET 47k Ω resistor ±1% 6 0.01µF capacitor Z (+80% to −2 0 % ) 12 MMTI 120k Ω resistor ±1% 15 CAPLFC 0.01µF capacitor Z (+80% to −2 0 % ) 17 THOLD 1000pF capacitor K (±10%) 19 VREF4 0.1µF capacitor Z (+80% to −2 0 % ) 20 VREF2 0.1µF capacitor Z (+80% to −2 0 % ) 35 DPDI 47k Ω resistor ±1% 36 DPDG 33k Ω resistor ±1% NIPPON PRECISION CIRCUITS—4 SM9403BM DC Electrical Characteristics VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Current consumption 1 Symbol Condition Unit min typ max IC C 1 Operating mode – 28 34 IC C 2 Sleep mode 1 – 17 21 IC C 3 Sleep mode 2 – 2.0 2.6 IC C 4 Sleep mode 3 – – 1.0 ∆I C C IC C 1 − IC C 2 9 – – mA C A P S E E K , C A P S E L , D E F E C T, SENB, SDATA, SCLK HIGH-level input voltage V IH 0.8V C C – – V C A P S E E K , C A P S E L , D E F E C T, SENB, SDATA, S C L K L OW -level input voltage V IL – – 0.2V C C V C A P S E E K , C A P S E L , D E F E C T H I G H - l evel input current IIH1 V IN = V C C 50 100 200 µA S E N B , SDATA, SCLK HIGH-level input current IIH2 V IN = V C C – – 3 µA C A P S E E K , C A P S E L , D E F E C T, SENB, SDATA, S C L K L OW -level input current IIL V IN = G N D −3 – – µA V C C − 0.2 – – V C A PA R E A , C A P I N , C A P O U T, T R P, T R O F F HIGH-level output voltage VOH I O H = −0 . 2 m A C A PA R E A , C A P I N , C A P O U T, T R P, T R O F F L O W -level output voltage VOL1 IO L = 0.8mA – – 0.4 V S D ATA L OW -level output voltage VOL2 IO L = 7mA – – 1.0 V 1. 33k Ω resistor connected between DPDG and AG N D 47k Ω resistor connected between DPDI and AG N D 120k Ω resistor connected between MMTI and AG N D 47k Ω resistor connected between ISET and AG N D 1000pF capacitor connected between FHOLD and AG N D 1000pF capacitor connected between T H O L D a n d AG N D 0.1µF capacitor connected between VREF4 and AG N D 0.1µF capacitor connected between VREF2 and AG N D 0.01µF capacitor connected between CAPLFC and AG N D 0.01µF capacitor connected between ISET and AG N D C A PA P, CAPA N , D P DA , D P D B, D P D C, D P D D, FSUB, TSUB connected to VREF2 or other 2V supply. S E N B , SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit. Sleep mode 1: DPD system only in sleep condition. Sleep mode 2: All blocks except reference supply voltage generator in sleep condition. Sleep mode 3: All blocks in sleep condition. NIPPON PRECISION CIRCUITS—5 SM9403BM Focus Sample-and-Hold, Low-pass Filter Characteristics (FSUB → FER) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C, FSUB and FER signals in phase Rating P arameter Condition Unit min typ max FSUB input signal range VREF2 reference −1.25 0 +1.25 V FER output voltage range VREF2 reference −1.25 0 +1.25 V FER output offset voltage VREF2 reference, V IN = V R E F 2 – – ±8.0 mV FER output offset voltage temperature drift VREF2 reference – – ±45 µV/ °C FER output signal slew rate LPF off 1 – – V/µs FER output load regulation IO U T = ±3mA, V IN = V R E F 2 – – ±10 mV FSUB input impedance 100 – – kΩ FER output signal gain −0.17 0 +0.17 dB LPF off (FFE = HIGH) 500 – – LPF on (FFE = LOW ) 115 160 230 FER output signal bandwidth 1 V IN = 1.5Vp-p, −3dB from DC kHz FER output gain peaking 1 DC to −3dB frequency −3 – +0.5 dB Hold time FER output droop characteristic V IN = 200mVp-p, C F H O L D = 1000pF – – 0.025 %/µs S/H acquisition time ∆V IN = 200mV, target value ± 10% – – 1 µs FER output hold error With respect to the previous value – – ±4 mV 1 – – MΩ Pow er-down state FER output impedance 1. C L = 20pF, R L = 500 Ω Tracking Sample-and-Hold, Low-pass Filter Characteristics (TSUB → TRE) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C, TSUB and TRE signals in phase Rating P arameter Condition Unit min typ max TSUB input signal range VREF2 reference −1.25 0 +1.25 V TRE output voltage range VREF2 reference −1.25 0 +1.25 V TRE output offset voltage VREF2 reference, V IN = V R E F 2 – – ±8.0 mV TRE output offset voltage temperature drift VREF2 reference – – ±45 µV/ °C TRE output load regulation IO U T = ±3mA, V IN = V R E F 2 – – ±10 mV TSUB input impedance 100 – – kΩ TRE output signal gain −0.17 0 +0.17 dB TFE = HIGH 24 35 50 TFE = LOW 115 160 230 TRE output signal bandwidth 1 V IN = 1.5Vp-p, −3dB from DC kHz TRE output gain peaking 1 DC to −3dB frequency −3 – +0.5 dB Hold time TRE output droop characteristic V IN = 200mVp-p, C T H O L D = 1000pF – – 0.025 %/µs S/H acquisition time ∆V IN = 200mV, target value ±10% – – 1 µs TRE output hold error With respect to the previous value – – ±4 mV 1 – – MΩ Pow er-down state TRE output impedance 1. C L = 20pF, R L = 500 Ω NIPPON PRECISION CIRCUITS—6 SM9403BM DPD Error Signal Detector Characteristics (DPDA/DPDB/DPDC/DPDD → TRP) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter 1 D P D A/DPDB/DPDC/DPDD input voltage range Condition typ max −0.55 – +1 V 1 – – MΩ – – ±0.17 dB D G 2 = L OW 1.2 1.6 2.3 DG2 = HIGH 1.8 2.2 2.9 D G 2 = L OW 5.5 6.1 6.6 DG2 = HIGH 6.1 6.7 7.2 Peak gain frequency (EQE = HIGH) 3.75 5.0 6.25 −3dB frequency (EQE = LOW ) 11 22 33 fpeak , (A + C) vs. (B + D) – – ±1.5 Time constant 1 D G 2 = L OW 56 84 109 Time constant 2 DG2 = HIGH 17 24 32 – – ±2 VREF2 reference D P D A/DPDB/DPDC/DPDD input impedance Signal gain relative accuracy Unit min Gain relative to DPDA , D P D B, D P D C, DPDD inputs 1MHz setting Equalizer gain dB 5MHz setting Equalizer frequency response Equalizer frequency response relative accuracy A C coupling time circuit −3dB frequency MHz % kHz A C coupling time constant relative accuracy −3dB frequency, (A + C) vs. (B + D) Delay control range See table 4. Phase difference detector minimum time DG1 = DG2 = LOW 2 – – ns Phase difference detector maximum time DG1 = DG2 = HIGH – – 1 µs Phase difference detector minimum repeat time Input pulse interval 120 – – ns Phase difference to voltage conversion coefficient DG1 = DG2 = LOW – See table 5. typ ± 20% mV/ns – See table 8. ±1 dB Phase difference to voltage conversion coefficient change accuracy See table 4. % ns Phase difference output offset voltage VREF2 reference – – ±0.1 V Phase difference output offset voltage temperature drift VREF2 reference – – ±570 µV/°C – – 1 µs DEFECT signal response time D P D e n a ble response time D P E fl a g – – 2 µs Abnor mal waveform TRP droop characteristic V O U T = V R E F 2 ± 200mV, VREF2 reference – – 0.1 %/µs TRP output voltage range VREF2 reference −1.25 0 +1.25 V TRP output signal frequency response −3dB frequency 500 – – kHz 1. The tracking error signal TRE is positive with respect to VREF2 if the (DPDA + DPDC) signal phase difference is leading. The detected phase difference is the difference between the point when one internal comparator output changes (from CMA and CMB both HIGH or both LOW) until the second output changes before the first changes again. The phase difference is conver ted to a voltage and sampled for output. Other signals are held constant in the output stage when a phase difference is detected. NIPPON PRECISION CIRCUITS—7 SM9403BM Header Position Detector Characteristics (CAPAP/N → CAPAREA, CAPIN, CAPOUT) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Condition Unit min typ max 1 – 3 V 13 – – MHz – See table 9. typ ± 15% V typ − 5 % See table 10. typ + 45% µs M o n o - m ultivibrator time constant switching accuracy – – ±5 % M o n o - m ultivibrator time-constant block interval accuracy – – ±2.5 % – – 15 ns C A PAP/N input voltage range Analog signal processor frequency response V IN = V R E F 2 ± 0.5V, −3dB from DC Analog signal quantization slice level M o n o - m ultivibrator time constant C A P I N , C A P O U T, CAPAREA output rise time and fall time C L = 20pF Sample-and-Hold Control Signal Generator Characteristics VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter FER, TRE output response time 1 Condition Unit min typ max M o n o - m ultivibra t o r / C A P S E L / C A P S E E K → FSHCNT/TSHCNT – – 100 ns Serial interface (HRE, FHE, THE, HAE) → FSHCNT/TSHCNT – – 2 µs 1. F S H C N T a n d TSHCNT are the focus and tracking sample-and-hold internal control signals, respectively. Tracking Error Signal Switching Characteristics (SWA, SWB) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Switching response time Condition Serial interface timing Unit min typ max – – 1 µs NIPPON PRECISION CIRCUITS—8 SM9403BM Track Count Pulse Generator Characteristics (TSUB → TRP, TROFF) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Condition Unit min typ max TSUB input signal range VREF2 reference −1.25 – +1.25 V TSUB signal limiter voltage level VREF2 reference ±1.0 – – V TSUB signal amplifier gain f = 5kHz 5.83 6.0 6.17 dB typ − 1 5 % See table 15 typ + 15% mV typ − 1 0 % See table 16 typ + 10% mV Quantization level offset set value TRP output comparator hysteresis 1 TRP output comparator hysteresis response time Minimum hysteresis, target value ± 10% – – 600 ns TRP output comparator hysteresis switching response time Minimum ↔ maximum hysteresis value – – 2 µs typ − 1 0 % See table 17 typ + 10% mV – – 5 µs T R OFF output comparator window T R OFF output comparator window switching response time Minimum ↔ maximum window value 1. TRP has the same polarity as TRE (i.e. TRP is HIGH when TRE > VREF2). T R OFF is HIGH when the input signal is inside the window , and LOW when outside the window . Reference Voltage Generator Characteristics (VREF2, VREF4) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Condition Unit min typ max 3.84 4.0 4.16 V 1.92 2.0 2.08 V – – ±400 µV/°C – – ±200 µV/°C – – ±6 mV – – ±3 mV IO U T = 0 to 8mA – – −20 mV IO U T = 0 to ±5mA – – ±10 mV V C C = 5V, IO U T = 0 – – ±20 mV Relative output voltage temperature drift V C C = 5V, T a = 0 to 70°C , IO U T = 0 – – ±10 µV/°C Relative output-voltage supply-voltage dependency V C C = 5V ± 5%, T a = 25°C , IO U T = 0 – – ±1 mV V R E F 4 p ow er-down output impedance 13 – – kΩ V R E F 2 p ow er-down output impedance 1 – – MΩ VREF4 output voltage V C C = 5V, T a = 25°C , IO U T = 0 VREF2 output voltage VREF4 output voltage temperature drift VREF2 output voltage temperature drift V C C = 5V, T a = 0 to 70°C , IO U T = 0 VREF4 output voltage supply voltage dependency VREF2 output voltage supply voltage dependency VREF4 output voltage load regulation VREF2 output voltage load regulation Relative output voltage accuracy 1 V C C = 5V ± 5%, T a = 25°C , IO U T = 0 V C C = 5V, T a = 25°C 1. D e fi ned as (VREF2 − (VREF4 ÷ 2)). NIPPON PRECISION CIRCUITS—9 SM9403BM Serial Interface Characteristics (SCLK, SDATA, SENB) VCC = 5V ± 5%, GND = 0V, Ta = 0 to 70°C Rating P arameter Symbol Condition Unit min typ max SCLK pulse cycle tc y S C K 100 – – ns SCLK HIGH-level pulsewidth tw h S C K 40 – – ns S C L K L OW -level pulsewidth tw l S C K 40 – – ns SENB setup time ts S E N 20 – – ns SENB hold time th S E N 40 – – ns S D ATA setup time ts S DA 15 – – ns S D ATA hold time th S D A 15 – – ns time 1 ts AC K 0 – 20 ns th AC K – – 50 ns ti n S E N 100 – – ns A CK setup A CK hold time 1 SENB inter val 1. A CK is the acknowledge output (n-channel open-drain). LOW -level output when the data received is valid. S D ATA load capacitance is 15pF. tinSEN SENB tsSEN twhSCK twlCLK thSEN tcySCK SCLOCK thACK tsSDA thSDA SDATA Controller SDATA Port bit 0 LSB tsACK bit 1 bit 15 MSB ACK High Impedance NIPPON PRECISION CIRCUITS—10 SM9403BM FUNCTIONAL DESCRIPTION Serial Interface The SM9403BM uses a serial interface comprising 5 ports to control and set all functions. The address and bit configuration of each port is shown in table 1 Table 1. Port address and bit configuration1 Bit nu m b e r 15 14 13 12 11 10 9 8 7 6 5 Data 4 3 2 1 0 A d dress MSB LSB DPE HAE FFE TFE SWB SWA SL2 SL1 × LOW LOW LOW HIGH LOW × × OF3 OF2 OF1 WD2 WD1 HS3 HS2 HS1 × LOW LOW LOW HIGH HIGH × × THE FHE HRE MM2 MM1 LS3 LS2 LS1 × LOW LOW HIGH LOW LOW × × EQE CG3 CG2 CG1 DL4 DL3 DL2 DL1 × LOW LOW HIGH LOW HIGH × × TS3 TS2 TS1 – – – DG2 DG1 × LOW LOW HIGH HIGH LOW × × 1. × = don’t care, – = unassigned Serial data is input on SDATA with the LSB first, in sync with the falling edge of the SCLK clock. After the 16th SCLK falling edge and 16 bits of valid data has been input, the SDATA n-channel open-drain output goes LOW as an acknowledge signal. If the number of SCLK cycles which occur when SENB (serial interface enable) is HIGH is less than 16, the received data is ignored and the internal port is not updated. If the number of SCLK cycles is greater than 16, the data is still considered value up to the 16th SCLK falling edge, the data is latched into the internal port, and the acknowledge signal is output. The acknowledge signal is held until SENB goes LOW again. Focus Sample-and-Hold/Low-pass Filter (FSUB → FER) This stage, the signal which is generated from the header position detector signal samples and holds the focus error signal. The output then passes through a low-pass filter. This low-pass filter can be turned ON or OFF using the serial interface control bit FFE. Table 2. Focus low-pass filter ON/OFF control FFE L o w-pass filter 1 LOW ON HIGH OFF 1. Default is ON Tracking Sample-and-Hold/Low-pass Filter (TSUB → TRE) This stage, the signal which is generated from the header position detector signal samples and holds the tracking error signal. The output then passes through a low-pass filter. This low-pass filter cutoff frequency can be switched using the serial interface control bit TFE. Table 3. Tracking low-pass filter cutoff frequency TFE L o w-pass filter 1 LOW fC = 160kHz HIGH fC = 35kHz 1. Default is 160kHz NIPPON PRECISION CIRCUITS—11 SM9403BM DPD Error Signal Detector (DPDA/DPDB/DPDC/DPDD → TRP) This stage compares the DPD signals, passes the comparator output through a low-pass filter to obtain the DPD tracking error signal. The phase comparator incorporates a detector function which prevents abnormal waveform signals getting to the output by holding the output constant. The DPD signals are first added, (DPDA + DPDC) and (DPDB + DPDD), then passed to an equalizer. A relative time delay is added for offset correction. The signals are then converted to a pulse waveform by comparators with hysteresis characteristics. In addition, serial interface control bit DPE and input DEFECT can be used to force the tracking error signal to the reference voltage VREF2. These controls can be used when powering up a system or to prevent output saturation from occurring during periods when the input signal is unstable. The phase comparator then compares the phase of the pulse waveforms to obtain a time signal equivalent to the tracking error. The time signal is then converted to a voltage. The converted voltage is passed to the output stage, undergoes sampling timing compensation before being integrated to generate the tracking error signal output. The relative time delay setting and time-to-voltage conversion coefficient can be controlled using serial interface control bits. Also, the equalizer used to compensate for the previous stage can be turned ON or OFF using serial interface control. NIPPON PRECISION CIRCUITS—12 SM9403BM Table 4. DPD delay time settings Table 4. DPD delay time settings (Continued) DPD delay (ns) 1 DG2 LOW LOW DG1 DL4 DL3 DL2 DL1 DPD delay (ns) 1 DG2 min typ max DG1 DL4 DL3 DL2 DL1 min typ max LOW LOW LOW LOW 0 0 0 LOW LOW LOW LOW 0 0 0 LOW LOW LOW HIGH −2.2 −3.0 −3.3 LOW LOW LOW HIGH −7.0 −8.5 −13 LOW LOW HIGH LOW −4.2 −5.6 −6.4 LOW LOW HIGH LOW −15 −17 −24 LOW LOW HIGH HIGH −6.0 −8.0 −9.5 LOW LOW HIGH HIGH −22 −27 −36 LOW HIGH LOW LOW −7.5 −11 −13 LOW HIGH LOW LOW −32 −37 −50 LOW HIGH LOW HIGH −10 −14 −16 LOW HIGH LOW HIGH −43 −48 −65 LOW HIGH HIGH LOW −12 −17 −20 LOW HIGH HIGH LOW −55 −62 −83 LOW HIGH HIGH HIGH −14 −20 −24 LOW HIGH HIGH HIGH −70 −78 −108 LOW HIGH LOW HIGH LOW LOW LOW +17 +24 +29 HIGH LOW LOW LOW +90 +100 +136 HIGH LOW LOW HIGH +14 +20 +23 HIGH LOW LOW HIGH +70 +78 +102 HIGH LOW HIGH LOW +12 +17 +19 HIGH LOW HIGH LOW +55 +61 +76 HIGH LOW HIGH HIGH +10 +13 +15 HIGH LOW HIGH HIGH +42 +47 +60 HIGH HIGH LOW LOW +7.5 +11 +13 HIGH HIGH LOW LOW +31 +36 +45 HIGH HIGH LOW HIGH +5.6 +7.7 +9.0 HIGH HIGH LOW HIGH +22 +26 +34 HIGH HIGH HIGH LOW +3.7 +5.5 +6.2 HIGH HIGH HIGH LOW +14 +17 +23 HIGH HIGH HIGH HIGH +2.0 +3.0 +3.4 HIGH HIGH HIGH HIGH +7.2 +8.2 +12 LOW LOW LOW LOW 0 0 0 LOW LOW LOW LOW 0 0 0 LOW LOW LOW HIGH −3.8 −4.5 −6.0 LOW LOW LOW HIGH −9.5 −11 −17 LOW LOW HIGH LOW −7.0 −8.5 −11 LOW LOW HIGH LOW −19 −22 −32 LOW LOW HIGH HIGH −11 −13 −17 LOW LOW HIGH HIGH −30 −35 −49 LOW HIGH LOW LOW −16 −18 −24 LOW HIGH LOW LOW −42 −48 −74 LOW HIGH LOW HIGH −20 −23 −32 LOW HIGH LOW HIGH −60 −67 −105 LOW HIGH HIGH LOW −26 −30 −42 LOW HIGH HIGH LOW −80 −90 −150 LOW HIGH HIGH HIGH −34 −38 −55 LOW H I G H H I G H H I G H −110 −122 −205 HIGH HIGH HIGH HIGH LOW LOW LOW +44 +49 +74 HIGH LOW LOW LOW +124 +167 +210 HIGH LOW LOW HIGH +33 +37 +52 HIGH LOW LOW HIGH +108 +120 +194 HIGH LOW HIGH LOW +25 +29 +38 HIGH LOW HIGH LOW +80 +88 +130 HIGH LOW HIGH HIGH +20 +22 +29 HIGH LOW HIGH HIGH +58 +65 +90 HIGH HIGH LOW LOW +15 +17 +22 HIGH HIGH LOW LOW +42 +47 +64 HIGH HIGH LOW HIGH +10 +12 +17 HIGH HIGH LOW HIGH +29 +33 +45 HIGH HIGH HIGH LOW +7.0 +7.9 +11 HIGH HIGH HIGH LOW +18 +21 +31 HIGH HIGH HIGH HIGH +3.6 +4.3 +5.6 HIGH HIGH HIGH HIGH +9.0 +10 +16 1. Default is 0 ns (DL4 = DL3 = DL2 = DL1 = LOW ) The DPD delay is positive when (A+C) leads (B+D). NIPPON PRECISION CIRCUITS—13 SM9403BM Table 5. Phase difference to voltage converter coefficient CG3 CG2 CG1 C o e f fi cient (mV/ns) 1 LOW LOW LOW 5.38 LOW LOW HIGH 7.58 LOW HIGH LOW 10.7 LOW HIGH HIGH 15.2 HIGH LOW LOW 21.4 HIGH LOW HIGH 30.3 HIGH HIGH LOW 42.7 HIGH HIGH HIGH 60.6 1. Default is 15.2 mV/ns Table 6. Equalizer control EQE Equalizer 1 LOW OFF HIGH ON 1. Default is OFF Table 7. DPD output control DPE DEFECT DPD output 1 LOW × Forced to V R E F 2 × HIGH Forced to V R E F 2 HIGH LOW Active 1. Default is VREF2 (DPE = LOW ) Table 8. DPD delay time coefficient, phase difference to voltage converter coefficient, AC coupling time constant DG2 DG1 Phase to voltag e coefficient (relative to values in table 5) 1 LOW LOW ×1 LOW HIGH × 1/2 HIGH LOW × 1/4 HIGH HIGH × 1/8 D P D - AC coupling time constant circuit −3dB frequency Selected media 8-times CD, DV D - R A M 100 kHz 4-times CD 2-times CD 25 kHz 1-times CD 1. Default is DG2 = DG1 = LOW NIPPON PRECISION CIRCUITS—14 SM9403BM Header Position Detector (CAPAP/N → CAPAREA, CAPIN, CAPOUT) This stage converts a high-speed push-pull signal (CAPAP/CAPAN) to single-ended signals, passes the outputs through low-pass filters to form quantized logic levels which are used as reference signals. These reference signals are level shifted to form plus and minus signals for use by comparators. The amount of level shift can be controlled by serial interface control bits. tinuous signals. This creates inner shifted header CAPIN and an outer shifted header CAPOUT output signals. After quantization logic conversion, retriggerable mono-multivibrators convert the pulse strings to con- In addition, the single-ended signal is also passed through a high-pass filter, which similarly converts to quantized logic signals. Retriggerable mono-multivibrators then convert the pulse strings to continuous signals to create a header area CAPAREA signal. The mono-multivibrator time constants are controlled by serial interface control bits. Table 9. Slice level shift voltages Table 11. CAPOUT/CAPIN/CAPAREA logic LS3 LS2 LS1 L evel shift (mV) 1 LOW LOW LOW ±25 LOW LOW HIGH ±50 LOW HIGH LOW ±75 LOW HIGH HIGH ±100 HIGH LOW LOW ±125 HIGH LOW HIGH ±150 HIGH HIGH LOW ±200 HIGH HIGH HIGH ±250 C A PA R E A HAE1 CAPOUT CAPIN LOW LOW Header signal output Header signal output LOW HIGH LOW LOW HIGH LOW Header signal output Header signal output HIGH HIGH Header signal output Header signal output 1. Default is LOW 1. Default is ±25 mV Table 10. Mono-multivibrator time constants MM2 MM1 CAPOUT/CAPIN output (µs) 1 C A PAREA (µs) 1 LOW LOW 4 8+α LOW HIGH 8 16 + α HIGH LOW 12 24 + α HIGH HIGH 16 32 + α 1. Default is 4 µs and (8 + α), where α ≈ 6 × ln(2V L S /V H ), V H = input signal amplitude, V L S = slice level absolute value shown in table 9. NIPPON PRECISION CIRCUITS—15 SM9403BM Sample-and-Hold Control Signal Generator This stage takes the OR-logic of the CAPIN and CAPOUT signals, generated by the header position detector, the CAPSEL and CAPSEEK input signals, and the serial interface control bit HRE and uses them to create a sample-and-hold circuit control signal SHCNT. The SHCNT is then used in conjunction with serial interface select bits FHE and THE to form the focus sample-and-hold (FSHCNT) and tracking sampleand-hold (TSHCNT) signals. Table 12. Sample-and-hold logic CAPIN CAPOUT CAPSEL CAPSEEK HRE1 SHCNT HIGH × × LOW HIGH HIGH × HIGH × LOW HIGH HIGH LOW LOW × LOW × LOW HIGH × × LOW LOW LOW × HIGH × LOW LOW LOW × × HIGH HIGH × HIGH × × LOW HIGH × LOW 1. Default is LOW × = don’t care. Table 13. Sample-and-hold signal control logic FHE1 THE1 FSHCNT2 TSHCNT2 LOW × LOW × × LOW × LOW HIGH × SHCNT × × HIGH × SHCNT 1. Default is LOW 2. FSHCNT is the focus sample-and-hold control signal, and T S H C N T i s the tracking sample-and-hold control signal. × = don’t care. Tracking Error Signal Switching (SWA, SWB) This stage performs tracking error signal switching during DVDRAM write/read and DVDROM and CD playback. Switching is controlled by serial interface control bits. Table 14. Tracking error signal select S WA SWB Tracking error signal select 1 LOW LOW S/H HIGH HIGH DPD 1. Default is S/H NIPPON PRECISION CIRCUITS—16 SM9403BM Track Count Pulse Generator (TSUB → TRP, TROFF) This stage filters the tracking error signal through a 6th-order Butterworth low-pass filter which effectively filters off header signal leakage effects. An offset voltage is added and the signal passes through a comparator with hysteresis to generate a track count pulse signal output on TRP. Simultaneously, the window comparator corresponding to the tracking error signal is output as the off-track signal on TROFF (LOW for off-track). Table 16. TRP comparator hysteresis HS3 HS2 HS1 Hysteresis (mV) 1 LOW LOW LOW ±100 LOW LOW HIGH ±200 LOW HIGH LOW ±300 LOW HIGH HIGH ±400 The offset voltage, hysteresis level and window width are controlled by serial interface bits. HIGH LOW LOW ±500 HIGH LOW HIGH ≥ 500 Table 15. Offset voltage setting HIGH HIGH LOW ≥ 500 HIGH HIGH HIGH ≥ 500 OF3 OF2 OF1 Offset voltag e (mV) 1 LOW LOW LOW 0 LOW LOW HIGH −200 LOW HIGH LOW −400 LOW HIGH HIGH −600 HIGH LOW LOW +800 HIGH LOW HIGH +600 HIGH HIGH LOW +400 HIGH HIGH HIGH +200 1. Default is ±100 mV Table 17. TROFF comparator window WD2 WD1 Comparator w i n d ow (mV) 1 LOW LOW ±125 LOW HIGH ±250 HIGH LOW ±375 HIGH HIGH ±475 1. Default is ±125 mV 1. Default is 0 mV Sleep Mode The SM9403BM features 3 sleep modes which can be used when the device is not operating to signifi- cantly reduce current consumption. The sleep modes are controlled by serial interface bits. Table 18. Sleep mode settings SL2 SL1 Mode description 1 LOW LOW Sleep mode OFF (nor mal operation) LOW HIGH DPD in sleep condition HIGH LOW All except reference voltage supply in sleep condition HIGH HIGH All blocks in sleep condition 1. Default is OFF (SL2 = SL1 = LOW ) Preset Function When power is applied or in sleep modes 2 and 3, all serial interface flags are reset to their default values with the exception of the sleep mode flags SL2 and SL1 (see the section “Serial Interface”). However, when writing data to SL2 and SL1 to cancel sleep mode, other flags in the same data word have precedence when writing to the port. NIPPON PRECISION CIRCUITS—17 SM9403BM NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9813AE 1999.09 NIPPON PRECISION CIRCUITS—18