TI SN65HVD1176DR

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SLLS563C − JULY 2003 − REVISED APRIL 2005
FEATURES
D Optimized for PROFIBUS Networks
APPLICATIONS
D Process Automation
− Meets the Requirements of EN 50170
− Signaling Rates Up to 40 Mbps
− Differential Output Exceeds 2.1 V
(54 Ω Load)
− Low Bus Capacitance: 10 pF (Max)
−
−
−
Chemical Production
Brewing and Distillation
Paper Mills
D Factory Automation
D
D
D
D
D
Meets the Requirements of TIA/EIA-485-A
ESD Protection Exceeds ±10 kV HBM
Failsafe Receiver for Bus Open, Short, Idle
Up to 160 Transceivers on a Bus
D
D
D
D
Common-Mode Rejection Up to 50 MHz
Short-Circuit Current Limit
Hot Swap Capable
Thermal Shutdown Protection
−
−
−
Automobile Production
Rolling, Pressing, Stamping Machines
Networked Sensors
D General RS-485 Networks
Low Skew During Output Transitions and
Driver Enabling / Disabling
−
−
−
Motor/Motion Control
HVAC and Building Automation Networks
Networked Security Stations
DESCRIPTION
These devices are half-duplex differential transceivers, with characteristics optimized for use in PROFIBUS (EN 50170)
applications. The driver output differential voltage exceeds the Profibus requirements of 2.1 V with a 54-Ω load. A signaling
rate of up to 40 Mbps allows technology growth to high data transfer speeds. The low bus capacitance provides low signal
distortion.
The SN65HVD1176 and SN75HVD1176 meet or exceed the requirements of ANSI standard TIA/EIA-485-A (RS-485) for
differential data transmission across twisted-pair networks. The driver outputs and receiver inputs are tied together to form
a half-duplex bus port, with one-fifth unit load, allowing up to 160 nodes on a single bus. The receiver output stays at logic
high when the bus lines are shorted, left open, or when no driver is active. The driver outputs are in high impedance when
the supply voltage is below 2.5 V to prevent bus disturbance during power cycling or during live insertion to the bus.
An internal current limit protects the transceiver bus pins in short-circuit fault conditions by limiting the output current to a
constant value. Thermal shutdown circuitry protects the device against damage due to excessive power dissipation caused
by faulty loading and drive conditions.
The SN75HVD1176 is characterized for operation at temperatures from 0°C to 70°C. The SN65HVD1176 is characterized
for operation at temperatures from −40°C to 85°C.
D PACKAGE
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
LOGIC DIAGRAM (POSITIVE LOGIC)
A
D
VCC
B
A
GND
B
DE
RE
R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
Copyright  2003, Texas Instruments Incorporated
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SLLS563C − JULY 2003 − REVISED APRIL 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
TA
0°C to 70°C
PACKAGED DEVICES(1)
MARKED AS
SN75HVD1176D
VN1176
−40°C to 85°C
SN65HVD1176D
VP1176
(1) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD1176DR).
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
SN65HVD1176, SN75HVD1176
Supply voltage(2), VCC
−0.5 V to 7 V
Voltage at any bus I/O terminal
−9 V to 14 V
Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 14)
−40 V to 40 V
Voltage input at any D, DE or RE terminal
−0.5 V to 7 V
Receiver output current, IO
Electrostatic discharge
−10 mA to 10 mA
Human Body Model, (HBM)(3)
All pins
4 kV
Bus terminals and GND
10 kV
Junction temperature, TJ
150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC standard 22. test method A114−A.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VCC
Voltage at either bus I/O terminal
High−level input voltage, VIH
Low−level input voltage, VIL
Differential input voltage, VID
Output current
Junction temperature, TJ (1)
4.75
A, B
MAX
5
5.25
UNIT
−7
12
2
0
VCC
0.8
A with respect to B
−12
12
Driver
−70
70
−8
8
−40
130
Ω
0
130
Ω
40
Mbps
D, DE, RE
Receiver
SN65HVD1176
SN75HVD1176
Differential load resistance, RL
Signaling rate, 1/tU1
(1) See the Thermal Characteristics table for more information on maintenance of this requirement.
2
NOM
V
mA
Ω
54
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VO
Open-circuit output voltage
A or B,
VOD(SS)
Steady-state differential output voltage magnitude
RL = 54 Ω,
See Figure 1
With common-mode loading,
(VTEST from −7 V to 12 V)
See Figure 2
∆|VOD(SS)|
Change in steady-state differential output voltage
between logic states
See Figure 1 and Figure 6
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage
VOC(PP)
VOD(RING)
Peak-to-peak common-mode output voltage
II
IO(OFF)
Input current
IOZ
IOS(P)
High impedance state output current
IOS(SS)
Steady-state short-circuit output current
COD
Differential output voltage over and under shoot
Output current with power off
MIN TYP(1)
TEST CONDITIONS
No load
0
See Figure 5
MAX
UNIT
VCC
V
2.1
2.9
2.1
2.7
−0.2
0
0.2
V
2
2.5
3
V
−0.2
0
0.2
V
V
0.5
RL = 54 Ω, CL = 50 pF, See Figure 6
D, DE
VCC < = 2.5 V
DE at 0 V
Peak short-circuit output current
DE at VCC,
See Figure 8
V
10% VOD(PP)
50
µA
−50
See receiver line input
current
VOS = −7 V to 12 V
VOS > 4 V,
Output driving low
VOS < 1 V,
Output driving high
Differential output capacitance
−250
250
60
90
135
−135
−90
−60
mA
mA
See receiver CI
(1) All typical values are at VCC = 5 V and 25°C.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
tPHL
Propagation delay time low-level-to-high-level output
tsk(p)
tr
Pulse skew | tPLH – tPHL |
tf
tt(MLH), tt(MHL)
Differential output fall time
Propagation delay time high-level-to-low-level output
TEST CONDITIONS
RL = 54 Ω, CL = 50 pF,
See Figure 3
Differential output rise time
Output transition skew
MIN
TYP
MAX
4
7
10
ns
4
7
10
ns
0
2
ns
3
7.5
ns
2
2
See Figure 4
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active output
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-to- high-impedance output
|tp(AZL) − tp(BZH)|
|tp(AZH) − tp(BZL)|
Enable skew time
|tp(ALZ) − tp(BHZ)|
|tp(AHZ) − tp(BLZ)|
Disable skew time
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active output
(from sleep mode)
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-output-to high-impedance
(to sleep mode)
t(CFB)
t(TSD)
Time from application of short-circuit to current foldback
See Figure 8
Time from application of short-circuit to thermal shutdown
TA = 25°C, See Figure 8
RL = 110 Ω,
CL = 50 pF,
See Figure 7a
and 7b
UNIT
3
7.5
ns
0.2
1
ns
10
20
ns
10
20
ns
0.55
1.5
ns
2.5
ns
1
4
µs
30
50
ns
RE at 0 V
RE at 5 V
0.5
100
µs
µs
(1) All typical values are at VCC = 5 V and 25°C.
3
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SLLS563C − JULY 2003 − REVISED APRIL 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT(+)
VIT(−)
Positive-going differential input voltage threshold
VHYS
VOH
Hysteresis voltage (VIT+ − VIT−)
VOL
IA, IB
Low-level output voltage
IA(OFF),
IB(OFF)
II
Bus pin input current
Receiver enable input current
RE
IOZ
RI
High-impedance -state output current
RE = VCC
Negative-going differential input voltage threshold
High-level output voltage
See Figure 9
VO = 2.4 V, IO = −8 mA
VO = 0.4 V, IO = 8 mA
VID = 200 mV, IOH = −8 mA, See Figure 9
VID = −200 mV, IOL = 8 mA, See Figure 9
VI = − 7 V to 12 V,
Other input = 0 V
MAX
−80
−20
mV
−200
−120
40
mV
4
4.6
V
0.2
0.4
V
−160
200
µA
−50
50
µA
−1
1
µA
VCC = 0V
60
Differential input capacitance
Common mode rejection
CMR
(1) All typical values are at 25°C.
UNIT
VCC = 4.75 V to 5.25 V
Input resistance
CID
MIN TYP(1)
kΩ
Test input signal is a 1.5 MHz sine wave
with amplitude 1 Vpp, capacitance
measured across A and B
7
See Figure 11
4
10
pF
V
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
tPLH
tPHL
Propagation delay time, low-to-high level output
20
25
Propagation delay time, high-to-low level output
20
25
tsk(p)
tr
Pulse skew | tPLH – tPHL |
1
2
Receiver output voltage rise time
2
4
tf
tPZH
Receiver output voltage fall time
2
4
tPHZ
tPZL
Propagation delay time, high-level-to-high-impedance output
tPLZ
tPZH
Propagation delay time, low-level-to-high-impedance output
tPHZ
tPZL
Propagation delay time, high-level-to-high-impedance output (active to standby)
tPLZ
Propagation delay time, low-level-to-high-impedance output (active to standby)
See Figure 10
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
DE at VCC,
See Figure 13
20
DE at VCC,
See Figure 14
20
20
20
UNIT
ns
ns
ns
ns
ns
DE at 0 V,
See Figure 12
1
4
µs
13
20
ns
DE at 0 V
See Figure 12
2
4
µs
13
20
ns
TYP
MAX
4
6
mA
Driver only, RE at VCC, DE at VCC, All other inputs open, no load
3.8
6
mA
Receiver only, RE at 0 V, DE at 0 V, All other inputs open, no load
3.6
6
mA
Standby only, RE at VCC, DE at 0 V, All other inputs open
0.2
5
µA
Propagation delay time, high-impedance-to-high-level output (standby to active)
Propagation delay time, high-impedance-to-low-level output (standby to active)
SUPPLY CURRENT
over recommended operating conditions
PARAMETER
TEST CONDITIONS
Driver and receiver, RE at 0 V, DE at VCC, All other inputs open, no load
ICC
4
Supply current
MIN
UNIT
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PARAMETER MEASUREMENT INFORMATION
NOTES:
Test load capacitance includes probe and jig capacitance (unless otherwise specified).
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 Ω (unless otherwise specified)
A
II
IO
27 Ω
VOD
0 V or 3 V
50 pF
27 Ω
D
B
IO
VOC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
A
60 Ω
VOD
0 V or 3 V
VTEST = −7 V to 12 V
D
375 Ω
B
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V
INPUT
0V
RL = 54 Ω
Signal
Generator
VOD
CL = 50 pF
50 Ω
90%
VOD(H)
10%
VOD(L)
OUTPUT
tr
tf
Figure 3. Driver Switching Test Circuit and Rise/Fall Time Measurement
D
1.5 V
1.5 V
tPLH
tPHL
A,B
50%
A
tt(MLH)
B
50%
tt(MHL)
50%
50%
Figure 4. Driver Switching Waveforms for Propagation Delay and Output Midpoint Time Measurements
5
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SLLS563C − JULY 2003 − REVISED APRIL 2005
27 Ω
A
VA
D
Signal
Generator
50 Ω
B
27 Ω
≈ 3.25 V
VB
50 pF
≈ 1.75 V
VOC(PP)
VOC
∆VOC(SS)
VOC
Figure 5. Driver VOC Test Circuit and Waveforms
VOD(SS)
VOD(RING)
VOD(PP)
0 V Differential
VOD(RING)
VOD(SS)
NOTE: VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the
VOD(H) and VOD(L) steady state values.
Figure 6. VOD(RING) Waveform and Definitions
3V
DE
RL = 110 Ω
0V
D
DE
Signal
Generator
A
B
50 Ω
VCC
CL = 50 pF
RL = 110 Ω
1.5 V
tp(AZL)
tp(ALZ)
A
0V
50%
VOL +0.5 V
tp(BHZ)
tp(BZH)
CL = 50 pF
50%
B
VOL −0.5 V
a) D at Logic Low
DE
3V
1.5 V
1.5 V
RL = 110 Ω
0V
3V
D
DE
Signal
Generator
A
B
CL = 50 pF
tp(AZH)
A
VOH −0.5 V
tp(BLZ)
tp(BZL)
CL = 50 pF
B
b) D at Logic High
Figure 7. Driver Enable/Disable Test
6
50%
RL = 110 Ω
VCC
50 Ω
tp(AHZ)
50%
VOH +0.5 V
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250
Output
Current |mA|
IOS
D
135
VOS
60
Voltage
Source
time
t(CFB)
t(TSD)
Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t = 0)
IA
VA
VIC
VA + VB
2
A
R
VID
VB
IO
B
VO
IB
Figure 9. Receiver DC Parameter Definitions
Signal
Generator
50 Ω
Input B
VID
A
B
Signal
Generator
R
IO
Input A
tPLH
VO
CL = 15 pF
50 Ω
1.5 V
50%
Output
90%
1.5 V
tr
0V
tPHL
VOH
10% V
OL
tf
Figure 10. Receiver Switching Test Circuit and Waveforms
50 Ω
100 nF
VI = A sin 2pft
1 MHz < f < 50 MHz
50 Ω
A
R
470 nF
RE
B
DE
2.2 kΩ
Voffset =
−2 V to 7 V
2.2 kΩ
VR
Scope
D
Scope
GND
VCC
100 nF
VR shall be greater than
2 V throughout this test.
Figure 11. Receiver Common-Mode Rejection Test Circuit
7
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3V
A
0 V or 1.5 V
R
B
1.5 V or 0 V
VI
S1
CL = 15 pF ±20%
RE
Input
Generator
A
1 kΩ ± 1%
VO
B
50 Ω
3V
VI
1.5 V
0V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
VO
GND
tPZL(2)
3V
1.5 V
VO
A at 0 V
B at 1.5 V
S1 to A
VOL
Figure 12. Receiver Enable Time From Standby (Driver Disabled)
VCC
VCC
D
DE
A
54 Ω
B
3V
R
RE
Signal
Generator
1 kΩ
0V
RE
1.5 V
0V
CL = 15 pF
tPZH
tPHZ
50 Ω
R
1.5 V
VOH
VOH −0.5 V
GND
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output High (Driver Active)
8
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SLLS563C − JULY 2003 − REVISED APRIL 2005
0V
VCC
D
DE
A
54 Ω
B
3V
1 kΩ
R
5V
RE
1.5 V
0V
CL = 15 pF
RE
tPZL
Signal
Generator
tPLZ
VCC
50 Ω
R
1.5 V
VOL +0.5 V
VOL
Figure 14. Receiver Enable Test Circuit and Waveforms, Data Output Low (Driver Active)
100 Ω
VTEST
0V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
15 µs
1.5 ms
−VTEST
Figure 15. Test Circuit and Waveforms, Transient Over-Voltage Test
9
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DEVICE INFORMATION
DRIVER FUNCTION TABLE
INPUT
ENABLE
D
DE
A
OUTPUTS
H
H
H
L
L
H
L
H
X
L
Z
Z
X
OPEN
Z
Z
OPEN
H
H
L
B
H = high level, L= low level, X = don’t care,
Z = high impedance (off)
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = (VA – VB)
VID ≥ 0.02 V
RE
R
L
H
−0.2 V < VID < −0.02 V
L
?
VID ≤ −0.2 V
X
L
L
H
Z
X
OPEN
Z
Open circuit
L
H
Short Circuit
L
H
Idle (terminated) bus
L
H
H = high level, L= low level, X = don’t care,Z = high impedance (off),
? = indeterminate
THERMAL CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETERS
θJA
Junction-to-ambient thermal resistance(3)
θJB
θJC
Junction-to-board thermal resistance
PD
MIN
SN75HVD1176
Ambient air temperature
SN65HVD1176
SN75HVD1176
MAX
UNITS
°C/W
High-K board(5), no air flow
128.7
°C/W
High-K board
77.6
°C/W
43.9
°C/W
RL = 54 Ω, CL= 50 pF, 0 V to 3 V
15 MHz, 50% duty cycle square
wave input, driver and receiver
enabled
Device power dissipation
TYP(2)
208.3
Junction-to-case thermal resistance
SN65HVD1176
TA
TEST CONDITIONS
Low-K board(4), no air flow
277
Low-K board, no air flow,
PD = 318 mW
−40
High-K board, no air flow,
PD = 318 mW
−40
0
0
318
mW
64
°C
89
°C
TSD Thermal shut down junction temperature
150
°C
(1) See Application Information section for an explanation of these parameters.
(2) All typical values are with VCC = 5 V and TA = 25°C.
(3) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment. This
methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(4) JESD51−3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(5) JESD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
10
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SLLS563C − JULY 2003 − REVISED APRIL 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
200 kΩ
Input
500 Ω
Input
500 Ω
200 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
18 kΩ
16 V
18 kΩ
90 kΩ
90 kΩ
Input
Input
16 V
18 kΩ
16 V
18 kΩ
A and B Outputs
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
11
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SLLS563C − JULY 2003 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
DRIVER SUPPLY CURRENT
vs
SIGNALING RATE
DIFFERENTIAL OUTPUT VOLTAGE
vs
LOAD CURRENT
66
5
VOD − Differential Output Voltage − V
VCC = 5.25 V
4
I DD − Driver Supply Current − mArms
VCC = 5 V
4.5
100 Ω
3.5
50 Ω
3
VCC = 4.75 V
2.5
2
1.5
1
64
62
60
VCC = 5 V
TA = 25°C
RL = 56 Ω,
DE and RE at 5 V
Input 0 V to 3 V PRBS
See Figure 3
58
56
0.5
TA = 255C
0
0
54
20
40
60
IL − Load Current − mA
0
80
10
3.75
VCC = 4.75 V
Driver Rise, Fall Time − ns
Driver Output Transition Skew − ns
4
0.25
VCC = 5 V
0.15
VCC = 5.25 V
0.1
0.05
0
−40
RL = 54 Ω,
CL = 50 pF
See Figure 3
VCC = 4.75 V
3.5
3.25
VCC = 5 V
3
VCC = 5.25 V
2.75
2.5
2.25
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 18
12
50
DRIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
RL = 54 Ω,
CL = 50 pF
See Figure 4
0.2
40
Figure 17
DRIVER OUTPUT TRANSITION SKEW
vs
FREE-AIR TEMPERATURE
0.3
30
Signaling Rate − Mbps
Figure 16
0.35
20
85
2
−40
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 19
85
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DRIVER ENABLE SKEW
vs
FREE-AIR TEMPERATURE
0.7
VCC = 4.75 V
Driver Enable Skew − ns
0.6
0.5
VCC = 5.25 V
0.4
VCC = 5 V
0.3
0.2
0.1
RL = 110 Ω,
CL = 50 pF
See Figure 7
0
−40
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 20
APPLICATION INFORMATION
THERMAL CHARACTERISTICS OF IC
PACKAGES
qJA (Junction-to-Ambient Thermal Resistance) is
defined as the difference in junction temperature to
ambient temperature divided by the operating power.
θJA is not a constant and is a strong function of:
D
the PCB design (50% variation)
D
altitude (20% variation)
D
device power (5% variation)
θJA can be used to compare the thermal performance of
packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB
construction, test chamber volume, sensor locations, and
the thermal characteristics of holding fixtures. θJA is often
misused when it is used to calculate junction temperatures
for other installations.
TI uses two test PCBs as defined by JEDEC
specifications. The low-k board gives average in-use
condition thermal performance, and it consists of a single
copper trace layer 25 mm long and 2-oz thick. The high-k
board gives best case in-use condition, and it consists of
two 1-oz buried power planes with a single copper trace
layer 25 mm long and 2-oz thick. A 4% to 50% difference
in θJA can be measured between these two test cards
qJC (Junction-to-Case Thermal Resistance) is defined
as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted
package up against a copper block cold plate to force heat
to flow from die, through the mold compound into the
copper block.
θJC is a useful thermal characteristic when a heatsink is
applied to package. It is not a useful characteristic to
predict junction temperature because it provides
pessimistic numbers if the case temperature is measured
in a nonstandard system and junction temperatures are
backed out. It can be used with θJB in 1-dimensional
thermal simulation of a package system.
13
www.ti.com
SLLS563C − JULY 2003 − REVISED APRIL 2005
qJB (Junction-to-Board Thermal Resistance) is defined
as the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the
die) when the PCB is clamped in a cold-plate structure. θJB
is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die
and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and
can be used for simple 1-dimensional network analysis of
package system (see Figure 21).
Ambient Node
qCA Calculated
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
Figure 21. Thermal Resistance
14
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD1176D
ACTIVE
SOIC
D
8
SN65HVD1176DR
ACTIVE
SOIC
D
8
SN75HVD1176D
ACTIVE
SOIC
D
8
SN75HVD1176DR
ACTIVE
SOIC
D
SN75HVD1176DRG4
ACTIVE
SOIC
D
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
75
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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