SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A – MAY 2002 – REVISED JULY 2002
D
D
D
D
D
D
D
D
D
D
DL PACKAGE
(TOP VIEW)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Member of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes PCB
Layout
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, highly
accelerated stress test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
description
The SN74ACT16245Q-EP is a 16-bit bus
transceiver organized as dual-octal noninverting
3-state
transceivers
and
designed
for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1G
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2G
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on
the logic level at the direction-control (DIR) input. The enable (G) input can be used to disable the devices so
that the buses are effectively isolated.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 125°C
SSOP – DL
Tape and reel
SN74ACT16245QDLREP
ACT16245QEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A – MAY 2002 – REVISED JULY 2002
FUNCTION TABLE
(each section)
CONTROL
INPUTS
G
OPERATION
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
logic diagram (positive logic)
1DIR
1
2DIR
48
1A1
25
1G
47
2A1
2
24
2G
36
13
1B1
To Seven Other Transceivers
2B1
To Seven Other Transceivers
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±260 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A – MAY 2002 – REVISED JULY 2002
recommended operating conditions (see Note 3)
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage (see Note 4)
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
Low-level output current
High-level input voltage
2
High-level output current
Input transition rise or fall rate
0
UNIT
V
V
0.8
V
VCC
VCC
V
–16
mA
V
16
mA
10
ns/V
TA
Operating free-air temperature
–40
125
°C
NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 kW or greater to keep them from floating. Refer
to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. All VCC and GND pins must be connected to the proper-voltage power supply.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A – MAY 2002 – REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –50
50 mA
VOH
16 mA
IOH = –16
IOH = –24 mA{
Control inputs
A or B ports}
IOL = 24 mA{
VI = VCC or GND
MIN
4.5 V
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.94
5.5 V
4.94
4.94
MAX
UNIT
4.4
V
3.85
4.5 V
IOL = 16 mA
II
IOZ
TA = 25°C
TYP
MAX
5.5 V
IOL = 50 mA
VOL
MIN
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.5
5.5 V
0.36
0.5
5.5 V
V
0.5
5.5 V
±0.1
±1
mA
mA
VO = VCC or GND
VI = VCC or GND,
5.5 V
±0.5
±10
ICC
IO = 0
5.5 V
8
160
mA
∆ICCw
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
Control inputs
Cio
A or B ports
VI = VCC or GND
VO = VCC or GND
5V
4.5
pF
5V
16
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current II.
§ This is the increase in supply current for each input that is at one of the specified TTL-voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
G
B or A
tPHZ
tPLZ
G
B or A
MIN
TA = 25°C
TYP
MAX
MIN
MAX
3.2
6.9
9.3
3.2
11.5
2.6
6.4
9.2
2.6
11.1
2.7
6.4
9.1
2.7
10.9
3.4
7.4
10.5
3.4
12.6
5.8
9.2
11.6
5.8
13.4
5.5
8.5
10.8
5.5
12.7
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
4
Power dissipation capacitance per transceiver
POST OFFICE BOX 655303
TEST CONDITIONS
Outputs enabled
Outputs disabled
• DALLAS, TEXAS 75265
CL = 50 pF,
pF
f = 1 MHz
TYP
52
10
UNIT
pF
SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A – MAY 2002 – REVISED JULY 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPLH
Output
tPHL
VOH
50% VCC
VOL
50% VCC
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
3V
1.5 V
1.5 V
0V
tPLZ
tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
50% VCC
20% VCC
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
≈VCC
50% VCC
80% VCC
VOH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated