SDAS060C − APRIL 1982 − REVISED DECEMBER 1994
•
•
•
D OR N PACKAGE
(TOP VIEW)
Combines Decoder and 3-Bit Address
Register
Incorporates Two Enable Inputs to Simplify
Cascading
Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
A
B
C
CLK
G2
G1
Y7
GND
description
1
16
2
15
3
14
4
13
5
12
6
11
7
10
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
8
9
The SN74AS131A is a 3-line to 8-line
decoder/demultiplexer with registers on the three
address inputs. When the clock (CLK) input goes
from low to high, the device acts as a decoder/
demultiplexer and the address present at the select (A, B, and C) inputs is stored in the registers. Further
address changes are ignored until the next rising transition of CLK. The output-enable (G1, G2) inputs control
the state of the outputs independently of the select or CLK inputs. All of the outputs are high unless G1 is high
and G2 is low. This device is ideally suited for implementing glitch-free decoders in strobed (stored-address)
applications in bus-oriented systems.
The SN74AS131A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
ENABLE
CLK
OUTPUTS
SELECT
G1
G2
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
X
X
H
X
X
X
H
H
H
H
H
H
H
Y7
H
X
L
X
X
X
X
H
H
H
H
H
H
H
H
↑
H
L
L
L
L
L
H
H
H
H
H
H
H
↑
H
L
L
L
H
H
L
H
H
H
H
H
H
↑
H
L
L
H
L
H
H
L
H
H
H
H
H
↑
H
L
L
H
H
H
H
H
L
H
H
H
H
↑
H
L
H
L
L
H
H
H
H
L
H
H
H
↑
H
L
H
L
H
H
H
H
H
H
L
H
H
↑
H
L
H
H
L
H
H
H
H
H
H
L
H
↑
H
L
H
H
H
H
H
H
H
H
H
H
L
L or H
H
L
X
X
X
Outputs corresponding to stored address = L; all others = H.
Copyright 1994, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
1
SDAS060C − APRIL 1982 − REVISED DECEMBER 1994
logic symbols (alternatives)†
CLK
A
B
C
G1
X/Y
4
C8
0
1
1
8D
2
1
2
3
4
3
4
5
&
6
2
15
14
13
12
11
10
9
6
5
EN
G2
7
7
Y0
CLK
Y1
A
Y2
B
Y3
C
Y4
4
1
G1
5
Y7
0
G
3
6
0
1
8D
2
Y5
Y6
DMUX
C8
2
0
7
3
2
4
5
&
6
EN
7
G2
15
14
13
12
11
10
9
7
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
G2
Enable
Inputs
G1
5
15
6
14
CLK
Y1
4
13
A
Y0
1
12
1D
Y2
Y3
Data
Outputs
C1
11
Select
Inputs
B
2
10
1D
Y4
Y5
C1
9
C
3
1D
7
C1
2
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
Y6
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SDAS060C − APRIL 1982 − REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
−2
mA
IOL
fclock
Low-level output current
20
mA
100
MHz
High-level input voltage
2
Clock frequency
V
0
CLK high
5
CLK low
5
tw
Pulse duration
tsu
Setup time, A, B, and C before CLK↑
th
TA
Hold time, A, B, and C after CLK↑
0
Operating free-air temperature
0
V
ns
3.5
ns
ns
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = −18 mA
IOH = − 2 mA
VOL
II
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 20 mA
VI = 7 V
IIH
IIL
IO§
VCC = 5.5 V,
VCC = 5.5 V,
VI = 2.7 V
VI = 0.4 V
VCC = 5.5 V,
VCC = 5.5 V
VO = 2.25 V
ICCH
ICCL
MIN
TYP‡
MAX
UNIT
−1.2
V
VCC −2
V
0.35
−30
15
0.5
V
0.1
mA
20
µA
−0.5
mA
−112
mA
29
mA
VCC = 5.5 V
16
30
mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
SDAS060C − APRIL 1982 − REVISED DECEMBER 1994
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
MIN
fmax
tPLH
MAX
100
MHz
2
14.5
2
9.5
2
10
2
9
2
7
tPHL
2
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
8.5
tPHL
tPLH
tPHL
tPLH
4
CLK
Y
G1
Y
G2
Y
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
UNIT
ns
ns
ns
SDAS060C − APRIL 1982 − REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
From Output
Under Test
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
3.5 V
Input
tPHZ
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
VOL
0.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
[3.5 V
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
0.3 V
[0 V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
5
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