TI SN74GTLP21395PWR

SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
D
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
Y Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (–12 mA/12 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
Polarity Control Selects True or
Complementary Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGV, DW, OR PW PACKAGE
(TOP VIEW)
1Y
1T/C
2Y
GND
1OEAB
VCC
1A
GND
2A
2OEAB
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1OEBY
2T/C
2OEBY
GND
1B
ERC
2B
GND
VREF
BIAS VCC
description
The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require
individual output-enable and true/complement controls. The device allows for transparent and inverted
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback
path for control and diagnostics monitoring. The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to
work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V),
reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved
GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several
backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent
load impedance down to 11 Ω.
The Y outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC and TI-OPC are trademarks of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP21395 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
GQN PACKAGE
(TOP VIEW)
1
2
2
3
terminal assignments
4
1
2
3
4
A
A
1T/C
1Y
1OEBY
2T/C
B
B
GND
GND
2Y
2OEBY
C
C
1OEAB
ERC
1B
D
D
VCC
GND
GND
1A
2B
E
E
2OEAB
2A
BIAS VCC
VREF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
Tube
SN74GTLP21395DW
Tape and reel
SN74GTLP21395DWR
TSSOP – PW
Tape and reel
SN74GTLP21395PWR
GU395
TVSOP – DGV
Tape and reel
SN74GTLP21395DGVR
GU395
VFBGA – GQN
Tape and reel
SN74GTLP21395GQNR
GU395
SOIC – DW
–40°C to 85°C
TOP-SIDE
MARKING
GTLP21395
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY,
and 2T/C control 2A, 2B, and 2Y.
OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high,
the B-port output is disabled.
A separate LVTTL A input and Y output provide a feedback path for control and diagnostics monitoring. OEBY
controls the Y output. When OEBY is low, the Y output is active. When OEBY is high, the Y output is disabled.
T/C selects polarity of data transmission in both directions. When T/C is high, data transmission is true, and
A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary,
and inverted A data goes to the B bus and inverted B data goes to the Y bus.
Function Tables
OUTPUT CONTROL
INPUTS
T/C
OEAB
OEBY
OUTPUT
MODE
Isolation
X
H
H
Z
H
L
H
A data to B bus
H
H
L
B data to Y bus
H
L
L
A data to B bus, B data to Y bus
L
L
H
Inverted A data to B bus
L
H
L
Inverted B data to Y bus
L
L
L
Inverted A data to B bus,
Inverted B data to Y bus
True transparent
True transparent
with feedback path
Inverted transparent
Inverted transparent
with feedback path
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT
ERC
LOGIC LEVEL
OUTPUT
B-PORT
EDGE RATE
H
Slow
L
Fast
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
logic diagram (positive logic)
12
VREF
15
ERC
5
1OEAB
1T/C
1A
2
7
16
1B
20
1OEBY
1Y
1
10
2OEAB
2T/C
2A
19
14
9
18
2OEBY
3
2Y
Pin numbers shown are for DGV, DW, and PW packages.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2B
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1): A inputs, ERC, and control inputs . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): Y outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, IO: Y outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
recommended operating conditions (see Notes 4 through 7)
VCC,
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
B port
Except B port
B port
Except B port
VREF+0.05
2
B port
V
V
V
V
V
VREF–0.05
0.8
V
–18
mA
Y outputs
–12
mA
Y outputs
12
Except B port
High-level output current
IOL
MIN
B port
100
Outputs enabled
10
–40
ns/V
µs/V
20
Operating free-air temperature
mA
85
°C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally it is two-thirds VTT. TI-OPC is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize
current drain.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 3.15 V,
VCC = 3.15 V to 3.45 V,
Y outputs
II = –18 mA
IOH = –100 µA
IOH = –6 mA
VCC = 3
15 V
3.15
IOH = –12 mA
VCC = 3
3.15
15 V
II‡
IOZ‡
ICC
VCC = 3.15 V
UNIT
–1.2
V
V
2
0.2
0.55
0.8
0.2
IOL = 64 mA
IOL = 100 mA
0.55
VCC = 3.45 V,
VI = 0 to 5.5 V
±10
Y outputs
VCC = 3.45 V,
VO = 0 to 5.5 V
±10
B port
VCC = 3.45 V, VREF within 0.6 V of VTT,
±10
Y outputs or B port
VCC = 3.45 V, IO = 0,
VI (A or control inputs) = VCC or GND,
VI (B port) = VTT or GND
VO = 0 to 2.3 V
Outputs high
Control inputs
Co
Y outputs
Cio
B port
µA
µA
20
Outputs low
20
Outputs disabled
20
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
A-port inputs
V
0.4
A-port and
control inputs
∆ICC§
Ci
MAX
VCC–0.2
2.4
IOL = 12 mA
IOL = 10 mA
VOL
B port
TYP†
IOL = 100 µA
IOL = 6 mA
VCC = 3.15 V to 3.45 V,
Y outputs
MIN
1.5
3 15 V or 0
VI = 3.15
VO = 3.15 V or 0
4
4.5
3.5
5
mA
mA
pF
5
5.5
pF
VO = 1.5 V or 0
7
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
10.5
pF
hot-insertion specifications for A inputs and Y outputs over recommended operating free-air
temperature range
PARAMETER
TEST CONDITIONS
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 5.5 V
VO = 0.5 V to 3 V,
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
MIN
MAX
UNIT
10
µA
OEBY = 0
±30
µA
OEBY = 0
±30
µA
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
BIAS VCC = 0,
IOZPD
VCC = 1.5 V to 0,
VCC = 0 to 3.15 V
ICC
(BIAS VCC)
VO
IO
VCC = 3.15 V to 3.45 V
VCC = 0,
VCC = 0,
MIN
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
VO = 0.5 V to 1.5 V,
BIAS VCC = 0,
VO = 0.5 V to 1.5 V,
BIAS VCC = 3
3.15
15 V to 3
3.45
45 V
V,
VO (B port) = 0 to 1.5
15V
BIAS VCC = 3.3 V,
IO = 0
VO (B port) = 0.6 V
BIAS VCC = 3.15 V to 3.45 V,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
10
µA
OEAB = 0
±30
µA
OEAB = 0
±30
µA
0.95
–1
5
mA
10
µA
1.05
V
µA
7
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
A
B
Slow
tPLH
tPHL
A
B
Fast
tPLH
tPHL
A
Y
Slow
tPLH
tPHL
A
Y
Fast
tPLH
tPHL
T/C
B
Slow
tPLH
tPHL
T/C
B
Fast
ten
tdis
OEAB
B
Slow
ten
tdis
OEAB
B
Fast
tr
time B outputs (20% to 80%)
Rise time,
tf
Fall time,
time B outputs (80% to 20%)
tPLH
tPHL
B
Y
tPLH
tPHL
T/C
Y
OEBY
Y
ten
tdis
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP‡
MAX
3.6
6.2
1.7
6
2.7
5.3
1.4
5
4
10.4
3.8
9.8
3.6
9.3
3.4
8.8
3.5
6.6
1.8
6.2
1.4
5.6
2.3
5.5
3.7
6.4
1.5
6.2
2.8
5.3
1.8
5.2
Slow
2.5
Fast
1.3
Slow
3
Fast
2.6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.8
5.6
1.4
5.1
1.7
5.1
1.4
5.1
1
5.1
1
4.8
ns
ns
ns
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature, VREF = 1 V, standard lumped loads (CL = 30 pF for B port and CL = 50 pF for Y port)
(unless otherwise noted)(see Figure 1)†
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE‡
tsk(LH)§
tsk(HL)§
A
B
Slow
tsk(LH)§
tsk(HL)§
A
tsk(LH)§
tsk(HL)§
B
PARAMETER
tsk(t)
( )§
MIN
MAX
0.3
UNIT
ns
0.4
B
Fast
0.3
ns
0.3
0.4
Y
ns
0.2
A
B
Slow
1.8
Fast
1.5
B
Y
tsk(prLH)¶
tsk(prHL)¶
A
B
Slow
tsk(prLH)¶
tsk(prHL)¶
A
B
Fast
tsk(prLH)¶
tsk(prHL)¶
B
Y
ns
1
0.7
2
0.5
1.7
1.2
ns
ns
ns
1.6
† Actual skew values between GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
‡ Slow (ERC = L) and Fast (ERC = H)
§ tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
¶ tsk(prLH)/tsk(prHL) – The magnitude of the difference in propagation delay times between corresponding terminals of two logic devices when both
logic devices operate with the same supply voltages and at the same temperature, and have identical package types, identical specified loads,
and identical logic functions. Furthermore, these values are provided by SPICE simulations.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
6V
500 Ω
From Output
Under Test
S1
Open
12.5 Ω
From Output
Under Test
CL = 30 pF
(see Note A)
GND
CL = 50 pF
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
S1
Open
6V
GND
LOAD CIRCUIT FOR Y OUTPUTS
Test
Point
LOAD CIRCUIT FOR B OUTPUTS
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1V
Output
1V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A input to B port)
1V
0V
tPLH
1.5 V
tPLZ
3V
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
VOH
Output
1.5 V
tPZL
1.5 V
1V
Input
3V
Output
Control
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A input)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to Y output)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in the backplane. See
www.ti.com/sc/gtlp for more information.
22 Ω
.25”
ZO = 50 Ω
1”
1”
.25”
22 Ω
1.5 V
1.5 V
1.5 V
11 Ω
Conn.
Conn.
Conn.
Conn.
From Output
Under Test
1”
1”
1”
LL = 14 nH
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 19
Slot 20
Test
Point
CL = 18 pF
Drvr
Slot 1
Figure 3. High-Drive RLC Network
Figure 2. High-Drive Test Backplane
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
A
B
Slow
tPLH
tPHL
A
B
Fast
tPLH
tPHL
A
Y
Slow
tPLH
tPHL
A
Y
Fast
tr
Rise time,
time B outputs (20% to 80%)
tf
Fall time,
time B outputs (80% to 20%)
TYP‡
4.3
4.2
3.8
3.4
6.6
6.5
6
6
Slow
1.5
Fast
1
Slow
2.6
Fast
2
UNIT
ns
ns
ns
ns
ns
ns
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
POST OFFICE BOX 655303
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11
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
operational description
The GTLP21395 is designed specifically for use with the TI 1394 backplane layer controller family to transmit
the 1394 backplane serial bus across parallel backplanes. But, it is a versatile two 1-bit device that also can
provide multiple 1-bit clocks or an ATM read and write clock in multislot parallel backplane applications.
The 1394–1995 is an IEEE designation for a high-performance serial bus. This serial bus defines both a
backplane (e.g., GTLP, VME, FB+, CPCI, etc.) physical layer and a point-to-point cable-connected virtual bus.
The backplane version operates at 25, 50, or 100 Mbps, whereas the cable version supports data rates of 100,
200, and 400 Mbps. Both versions are compatible at the link layer and above. The interface standard defines
the transmission method, media in the cable version, and protocol. The primary application of the cable version
is the interconnection of digital A/V equipment and integration of I/O connectivity at the back panel of personal
computers using a low-cost, scalable, high-speed serial interface. The primary application of the backplane
version is to provide a robust control interface to each daughter card. The 1394 standard also provides new
services such as real-time I/O and live connect/disconnect capability for external devices.
electrical
The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both
chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory
space interconnected between devices, or as if devices resided in slots on the main backplane. Device
addressing is 64 bits wide, partitioned as 10 bits for bus ID, 6 bits for node ID, and 48 bits for memory addresses.
The result is the capability to address up to 1023 buses, each having up to 63 nodes and each with 281 terabytes
of memory. Memory-based addressing, rather than channel addressing, views resources as registers or
memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a unit, to be
individually addressed, reset, and identified. Multiple nodes can reside physically in a single module, and
multiple ports can reside in a single node.
Some key features of the 1394 topology are multimaster capabilities, live connect/disconnect (hot plugging)
capability, genderless cabling connectors on interconnect cabling, and dynamic node address allocation as
nodes are added to the bus. A maximum of 63 nodes can be connected to one network.
The cable-based physical interface uses dc-level line states for signaling during initialization and arbitration.
Both environments use dominant mode addresses for arbitration. The backplane environment does not have
the initialization requirements of the cable environment because it is a physical bus and does not contain
repeaters. Due to the differences, a backplane-to-cable bridge is required to connect these two environments.
The signals transmitted on both the cable and backplane environments are NRZ with data-strobe (DS)
encoding. DS encoding allows only one of the two signal lines to change each data-bit period, essentially
doubling the jitter tolerance with very little additional circuitry overhead in the hardware.
12
POST OFFICE BOX 655303
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SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
protocol
Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and
transaction layer information to an explicit address. The isochronous format broadcasts data based on channel
numbers rather than specific addressing. Isochronous packets are issued on the average of each 125 µs in
support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same
interface allows both non-real-time and real-time critical applications on the same bus. The cable environment’s
tree topology is resolved during a sequence of events, triggered each time a new node is added or removed
from the network. This sequence starts with a bus reset phase, where previous information about a topology
is cleared. The tree ID sequence determines the actual tree structure, and a root node is dynamically assigned,
or it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows
each node on the network to identify itself to all other nodes. During the self-ID process, each node is assigned
an address. After all the information has been gathered on each node, the bus goes into an idle state, waiting
for the beginning of the standard arbitration process.
The backplane physical layer shares some commonality with the cable physical layer. Common functions
include: bus-state determination, bus-access protocols, encoding and decoding functions, and synchronization
of received data to a local clock.
backplane features
D
D
D
D
D
25-, 50-, and 100-Mbps data rates for backplane environments
Live connection/disconnection possible without data loss or interruption
Configuration ROM and status registers supporting plug and play
Multidrop or point-to-point topologies supported.
Specified bandwidth assignments for real-time applications
applicability and typical application for IEEE 1394 backplane
The 1394 backplane serial bus (BPSB) plays a supportive role in backplane systems, specifically GTLP,
FutureBus+, VME64, and proprietary backplane bus systems. This supportive role can be grouped into three
categories:
D
Diagnostics
–
–
–
D
System enhancement
–
–
–
–
D
Alternate control path to the parallel backplane bus
Test, maintenance, and troubleshooting
Software debug and support interface
Fault tolerance
Live insertion
CSR access
Auxiliary 2-bit bus with a 64-bit address space to the parallel backplane bus
Peripheral monitoring
–
Monitoring of peripherals (disk drives, fans, power supplies, etc.) in conjunction with another externally
wired monitor bus, such as defined by the Intelligent Platform Management Interface (IPMI)
The 1394 backplane physical layer (PHY) and the SN74GTLP21395 provide a cost-effective way to add
high-speed 1394 connections to every daughter card in almost any backplane. More information on the
backplane PHY devices and how to implement the 1394 standard in backplane and cable applications can be
found at www.ti.com/sc/1394.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
SN74GTLP21395 interface with the TSB14AA1 1394 backplane PHY
D
D
D
D
D
D
D
D
D
1A, 1B, and 1Y are used for the PHY data signals.
2A, 2B, and 2Y are used for the PHY strobe signals.
PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
1OEBY and 2OEBY are connected to GND because the transceiver must always be able to receive signals
from the backplane and relay them to the PHY.
1T/C and 2T/C are connected to GND for inverted signals.
VCC is nominal 3.3 V.
BIAS VCC is connected to nominal 3.3 V to support live insertion.
VREF is normally 2/3 of VTT.
ERC is normally connected to VCC for slow edge-rate operation because frequencies of only 50 MHz (S100)
and 25 MHz (S50) are required.
logical representation
VCC
TSB14AA1
3.3-V VCC
SN74GTLP21395
1 kΩ
TDOE
1OEAB
Tdata 1A
1B
2
D0–D1
BPdata
Rdata 1Y
Host
Interface
CTL0–CTL1
1394
LinkLayer
LREQ
Controller
2
1394
Backplane
PhysicalLayer
Controller
OCDOE
2OEAB
Tstrb 2A
2B
SCLK
BPstrb
Rstrb 2Y
14
POST OFFICE BOX 655303
GND
1OEBY
1T/C
GND
GND
2OEBY
2T/C
GND
• DALLAS, TEXAS 75265
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
physical representation
64-Bit Data Bus
32- to 64-Bit Address Bus
GTLP21395 Transceiver
1394 Backplane PHY
1394 Link-Layer Controller
Host Microprocessor
Terminators
Backplane Trace
Connectors
VME/FB+/CPCI or
GTLP Transceivers
STRB
2A
Module
Module
Module
Node
Node
Node
PHY
PHY
PHY
2Y
1A
1Y
VTT
RTT
DATA
VTT
2B
STRB
RTT
DATA
1B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74GTLP21395DGVR
ACTIVE
TVSOP
DGV
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74GTLP21395DW
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74GTLP21395DWR
ACTIVE
SOIC
DW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74GTLP21395GQNR
ACTIVE
VFBGA
GQN
20
1000
None
SNPB
Level-1-240C-UNLIM
SN74GTLP21395PW
ACTIVE
TSSOP
PW
20
70
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74GTLP21395PWR
ACTIVE
TSSOP
PW
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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