SLDS034 − DECEMBER 1986 − REVISED JULY 1889 D Each Device Drives 32 Lines D 180-V Open-Drain Parallel Outputs D 220-mA Parallel Output Sink Current D D D D SN751506 . . . FT PACKAGE (TOP VIEW) Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Q17 NC GND NC NC CLOCK VCC NC SERIAL OUT Capability CMOS-Compatible Inputs Strobe Input Provided Serial Data Output for Cascade Operation Inputs Have Built-In Electrostatic Discharge Protection description The SN751506 and the SN751516 are monolithic integrated circuits designed to drive the scan lines of a dc plasma panel display. The SN751516 pin sequence is reversed from the SN751506 for ease in printed-circuit-board layout. Each device consists of a 32-bit shift register and 32 OR gates. Serial data is entered into the shift register on the high-to-low transition of the clock input. When STROBE is low, all Q outputs are in the off state. Outputs are open-drain JFET transistors with a breakdown voltage in excess of 180 V. The outputs have a 220-mA sink current capability in the on state. Only one Q output should be allowed to be in the on state at a time. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 NC GND NC STROBE NC VCC NC DATA IN SN751516 . . . FT PACKAGE (TOP VIEW) SERIAL OUT from the shift register can be used to cascade shift registers. This output is not affected by the STROBE input. All inputs are CMOS compatible with ESD protection built in. Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 NC GND NC STROBE NC VCC NC DATA IN The SN751506 and SN751516 are characterized for operation from 0°C to 70°C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Q17 NC GND NC NC CLOCK VCC NC SERIAL OUT NC − No internal connection Copyright 1989, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SLDS034 − DECEMBER 1986 − REVISED JULY 1889 logic symbols† STROBE CLOCK DATA IN 29 21 25 SN751506 SN751516 CMOS/ PLASMA DISP CMOS/ PLASMA DISP EN2 STROBE SRG32 CLOCK C1/→ 48 47 2 2 1D .. . .. . .. . 33 16 2 2 .. . .. . .. . 2 1 24 2 2 Q1 Q2 DATA IN 20 EN2 SRG32 28 C1/→ 24 1 2 2 2 1D .. . .. . .. . Q16 Q17 16 33 2 2 .. . Q31 Q32 SERIAL OUT .. . .. . 47 48 25 2 2 Q1 Q2 Q16 Q17 Q31 Q32 SERIAL OUT † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) STROBE R1 CLOCK Q1 R2 32-Bit Static Shift Register DATA IN Q2 .. . R31 .. . 28 Outputs (Q3 thru Q30) Not Shown Q31 R32 Q32 SERIAL OUT FUNCTION TABLE CONTROL INPUTS FUNCTION CLOCK STROBE Load ↓ No ↓ X X Strobe X X L H SHIFT REGISTERS R1 THRU R32 OUTPUTS SERIAL QI THRU Q32 Load and shift‡ No change R32 R32 Determined by STROBE As determined above R32 R32 All high impedance R1 through R32 H = high level, L = low level, X = irrelevant, ↓= high-to-low transition. ‡ R32 takes on the state of R31, R31 takes on the state of R30, . . . R2 takes on the state of R1, and R1 takes on the state of the data input. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SLDS034 − DECEMBER 1986 − REVISED JULY 1889 . . . typical operating sequence CLOCK DATA IN Valid Irrelevant Shift Register Invalid Valid Contents STROBE Outputs Off State Valid Off State † Only 1 bit in 32 should be low in the input data. schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL OF SERIAL OUTPUT VCC VCC Output Input Output GND GND GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.4 V to 7 V On-state Q output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.4 V to 125 V Off-state Q output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.4 V to 180 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.4 V to VCC + 0.4 V Serial output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.4 V to VCC + 0.4 V Q output on-state time duration (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 µs Q output duty cycle (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/200 Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 3) . . . . . . . . 1025 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. Voltage values are with respect to GND. 2. Only one Q output should be on at a time. 3. For operation above 25°C free-air temperature, derate linearly to 656 mW at 70°C at the rate of 8.2 mW/°C. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SLDS034 − DECEMBER 1986 − REVISED JULY 1889 recommended operating conditions Supply voltage, VCC MIN NOM 4 5 Peak on-state Q output voltage, VO(on) High-level input voltage, VIH VCC = 4 V VCC = 6 V Low-level input voltage, VIL VCC = 4 V VCC = 6 V MAX UNIT 6 V 110 V 3.2 V 4.8 0.8 1.2 V Output current, Io (TA = 25°C) 220 mA Clock frequency, fclock 200 kHz 1.5† µs Pulse duration, DATA, twD 5 µs Pulse duration, STROBE, tw(STRB) 2 µs 1 µs 1.2 µs Pulse duration, CLOCK high or low, tw(CLK) Setup time, DATA IN before CLOCK ↓, tsu Hold time, DATA IN after CLOCK↓, th Operating free-air temperature, TA † The minimum clock period is 5 µs. 0 70 °C electrical characteristics, VCC = 5 V, TA = 25°C PARAMETER VOH High-level output voltage TEST CONDITIONS SERIAL OUT IOH = − 0.1 mA IOL= 180 mA Q outputs VOL Low-level output voltage IO(off) IOL Off-state output current Q outputs Low-level output current Q outputs IIH IIL High-level input current VOL = 16 V VI = VCC Low-level input current VI = 0 Ci Input capacitance ICC Supply current SERIAL OUT MIN TYP MAX 6 10 4.5 V IOL= 0.1 mA VOH = 110 V 0.5 1 220 V µA mA All Q outputs off 1 µA −1 µA 15 pF 1 One Q output on UNIT mA 20 40 TYP MAX 0.2 0.2‡ 0.5 µs 0.6 µs 0.35‡ 1 µs 0.1 0.3 µs 0.35 1 µs switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tpd tDHL Propagation delay time, CLOCK to SERIAL OUT CL = 15 pF tDLH tTHL Delay time, low-to-high-level Q output from STROBE or CLOCK inputs Delay time, high-to-low-level Q output from STROBE or CLOCK inputs Transition time, high-to-low-level Q output CL = 150 pF, RL = 470 Ω, Ω See Figures 2 and 3 tTLH Transition time, low-to-high-level Q output ‡ Typical values are for clock Inputs. Typical values from STROBE will be less. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • MIN UNIT SLDS034 − DECEMBER 1986 − REVISED JULY 1889 PARAMETER MEASUREMENT INFORMATION 4V CLOCK 50% 50% 50% 1V tw(CLKH) tw(CLKL) th tsu 4V DATA IN 50% 50% 1V twD Figure 1. Input Timing Voltage Waveforms CLOCK Last Pulse 4V 50% 1V VOH SERIAL OUT 50% VOL tpd tw(STRB) STROBE tDHL Q Output 4V 50% 50% tDLH 90% 10% tDHL 90% 10% tDLH tTLH 90% 10% VOH VOL tTHL Figure 2. Switching Characteristics • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 SLDS034 − DECEMBER 1986 − REVISED JULY 1889 PARAMETER MEASUREMENT INFORMATION 5V VDD = 100 V 150 pF Q1 150 pF Generator (see Note A) 470 Ω DATA IN Q2 470 Ω Generator (see Note A) 150 pF CLK Q31 150 pF Generator (see Note A) STROBE 470 Ω Q32 470 Ω SERIAL OUT GND CL = 15 pF (see Note B) NOTES: A. Input pulses are supplied by generators having the following characteristics: tw = 1.25 µs, PRR ≤ 200 kHz, tr ≤ 30 ns, tf ≤ 30 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 3. Test Circuit 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SLDS034 − DECEMBER 1986 − REVISED JULY 1889 TYPICAL CHARACTERISTICS LOW-LEVEL Q OUTPUT CURRENT vs FREE-AIR TEMPERATURE LOW-LEVEL Q OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 10 500 VCC = 5 V IOL = 180 mA 8 7 6 5 4 ÁÁ ÁÁ ÁÁ 3 400 350 300 250 200 150 ÁÁ ÁÁ 2 1 0 0 10 VCC = 5 V VOL = 16 V 450 − Low-Level Output Current − mA IIoL OL VoL − Low-Level Output Voltage − V V OL 9 20 30 40 50 60 70 TA − Free-Air Temperature − °C 80 100 50 0 0 10 20 30 40 50 60 70 TA − Free-Air Temperature − °C Figure 5 Figure 4 PROPAGATION DELAY TIME, CLOCK TO SERIAL OUT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.5 26 24 µs ttpd pd − Propagation Delay Time − us VCC = 5 V One Q Output Low 25 IICC CC − Supply Current − mA 80 23 22 21 ÁÁ ÁÁ ÁÁ 20 19 18 VCC = 5 V CL = 15 pF 0.4 0.3 0.2 0.1 17 16 0 10 20 30 40 50 60 70 TA − Free-Air Temperature − °C 0 80 0 10 20 30 40 50 60 70 TA − Free-Air Temperature − °C 80 Figure 7 Figure 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 SLDS034 − DECEMBER 1986 − REVISED JULY 1889 TYPICAL CHARACTERISTICS DELAY TIME, HIGH-TO-LOW-LEVEL Q OUTPUT vs FREE-AIR TEMPERATURE DELAY TIME, LOW-TO-HIGH-LEVEL Q OUTPUT vs FREE-AIR TEMPERATURE 0.5 VCC = 5 V CL = 150 pF RL = 470 Ω 0.4 t DLH − Delay Time, Low-to-High Level − µ s t DHL − Delay Time, High-to-Low Level − µ s 0.5 0.3 0.2 0.1 VCC = 5 V CL = 150 pF RL = 470 Ω 0.4 0.3 0.2 0.1 0 0 0 10 20 30 40 50 60 70 0 80 10 TA − Free-Air Temperature − °C 20 t THL THL − Low-to-High-Level Transition Time − us µs uss ttTHL THL − High-to-Low-Level Transition Time − µ VCC = 5 V CL = 150 pF RL = 470 Ω 0.3 0.2 0.1 0 20 30 40 70 80 50 60 70 1.0 VCC = 5 V CL = 150 pF RL = 470 Ω 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 80 0 10 TA − Free-Air Temperature − °C 20 30 40 50 60 70 TA − Free-Air Temperature − °C Figure 10 8 60 TRANSITION TIME, LOW-TO-HIGH-LEVEL Q OUTPUT vs FREE-AIR TEMPERATURE 0.5 10 50 Figure 9 TRANSITION TIME, HIGH-TO-LOW-LEVEL vs FREE-AIR TEMPERATURE 0 40 TA − Free-Air Temperature − °C Figure 8 0.4 30 Figure 11 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 80 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN751506FT OBSOLETE DFP FT 48 TBD Call TI Call TI SN751516FT OBSOLETE DFP FT 48 TBD Call TI Call TI SN751516FT OBSOLETE DFP FT 48 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MDFP001 – OCTOBER 1994 FT (R-PDFP-G48) PLASTIC DUAL FLATPACK 0,45 0,25 0,80 48 0,16 M 25 14,20 13,80 18,00 17,20 0,15 NOM 1 Gage Plane 24 20,20 19,80 0,25 0°– 10° 1,00 0,60 2,00 TYP 2,30 MAX Seating Plane 0,15 0,10 MIN 4040228-2 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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