SN55LBC180 SN65LBC180 SN75LBC180 RSA−16 D−14 N−14 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 LOW-POWER RS-485 LINE DRIVER AND RECEIVER PAIRS FEATURES 1 RSA PACKAGE (TOP VIEW) D OR N PACKAGE (TOP VIEW) 14 2 13 3 12 4 11 5 10 6 7 9 8 VCC VCC A B Z Y NC NC R RE DE 16 15 14 13 1 12 2 11 3 4 10 5 6 7 8 NC − No internal connection Pins 6 and 7 are connected together internally Pins 13 and 14 are connected together internally 9 A B Z Y NC 1 D GND GND NC R RE DE D GND GND NC NC VCC VCC • Designed for High-Speed Multipoint Data Transmission Over Long Cables • Operate With Pulse Durations as Low as 30 ns • Low Supply Current . . . 5 mA Max • Meet or Exceed the Requirements of ANSI Standard RS-485 and ISO 8482:1987(E) • 3-State Outputs for Party-Line Buses • Common-Mode Voltage Range of –7 V to 12 V • Thermal Shutdown Protection Prevents Driver Damage From Bus Contention • Positive and Negative Output Current Limiting • Pin Compatible With the SN75ALS180 2 logic diagram (positive logic) DESCRIPTION 4 DE The SN55LBC180, SN65LBC180 and SN75LBC180 differential driver and receiver pairs are monolithic integrated circuits designed for bidirectional data communication over long cables that take on the characteristics of transmission lines. They are balanced, or differential, voltage mode devices that meet or exceed the requirements of industry standards ANSI RS-485 and ISO 8482:1987(E). These devices are designed using TI's proprietary LinBiCMOS™ with the low-power consumption of CMOS and the precision and robustness of bipolar transistors in the same circuit. D RE R 9 5 10 3 12 2 11 Y Z A B this deviceinfo section is for space between the para and table ORDERING INFORMATION TA PACKAGE PART NUMBER PART MARKING PDIP SN75LBC180N SN75LBC180N 0°C to 70°C SOIC SN75LBC180D 7LB180 QFN SN75LBC180RSA LB180 –40°C to 85°C –55°C to 125°C PDIP SN65LBC180N 65LBC180N SOIC SN65LBC180D 6LB180 QFN SN65LBC180RSA BL180 QFN SN55LBC180RSA SN55LBC180 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1994–2009, Texas Instruments Incorporated SN55LBC180 SN65LBC180 SN75LBC180 SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN55LBC180, SN65LBC180 and SN75LBC180 combine a differential line driver and receiver with 3-state outputs and operate from a single 5-V supply. The driver and receiver have active-high and active-low enables, respectively, which can be externally connected to function as a direction control. The driver differential outputs and the receiver differential inputs are connected to separate terminals for full-duplex operation and are designed to present minimum loading to the bus whether disabled or powered off (VCC = 0). These parts feature a wide common-mode voltage range making them suitable for point-to-point or multipoint data-bus applications. The devices also provide positive and negative output-current limiting and thermal shutdown for protection from line fault conditions. The line driver shuts down at a junction temperature of approximately 172°C. The SN75LBC180 is characterized for operation over the commercial temperature range of 0°C to 70°C. The SN65LBC180 is characterized over the industrial temperature range of –40°C to 85°C. The SN55LBC180 is characterized for operation over the military temperature range of –55°C to 125°C. FUNCTION TABLES (1) DRIVER INPUT D ENABLE DE OUTPUTS H H H L L H L H X L Z Z Y Z RECEIVER DIFFERENTIAL INPUTS A–B ENABLE RE OUTPUT R VID ≥ 0.2 V L H –0.2 V < VID < 0.2 V L ? VID ≤ –0.2 V L L X H Z Open circuit L H (1) 2 H = high level, L = low level, ? = Indeterminate, X = irrelevant, Z = high impedance (off) Submit Documentation Feedback Copyright © 1994–2009, Texas Instruments Incorporated Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 SN55LBC180 SN65LBC180 SN75LBC180 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 ABSOLUTE MAXIMUM RATINGS (1) UNIT (2) VCC Supply voltage range –0.3 to 7 V VBUS Bus voltage range (A, B, Y, Z) (2) –10 to 15 V Voltage range at D, R, DE, RE (2) –0.3 to VCC + 0.5 V Continuous total power dissipation (3) Internally limited Total power dissipation See Dissipation Rating Table Tstg Storage temperature range IO Receiver output current range ESD (1) (2) (3) Electrostatic discharge –65 to 150 °C –50 to 50 mA HBM (Human Body Model) EIA/JESD22-A114 ±4 kV MM (Machine Model) EIA/JESD22-A115 400 V CDM (Charge Device Model) EIA/JESD22-C101 1.5 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature. DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 950 mW 7.6 mW/°C 608 mW 494 mW — N 1150 mW 9.2 mW/°C 736 mW 598 mW — RSA 3333 mW 26.67 mW/°C 2133 mW 1733 mW 400 mW PACKAGE (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage D, DE, and RE VIL Low-level input voltage D, DE, and RE VID Differential input voltage VO, VI, or VIC Voltage at any bus terminal (separately or common mode) IOH High-level output current IOL Low-level output current TA (1) Operating free-air temperature MIN NOM MAX UNIT 4.75 5 5.25 V 2 V (1) 6 V –7 (1) 12 V –6 A, B, Y, or Z V 0.8 Y or Z –60 R –8 Y or Z 60 R 8 SN55LBC180 –55 125 SN65LBC180 –40 85 SN75LBC180 0 70 mA mA °C The algebraic convention where the least positive (more negative) limit is designated minimum, is used in this data sheet for the differential input voltage, voltage at any bus terminal, operating temperature, input threshold voltage, and common-mode output voltage. Copyright © 1994–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 3 SN55LBC180 SN65LBC180 SN75LBC180 SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009................................................................................................................................................... www.ti.com DRIVER SECTION ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIK Input clamp voltage TEST CONDITIONS II = -18 mA RL = 54 Ω, See Figure 1 | VOD | Differential output voltage magnitude (2) RL = 60 Ω, See Figure 2 Δ| VOD | Change in magnitude of differential output voltage (3) VOC MIN TYP (1) MAX UNIT –1.5 V SN55LBC180 1 2.5 5 SN65LBC180 1.1 2.5 5 SN75LBC180 1.5 2.5 5 SN55LBC180 1 2.5 5 SN65LBC180 1.1 2 5 SN75LBC180 1.5 2 See Figure 1 and Figure 2 Common-mode output voltage 1 V 5 ±0.2 V 3 V ±0.2 V ±100 µA ±100 µA µA 2.5 Δ| VOC | Change in magnitude of common-mode output voltage (3) RL = 54 Ω, IO Output current with power off VCC = 0, IOZ High-impedance-state output current VO = –7 V to 12 V IIH High-level input current VI = 2.4 V 100 IIL Low-level input current VI = 0.4 V 100 µA IOS Short-circuit output current –7 V ≤ VO ≤ 12 V ±250 mA ICC Supply current Receiver disabled (1) (2) (3) See Figure 1 VO = –7 V to 12 V Outputs enabled 5 Outputs disabled 3 mA All typical values are at VCC = 5 V and TA = 25°C. The minimum VOD specification may not fully comply with ANSI RS-485 at operating temperatures below 0°C. System designers should take the possibly lower output signal into account in determining the maximum signal-transmission distance. Δ|VOD| and Δ|VOC| are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C PARAMETER td(OD) Differential output delay time tt(OD) Differential output transition time tPZH TEST CONDITIONS MIN TYP MAX 7 12 18 UNIT ns 5 10 RL = 54 Ω, See Figure 3 20 ns Output enable time to high level RL = 110 Ω, See Figure 4 35 ns tPZL Output enable time to low level RL = 110 Ω, See Figure 5 35 ns tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 50 ns tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 35 ns SWITCHING CHARACTERISTICS (SN55LBC180) VCC = 5 V, TA = 25°C PARAMETER td(OD) Differential output delay time tt(OD) Differential output transition time tPZH Output enable time to high level tPHZ Output disable time from high level tPZL Output enable time to low level tPLZ Output disable time from low level 4 Submit Documentation Feedback TEST CONDITIONS RL = 54 Ω, See Figure 3 RL = 110 Ω, See Figure 4 RL = 110 Ω, See Figure 5 MIN TYP MAX UNIT 15 ns 21 ns 32 55 32 20 ns ns Copyright © 1994–2009, Texas Instruments Incorporated Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 SN55LBC180 SN65LBC180 SN75LBC180 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 RECEIVER SECTION ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Positive-going input threshold voltage IO = –8 mA VIT– Negative-going input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ – VIT–) VIK Enable-input clamp voltage II = –18 mA VOH High-level output voltage VID = 200 mV, IOH = –8 mA VOL Low-level output voltage VID = –200 mV, IOL = 8 mA IOZ High-impedance-state output current VO = 0 V to VCC IIH High-level enable-input current VIH = 2.4 V –50 A IIL Low-level enable-input current VIL = 0.4 V –100 µA II ICC Bus input current Supply current 0.2 UNIT VIT+ –0.2 V 45 mV -1.5 3.5 V 4.5 0.3 V 0.5 V ±20 µA VI = 12 V, VCC = 5 V, Other input at 0 V 0.7 1 VI = 12 V, VCC = 0 V, Other input at 0 V 0.8 1 VI = -7 V, VCC = 5 V, Other input at 0 V –0.8 -0.5 VI = -7 V, VCC = 0 V, Other input at 0 V –0.8 –0.5 Driver disabled V Outputs enabled 5 Outputs disabled 3 mA mA SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPHL Propagation delay time, high- to low-level output tPLH Propagation delay time, low- to high-level output tsk(p) Pulse skew (| tPHL – tPLH|) tt Transition time tPZH Output enable time to high level tPZL Output enable time to low level tPHZ Output disable time from high level tPLZ Output disable time from low level VID = –1.5 V to 1.5 V, See Figure 6 MIN TYP MAX 11 22 33 ns 11 22 33 ns 3 6 ns 5 8 ns 35 ns 30 ns 35 ns 30 ns See Figure 7 UNIT SWITCHING CHARACTERISTICS (SN55LBC180) VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHL Propagation delay time, high- to low-level output 26 ns tPLH Propagation delay time, low- to high-level output 23 ns tsk(p) Pulse skew (| tPHL – tPLH|) 3 ns tsk(p)t Transition time 4 ns tPZH Output enable time to high level 30 ns tPHZ Output disable time from high level 26 ns tPZL Output enable time to low level 30 ns tPLZ Output disable time from low level 30 ns Copyright © 1994–2009, Texas Instruments Incorporated VID = –1.5 V to 1.5 V, See Figure 6 See Figure 4 Submit Documentation Feedback Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 5 SN55LBC180 SN65LBC180 SN75LBC180 SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION Y RL 2 D VOD 0 V or 3 V RL 2 DE at 3 V VOC Z Figure 1. Differential and Common-Mode Output Voltages Vtest –7 V < Vtest < 12 V R1 375 Ω Y D RL = 60 Ω 0 V or 3 V VOD Z DE at 3 V R2 375 Ω Vtest Figure 2. Driver VOD Test Circuit 3V Input 1.5 V Y CL = 50 pF (see Note B) Generator (see Note A) RL = 54 Ω 50 Ω 1.5 V 0V td(OD) ≈ 2.5 V td(OD) Output Output 90% 50% 10% 90% 50% 10% Z DE at 3 V tt(OD) TEST CIRCUIT ≈ – 2.5 V tt(OD) VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR > 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Differential Output Delay and Transition Time Voltage Waveforms 6 Submit Documentation Feedback Copyright © 1994–2009, Texas Instruments Incorporated Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 SN55LBC180 SN65LBC180 SN75LBC180 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION (continued) Y D 0 V or 3 V DE 0V 0.5 V tPZH RL = 110 Ω CL = 50 pF (see Note B) 50 Ω 1.5 V 1.5 V Input Output Z Input Generator (see Note A) 3V S1 VOH Output 2.3 V Voff ≈ 0 tPHZ TEST CIRCUIT VOLTAGE WAVEFORMS Figure 4. Driver Test Circuit and Enable and Disable Time Waveforms 5V Y D 0 V or 3 V RL = 110 Ω S1 1.5 V Input 1.5 V 0V Output Z tPZL CL = 50 pF (see Note B) DE Input Generator (see Note A) 3V tPLZ 5V 0.5 V 50 Ω 2.3 V Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS Figure 5. Driver Test Circuit and Enable and Disable Time Voltage Waveforms 3V Input Input Generator (see Note A) R 50 Ω 1.5 V 1.5 V A B 1.5 V tPLH Output tPHL RE CL = 15 pF (see Note B) 0V 0V 90% Output 1.3 V 10% tt TEST CIRCUIT VOH 90% 1.3 V 10% VOL tt VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Propagation Delay Time Voltage Waveforms Copyright © 1994–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 7 SN55LBC180 SN65LBC180 SN75LBC180 SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Output S1 1.5 V A R − 1.5 V 2 kΩ S2 5V B CL = 15 pF (see Note B) RE IN916 or Equivalent (4 places) 5 kΩ Input Generator (see Note A) 50 Ω S3 TEST CIRCUIT 3V Input 1.5 V S1 to − 1.5 V S2 Closed 1.5 V S3 Open 3V S1 to 1.5 V S2 Open S3 Closed Input 0V 0V tPZH tPZL VOH Output 1.5 V 0V ≈ 4.5 V Output 1.5 V VOL 3V Input 1.5 V S1 to 1.5 V S2 Closed S3 Closed 3V Input 1.5 V S1 to − 1.5 V S2 Closed S3 Closed 0V 0V tPHZ tPLZ ≈ 1.3 V VOH Output Output ≈ 1.3 V 0.5 V 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 7. Receiver Output Enable and Disable Times 8 Submit Documentation Feedback Copyright © 1994–2009, Texas Instruments Incorporated Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 SN55LBC180 SN65LBC180 SN75LBC180 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS SCHEMATICS OF INPUTS AND OUTPUTS EQUIVALENT OF D, DE, AND RE INPUTS RECEIVER A INPUT VCC VCC 100 kΩ NOM 18 kΩ NOM 22 kΩ 3 kΩ NOM Input Input 12 kΩ 1.1 kΩ NOM DRIVER OUTPUT RECEIVER B INPUT VCC VCC 18 kΩ NOM TYPICAL OF RECEIVER OUTPUT VCC 3 kΩ NOM Input R Output Output 100 kΩ NOM 12 kΩ 1.1 kΩ NOM Copyright © 1994–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 9 SN55LBC180 SN65LBC180 SN75LBC180 SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009................................................................................................................................................... www.ti.com DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5 VCC = 5 V TA = 25°C 4.5 VCC = 5 V TA = 25°C 4.5 VOL− Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 5 4 3.5 3 2.5 2 1.5 1 0.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0 10 20 30 40 50 60 70 80 90 100 IOH − High-Level Output Current − mA Figure 8. 0 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT 2.4 3.5 2.3 VOD - Driver Output Voltage - V VOD − Differential Output Voltage − V VCC = 5 V TA = 25°C 3 2.5 2 1.5 1 0.5 2.2 2.1 2 1.9 1.8 1.7 1.6 0 10 20 30 40 50 60 70 80 IO − Output Current − mA 90 100 1.5 -60 -40 -20 0 20 40 60 80 100 120 TA - Ambient Temperature - °C Figure 10. 10 120 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 4 0 20 40 60 80 100 IOL − Low-Level Output Current − mA Figure 9. Submit Documentation Feedback Figure 11. Copyright © 1994–2009, Texas Instruments Incorporated Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 SN55LBC180 SN65LBC180 SN75LBC180 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 20 80 18 60 RL = 54 Ω IOL 40 16 I O − Output Current − mA Driver Output Voltage - ns DRIVER DIFFERENTIAL DELAY TIMES vs FREE-AIR TEMPERATURE 14 12 10 8 20 0 −20 −40 IOH −60 6 -60 -40 −80 -20 0 20 40 60 80 100 120 TA - Ambient Temperature - °C 0 2 3 4 5 6 VCC − Supply Voltage − V Figure 12. Figure 13. RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 6 1 VID = 200 mV VCC = 5 V TA = 25°C VID = − 200 mV 0.9 5 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 1 4 3 2 1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0 −10 − 20 − 30 − 40 IOH − High-Level Output Current − mA − 50 0 5 10 15 20 25 30 35 IOL − Low-Level Output Current − mA Figure 14. Copyright © 1994–2009, Texas Instruments Incorporated 40 Figure 15. Submit Documentation Feedback Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 11 SN55LBC180 SN65LBC180 SN75LBC180 SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009................................................................................................................................................... www.ti.com RECEIVER OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE AVERAGE SUPPLY CURRENT vs FREQUENCY 60 I CC − Average Supply Current − mA 6 VO − Output Voltage − V 5 VIC = 12 V 4 VIC = 0 V 3 2 VIC = −7 V 1 55 50 45 TA = 25°C VCC = 5 V DRVR and RCVR Enabled Driver Load = Receiver Inputs Receiver Load = 50 pF 40 35 30 25 20 15 10 5 0 − 80 − 60 − 40 − 20 0 20 40 60 0 10 k 80 100 k VID − Differential Input Voltage − mV 0.8 I I − Bus Input Current − mA 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 Figure 16. Figure 17. RECEIVER BUS INPUT CURRENT vs INPUT VOLTAGE (COMPLEMENTARY INPUT AT 0 V) RECEIVER PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ −1 −8 The shaded region of this graph represents more than 1 unit load per RS-485. −6 −4 −2 0 2 4 6 VI − Input Voltage − V 8 10 12 29 28 27 26 25 24 23 22 21 20 -60 -40 -20 0 20 40 60 80 100 120 TA - Ambient Temperature - °C Figure 18. 12 Submit Documentation Feedback 100 M 30 TA = 25°C VCC = 5 V Receiver Output Delay - ns 1 1M 10 M f − Frequency − Hz Figure 19. Copyright © 1994–2009, Texas Instruments Incorporated Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 SN55LBC180 SN65LBC180 SN75LBC180 www.ti.com................................................................................................................................................... SLLS174G – FEBRUARY 1994 – REVISED APRIL 2009 APPLICATION INFORMATION Master Node Slave Node Slave Node Slave Node Figure 20. Full Duplex Application Circuit Copyright © 1994–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN55LBC180 SN65LBC180 SN75LBC180 13 PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN55LBC180RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN55LBC180RSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LBC180D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC180N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65LBC180NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65LBC180RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LBC180RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LBC180RSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LBC180RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LBC180D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC180N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75LBC180NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75LBC180RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LBC180RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LBC180RSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LBC180RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) Lead/Ball Finish MSL Peak Temp (3) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2009 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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OTHER QUALIFIED VERSIONS OF SN55LBC180, SN65LBC180, SN75LBC180 : • Automotive: SN65LBC180-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN55LBC180RSAR Package Package Pins Type Drawing QFN RSA 16 SN55LBC180RSAT QFN RSA SN65LBC180DR SOIC D SN65LBC180RSAR QFN SN65LBC180RSAT QFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 SN75LBC180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN75LBC180RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 SN75LBC180RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN55LBC180RSAR QFN RSA 16 3000 367.0 367.0 35.0 SN55LBC180RSAT QFN RSA 16 250 210.0 185.0 35.0 SN65LBC180DR SOIC D 14 2500 333.2 345.9 28.6 SN65LBC180RSAR QFN RSA 16 3000 367.0 367.0 35.0 SN65LBC180RSAT QFN RSA 16 250 210.0 185.0 35.0 SN75LBC180DR SOIC D 14 2500 333.2 345.9 28.6 SN75LBC180RSAR QFN RSA 16 3000 367.0 367.0 35.0 SN75LBC180RSAT QFN RSA 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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