SN75LVCP422 www.ti.com ................................................................................................................................................................................................... SLLS972 – MARCH 2009 Two Channel SATA 3-Gbps Redriver • FEATURES 1 • • • • • • • • Data Rates up to 3 Gbps SATA Gen 2.6, eSATA Compliant SATA Hot-Plug Capable Supports Common-Mode Biasing for OOB Signaling with Fast Turn-On Channel Selectable Pre-Emphasis Fixed Receiver Equalization Integrated Termination Low Power – <200 mW Typ – <5 mW in Sleep Mode – 15% Typ Lower Power in Auto Low Power Mode • • • Excellent Jitter and Loss Compensation Capability to Over 20 Inch FR4 Trace High Protection Against ESD Transient – HBM: 8000V – CDM: 1500V – MM: 200V 20-Pin SSOP Package Pin Compatible with PI2EQX3211A and PI2EQX3211B APPLICATIONS • Notebooks, Desktops, Docking Stations, Servers, and Workstations DESCRIPTION The SN75LVCP422 is a dual channel, single lane SATA redriver and signal conditioner supporting data rates up to 3 Gbps. The device complies with SATA specification revision 2.6 and eSATA requirements. The SN75LVCP422 operates from a single 3.3-V supply. Integrated 100-Ω line termination and self-biasing make the device suitable for AC coupling. The inputs incorporate an OOB detector, which automatically turns the differential outputs off while maintaining a stable output common-mode voltage compliant to SATA link. The device is also designed to handle SSC transmission per SATA spec. The SN75LVCP422 handles interconnect losses at both its input and output. The built-in transmitter pre-emphasis feature is capable of applying 0 dB or 2.5 dB of relative amplification at higher frequencies to counter the expected interconnect loss. On the receive side the device applies a fixed equalization of 7 dB to boost input frequencies near 1.5 GHz. Collectively, the input equalization and output pre-emphasis features of the device work to fully restore SATA signal integrity over extended cable and backplane pathways. The device is hot-plug capable(1) preventing device damage under device hot-insertion such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal. (1) Requires use of AC coupling capacitors at differential inputs and outputs. ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75LVCP422DB LVCP422 20-Pin SSOP Tube SN75LVCP422DBR LVCP422 20-Pin SSOP Reel (large) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN75LVCP422 SLLS972 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION PC Motherboard ICH HDD R R = SN75LVCP422 eSATA connector SATA Cable (2m) In Notebook and Desktop Motherboard HDD Dock Connector R = SN75LVCP422 ICH Notebook R eSATA connector SATA Cable (2m) Dock In Notebook Dock 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 SN75LVCP422 www.ti.com ................................................................................................................................................................................................... SLLS972 – MARCH 2009 GND [5, 9, 12, 16] VBB = 1.6 V typ RT TX_OP [18] RT Driver Equalizer RX_0P [3] TX_ON [17] OOB Detect RX_0N [4] VBB SN75LVCP422 RT RX_1N [13] Driver Equalizer TX_1N [8] RX_1P [14] OOB Detect TX_1P [7] RT CTRL D1 [10] D0 [1] EN [20] VCC [2, 6, 15, 19] Figure 1. Data Flow Block Diagram Table 1. Control Logic EN D0 D1 FUNCTION 0 X X Low power mode 1 0 0 Normal SATA output (default state); CH 0 and CH 1 → 0 dB 1 1 0 CH 0 → 2.5 dB pre-emphasis; CH 1 → 0 dB 1 0 1 CH 1→ 2.5 dB pre-emphasis; CH 0 → 0 dB 1 1 1 CH 0 and CH 1 → 2.5 dB pre-emphasis Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 3 SN75LVCP422 SLLS972 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com PIN ASSIGNMENT DB PACKAGE TOP VIEW 1 20 EN VCC 2 19 VCC RX_0P 3 18 TX_0P RX_0N 4 17 TX_0N GND 5 16 GND VCC 6 15 VCC TX_1P 7 14 RX_1P TX_1N 8 13 RX_1N GND 9 12 GND 10 11 NC D1 SN75LVCP422DB D0 TERMINAL FUNCTIONS PIN NAME PIN NAME 1 D0 (1) Pre-emphasis _0 11 NC 2 VCC Power 12 GND 4 DESCRIPTION No connect Ground 3 RX_0P Input 0, non-inverting 13 RX_1N Input 1, non-inverting 4 RX_0N Input 0, inverting 14 RX_1P Input 1, inverting 5 GND Ground 15 VCC Power 6 VCC Power 16 GND Ground 7 TX_1P Output 1, inverting 17 TX_0N Output 0, inverting 8 TX_1N Output 1, non-inverting 18 TX_0P Output 0, non-inverting 9 GND Ground 19 VCC 20 (2) 10 (1) (2) DESCRIPTION D1 (1) Pre-emphasis_1 EN Power Enable D0 and D1 are tied to VCC via an internal PU resistor. EN tied to VCC via an internal PU resistor. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 SN75LVCP422 www.ti.com ................................................................................................................................................................................................... SLLS972 – MARCH 2009 TYPICAL DEVICE IMPLEMENTATION 3.3V VCC 10nF 10nF 10nF TX_0P RX_0N GND TX_0N GND VCC VCC TX_1P RX_1P TX_1N RX_1N D1 10 GPIO 10nF VCC RX_0P GND 20 10nF 10nF GND eSATA Connector SATA Host 10nF EN 0.01uF D0 0.1uF 1.0uF 1 10nF NC 11 SN75LVCP422DB Note: 1) Place supply caps close to device pin 2) EN can be left open or tied to supply when no external control is implem ented 3) Output pre-emphasis (D1, D0) is shown enabled . Setting will depend on device placem ent relative to eSATA connector DETAILED DESCRIPTION INPUT EQUALIZATION Each differential input of the SN75LVCP422 has 7 dB of fixed equalization in its front stage. The equalization amplifies high frequency signals to correct for loss from the transmission channel. The input equalizer is designed to recover signal even when no eye is present at the receiver and affectively supports FR4 trace at the input anywhere from <4 inches to 20 inches or <10 cm to >50 cm. OUTPUT PRE-EMPHASIS The SN75LVCP422 provides single step pre-emphasis from 0 dB to 2.5 dB at each of its differential outputs. Pre-emphasis is controlled independently for each channel and is set by the control pins D0 and D1 as shown in Table 1. The pre-emphasis duration is 0.5 UI or 133 ps (typ) at SATA 3-Gbps speed. LOW POWER MODE Two low power modes are supported by the SN75LVCP422: • Sleep Mode (triggered by EN pin, EN = 0 V) – Low power mode is controlled by the enable (EN) pin. In its default state this pin is internally pulled high. Pulling this pin low puts the device in sleep mode within 2 us (max). In this mode all active components of the device are driven to their quiescent level and differential outputs are driven to Hi-Z (open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode to normal operation requires a maximum latency of 20 µs. • Auto Low Power Mode (triggered when a given channel is in electrical idle state, EN = VCC) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 5 SN75LVCP422 SLLS972 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com – The device enters and exits low power mode by actively monitoring the input signal (VIDp-p) level on each of its channels independently. When the input signal on either or both channels is in the electrical idle state, i.e. VIDp-p <50 mV, and stays in this state for > 3 µs, the associated channel(s) enters the low power state. In this state, the output of the associated channel(s) is driven to VCM, and the device selectively shuts off some circuitry to lower power by up to 20% of its normal operating power. Exit time from auto low power mode is less than 50 ns. – As an example, if under normal operating conditions the device is consuming typical power of 200 mW, when the device enters this mode, i.e. the condition for auto-low power mode is met, power consumption can drop down to 160 mW. The device enters normal operation within 50 ns of signal activity detection. OUT-OF-BAND (OOB) SUPPORT The squelch detector circuit within the device enables full detection of OOB signaling as specified in SATA specification 2.6. Differential signal amplitude at the receiver input of 50 mVp-p or less is not detected as an activity and hence is not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as an activity and therefore passed to the output indicating activity. Squelch circuit on/off time is 5 ns maximum. While in squelch mode outputs are held to VCM. DEVICE POWER The SN75LVCL412 is designed to operate from a single 3.3-V supply. Always practice proper power supply sequencing procedures. Apply VCC first before any input signals are applied to the device. The power down sequence is in reverse order. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range (2) VCC Voltage range Differential I/O Control I/O Electrostatic discharge V V ±8000 V ±1500 V ±200 V Machine model (5) (1) (2) (3) (4) (5) V –0.5 to 4 (4) Continuous power dissipation UNIT –0.5 to VCC + 0.5 Human body model (3) Charged-device model VALUE –0.5 to 6 See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. DISSIPATION RATINGS PACKAGE 20-pin SSOP (DB) (1) 6 PCB JEDEC STANDARD TA ≤ 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING Low-K 952 mW 9.52 mW/°C 381 mW High-K 1149 mW 11.49 mW/°C 460 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 SN75LVCP422 www.ti.com ................................................................................................................................................................................................... SLLS972 – MARCH 2009 THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX (1) TYP UNIT RθJB Junction-to-board thermal resistance 58 °C/W RθJC Junction-to-case thermal resistance 65 °C/W PD Device power dissipation D0, D1, EN = 3.3 V, K28.5 pattern at 3 Gbps, VID = 700 mVp-p, VCC = 3.6 V 300 mW PSD Device power dissipation, under low power EN = 0 V, K28.5 pattern at 3 Gbps, VID = 700 mVp-p, VCC = 3.6 V 5 mW (1) The maximum rating is simulated under 3.6-V VCC. RECOMMENDED OPERATING CONDITIONS with typical values measured at VCC = 3.3 V, TA = 25°C; all temperature limits are assured by design PARAMETER VCC Supply voltage CCOUPLING Coupling capacitor TA Operating free-air temperature CONDITIONS MIN TYP MAX 3 3.3 3.6 12 0 UNITS V nF 85 °C ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNITS 55 77 mA 1 mA DEVICE PARAMETERS ICC Supply current, active mode EN, D0, D1 in default state, K28.5 pattern at 3 Gbps, VID = 700 mVp-p, VCC = 3.3 V ICCSDWN Shutdown current EN = 0 V ICC-LP Supply current in auto low power mode Low power mode activated 50 Maximum data rate mA 3.0 300 Gbps tPDelay Propagation delay Measured using K28.5 pattern, See Figure 4 500 ps tENB Device enable time ENB = L → H 20 µs tDIS Device disable time ENB = H → L 2 µs AutoLPENTRY Auto low power entry time Electrical idle at input, see Figure 7 AutoLPEXIT Auto low power exit time After first signal activity, see Figure 7 VOOB Input OOB threshold See Figure 5 tOOB1 OOB mode enter See Figure 5 5 ns tOOB2 OOB mode exit See Figure 5 5 ns µs 6 45 50 100 ns 150 mVp-p CONTROL LOGIC VIH High-level input voltage 1.4 V VIL Low-level input voltage VINHYS Input hysteresis IIH High-level input current 10 µA IIL Low-level input current 10 µA 115 Ω 0.5 100 V mV RECEIVER AC/DC ZDiffRX Differential input impedance 85 ZSERX Single-ended input impedance 40 VCMRX Common-mode voltage 100 Ω 1.6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 V 7 SN75LVCP422 SLLS972 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER RLDiffRX Differential mode return loss RLCMRX Common-mode return loss CONDITIONS MIN f = 150 MHz – 300 MHz 18 f = 300 MHz – 600 MHz 14 f = 600 MHz – 1.2 GHz 10 f = 1.2 GHz – 2.4 GHz 8 f = 2.4 GHz – 3.0 GHz 3 f = 150 MHz – 300 MHz 5 f = 300 MHz – 600 MHz 5 f = 600 MHz – 1.2 GHz 2 f = 1.2 GHz – 2.4 GHz 1 f = 2.4 GHz – 3.0 GHz TYP MAX UNITS dB dB 1 VDiffRX Differential input voltage PP f = 150 MHz – 300 MHz 200 IBRX Impedance balance f = 150 MHz – 300 MHz 30 f = 300 MHz – 600 MHz 30 f = 600 MHz – 1.2 GHz 20 f = 1.2 GHz – 2.4 GHz 10 f = 2.4 GHz – 3.0 GHz 2000 mV/ppd dB 4 T20-80RX Rise/fall time Rise times and fall times measured between 20% and 80% of the signal TskewRX Differential skew Difference between the single-ended mid-point of the RX+ signal rising/falling edge and the single-ended mid-point of the RX– signal falling/rising edge 67 136 ps 50 ps 115 Ω TRANSMITTER AC/DC ZDiffTX Pair differential Impedance 85 ZSETX Single-ended input impedance 40 Ω RLDiffTX Differential mode return loss f = 150 MHz – 300 MHz 14 dB f = 300 MHz – 600 MHz 8 f = 600 MHz – 1.2 GHz 6 f = 1.2 GHz – 2.4 GHz 6 f = 2.4 GHz – 3.0 GHz 3 f = 150 MHz – 300 MHz 5 f = 300 MHz – 600 MHz 5 f = 600 MHz – 1.2 GHz 2 f = 1.2 GHz – 2.4 GHz 1 RLCMTX Common-mode return loss f = 2.4 GHz – 3.0 GHz IBTX Impedance balance dB 1 f = 150 MHz – 300 MHz 30 f = 300 MHz – 600 MHz 20 f = 600 MHz – 1.2 GHz 10 f = 1.2 GHz – 2.4 GHz 10 f = 2.4 GHz – 3.0 GHz 4 dB DiffVppTX Differential output voltage PP f = 1.5 GHz, D0/D1 = 0, Refer to Figure 2 for test setup 400 585 700 mVpp DiffVppTX_PE Differential output voltage PP f = 1.5 GHz, D0/D1 = 1, Refer to Figure 2 for test setup 600 790 965 mVpp Output pre-emphasis At 1.5 GHz (when enabled) 2.5 VCMTX Common-mode voltage VCMTX_AC AC CM voltage Maximum amount of AC CM signal at TX T20-80TX Rise/fall time Rise times and fall times measured between 20% and 80% of the signal, D1/D0 = 0 V 8 dB 1.97 Submit Documentation Feedback 67 V 20 50 mVpp 83 136 ps Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 SN75LVCP422 www.ti.com ................................................................................................................................................................................................... SLLS972 – MARCH 2009 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TskewTX CONDITIONS Differential skew MIN Difference between the single-ended mid-point of the TX+ signal rising/falling edge and the single-ended mid-point of the TX– signal falling/rising edge TYP MAX 7 20 UNITS ps 30 67 ps-pp JITTER (with pre-emphasis disabled; measured at device pin + 2" loadboard trace) Total jitter (1) TJTX DJTX Deterministic jitter RJTX Random jitter (1) UI = 333 ps, +K28.5 control character; D1/D0 = 0 V (1) UI = 333 ps, +K28.5 control character; D1/D0 = 0 V 10 33 ps-pp UI = 333 ps, +K28.7 control character; D1/D0 = 0 V 1.7 2.0 ps-rms 60 100 ps-pp JITTER (with pre-emphasis enabled; measured as shown in Figure 2) Total jitter (1) TJTX DJTX Deterministic jitter RJTX Random jitter (1) (1) UI = 333 ps, +K28.5 control character; D1/D0 = VCC (1) UI = 333 ps, +K28.5 control character; D1/D0 = VCC 33 67 ps-pp UI = 333 ps, +K28.7 control character; D1/D0 = VCC 1.7 2.0 ps-rms TJ = (14.1×RJSD + DJ) where RJSD is one standard deviation value of RJ Gaussian distribution. TJ measurement is at the SATA connector and includes jitter generated at the package connection on the printed circuit board and at the board interconnect. Ji tter Measurement Point Jitter Measurement Setup *Signal Source 10" FR4 6" FR4 *Signal Source LVCP422 Jitter Measurement Point *Source Ji tte r Mea sure me nts (ps) Total Jitt er Determinis tic Jitt er 32pp 8pp Random Jit ter 1.7rms Figure 2. Output Jitter Measurement Test Setup Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 9 SN75LVCP422 SLLS972 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com Suggested Trace Length Using LVCP422 in PC MB and PC Dock A Redriver SATA Host PC MB B Suggested Trace Lengths eSATA connector PC MB B C A TYP* (inch) MAX* (inch) 4 to 16 18 2 to 4 6 6 to 20 24 C Redriver on PC Motherboard A B1 SATA Host Redriver PC MB eSATA connector DOCK C B2 Suggested Trace Lengths DOCK TYP* (inch) MAX* (inch) B = (B1+B2) 8 to 14 16 C 2 to 4 6 A 10 to 18 22 Redriver on Dock Board Note*: Trace lengths are suggested values based on TI lab measurements (taken with output pre-emphasis enabled on both channels) to meet SATA loss and jitter spec. Actual trace length supported by LVCP422 may be more or less than suggested values and will depend on board layout, number of connectors used in the SATA signal path, and SATA host and esata connector design. Figure 3. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 SN75LVCP422 www.ti.com ................................................................................................................................................................................................... SLLS972 – MARCH 2009 IN tPDelay tPDelay OUT Figure 4. Propagation Delay Timing Diagram IN+ Vcm 50 mV INtOOB2 tOOB1 OUT+ Vcm OUT- Figure 5. OOB Enter and Exit Timing 1-bit tDE 2.5 dB 1 to N bits 1-bit 1 to N bits 0dB Vcm DiffVPPTX DiffVPPTX_PE 0dB tDE 2.5 dB Figure 6. TX Differential Output with 2.5 dB Pre-Emphasis Step Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 11 SN75LVCP422 SLLS972 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com RX_0,1P VCMRX RX_0,1N tOOB1 AutoLPEXIT TX_0,1P VCMT X TX_0,1N AutoLPENT RY Power Saving Mode Figure 7. Auto Low Power Mode Timing 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP422 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN75LVCP422DB ACTIVE SSOP DB 20 SN75LVCP422DBR ACTIVE SSOP DB 20 70 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVCP422DBR Package Package Pins Type Drawing SSOP DB 20 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 7.5 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Mar-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVCP422DBR SSOP DB 20 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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