SSM630GP N-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS 200V R DS(ON) 400mΩ ID 9A DESCRIPTION The SSM630GP achieves fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. Pb-free; RoHS-compliant TO-220 The SSM630GP is in TO-220 for through-hole mounting where a small footprint is required on the board, and/or an external heatsink is to be attached. G D These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. S TO-220 (suffix P) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value VDS Drain-source voltage 200 V VGS Gate-source voltage ±30 V ID Continuous drain current, TC = 25°C 9 A 5.7 A TC = 100°C 1 IDM Pulsed drain current PD Total power dissipation, TC = 25°C Linear derating factor 3 Units 36 A 74 W 0.59 W/°C 240 mJ EAS Single pulse avalanche energy IAR Avalanche current 9 A EAR Repetitive avalanche energy 7 mJ TSTG Storage temperature range -55 to 150 °C TJ Operating junction temperature range -55 to 150 °C THERMAL CHARACTERISTICS Symbol Parameter Value Units RΘ JC Maximum thermal resistance, junction-case 1.7 °C/W RΘ JA Maximum thermal resistance, junction-ambient 62 °C/W Notes: 1. Pulse width must be limited to avoid exceeding the safe operating area. 2. Pulse width <300us, duty cycle <2%. 3. Starting Tj = 25°C, VDD=50V , L=4.5mH , RG=25Ω , IAS=9A. 8/22/2006 Rev.3.1 www.SiliconStandard.com 1 of 7 SSM630GP ELECTRICAL CHARACTERISTICS Symbol (at Tj = 25°C, unless otherwise specified) Parameter Test Conditions Min. Typ. Max. Units 200 - - V - 0.248 - V/°C BVDSS Drain-source breakdown voltage VGS=0V, ID=250uA ∆ BV DSS/∆ Tj Breakdown voltage temperature coefficient Reference to 25°C, ID=1mA RDS(ON) Static drain-source on-resistance VGS=10V, ID=5A - - 400 mΩ VGS(th) Gate threshold voltage VDS=VGS, ID=250uA 2 - 4 V gfs Forward transconductance VDS=10V, ID=5A - 40 - S IDSS Drain-source leakage current VDS=200V, VGS=0V - - 10 uA VDS=160V ,VGS=0V, Tj = 150°C - - 25 uA VGS=±30V - - ±100 nA ID=9A - 25 - nC IGSS Gate-source leakage current 2 Qg Total gate charge Qgs Gate-source charge VDS=160V - 3.6 - nC Qgd Gate-drain ("Miller") charge VGS=10V - 14 - nC VDS=100V - 8 - ns 2 td(on) Turn-on delay time tr Rise time ID=9A - 26 - ns td(off) Turn-off delay time RG=10Ω , VGS=10V - 34 - ns tf Fall time RD=11Ω - 22 - ns Ciss Input capacitance VGS=0V - 515 - pF Coss Output capacitance VDS=25V - 90 - pF Crss Reverse transfer capacitance f=1.0MHz - 40 - pF Min. Typ. IS= 9A, VGS=0V - - 1.3 V VD=VG=0V , VS=1.3V - - 36 A Source-Drain Diode Symbol Parameter Test Conditions 2 VSD Forward voltage IS Continuous source current (body diode) I SM Pulsed source current (body diode)1 - - Max. Units 9 A Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 8/22/2006 Rev.3.1 www.SiliconStandard.com 2 of 7 SSM630GP 10 V G =10V T C =25 o C 14 V G =10V V G =8.0V V G =8.0V V G =7.0V 8 ID , Drain Current (A) 12 ID , Drain Current (A) T C =150 o C 10 V G =6.0V 8 6 V G =7.0V V G =6.0V 6 4 V G =5.0V 4 2 V G =5.0V V G =4.0V 2 V G =4.0V 0 0 0 2 4 6 8 10 12 0 14 2 4 6 8 10 12 14 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1.2 3 I D =5A V G =10V 2.5 Normalized R DS(ON) Normalized BVDSS (V) 1.1 1 2 1.5 1 0.9 0.5 0.8 0 -50 0 50 100 150 -50 0 T j , Junction Temperature ( o C ) Fig 3. Normalized BVDSS vs. Junction Temperature 8/22/2006 Rev.3.1 50 100 150 T j , Junction Temperature ( o C) Fig 4. Normalized On-Resistance vs. Junction Temperature www.SiliconStandard.com 3 of 7 SSM630GP 10 80 8 6 PD (W) ID , Drain Current (A) 60 40 4 20 2 0 0 25 50 75 100 125 0 150 50 100 150 T c , Case Temperature ( o C) Tc , Case Temperature ( o C) Fig 5. Maximum Drain Current vs. Case Temperature Fig 6. Typical Power Dissipation 1 Normalized Thermal Response (R thjc) 100 10us 10 ID (A) 100us 1ms 10ms 1 100ms DUTY=0.5 0.2 0.1 0.1 0.05 PDM 0.02 t SINGLE PULSE T 0.01 Duty factor = t/T Peak Tj = P DM x Rthjc + TC o T c =25 C Single Pulse 0.01 0 1 10 100 1000 0.00001 0.0001 V DS (V) 0.01 0.1 1 10 t , Pulse Width (s) Fig 7. Maximum Safe Operating Area 8/22/2006 Rev.3.1 0.001 Fig 8. Effective Transient Thermal Impedance www.SiliconStandard.com 4 of 7 SSM630GP f=1.0MHz 10000 16 I D =9A V DS =80V 12 V DS =120V Ciss V DS =160V 10 C (pF) VGS , Gate to Source Voltage (V) 14 8 100 Coss 6 Crss 4 2 0 1 0 5 10 15 20 25 30 35 1 11 21 31 V DS (V) Q G , Total Gate Charge (nC) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100.00 4 10.00 3.5 T j =150 o C VGS(th) (V) IS (A) T j =25 o C 1.00 0.10 3 2.5 2 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 -50 0 Fig 11. Forward Characteristic of Reverse Diode 8/22/2006 Rev.3.1 50 100 150 T j Junction Temperayure ( o C) V SD (V) Fig 12. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 5 of 7 SSM630GP VDS 90% RD VDS D RG TO THE OSCILLOSCOPE 0.5x RATED VDS G + 10% VGS S 10 V VGS - td(on) Fig 13. Switching Time Circuit tr td(off) tf Fig 14. Switching Time Waveform VG VDS 10V 0.8 x RATED VDS G S QG TO THE OSCILLOSCOPE D QGS QGD VGS + 1~ 3 mA IG ID Charge Fig 15. Gate Charge Circuit 8/22/2006 Rev.3.1 Q Fig 16. Gate Charge Waveform www.SiliconStandard.com 6 of 7 SSM630GP PHYSICAL DIMENSIONS - TO-220 E A Millimeters SYMBOLS φ L2 L5 c1 D L4 b1 L3 L c b MIN NOM MAX A 4.25 4.48 4.70 b b1 c c1 0.65 0.80 0.90 1.15 1.38 1.60 0.40 0.50 0.60 1.00 1.20 1.40 E 9.70 10.00 10.40 e ---- 2.54 ---- L 12.70 13.60 14.50 L1 2.60 2.80 3.00 L2 1.00 1.40 1.80 L3 2.6 3.10 3.6 L4 14.70 15.50 16 L5 6.30 6.50 6.70 φ 3.50 3.60 3.70 D 8.40 8.90 9.40 L1 1. All dimensions are in millimeters. 2. Dimensions do not include mold protrusions. e PART MARKING - TO-220 PACKING: Moisture sensitivity level MSL3 1000pcs in tubes packed inside a moisture barrier bag (MBB). 630GP YWWSSS PART NUMBER: 630GP = SSM630GP DATE/LOT CODE: Y = last digit of the year WW = work week (01 -> 52) SSS = lot code sequence Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 8/22/2006 Rev.3.1 www.SiliconStandard.com 7 of 7