SITRONIX ST7669

ST
Sitronix
ST7669
262K 132x162 Color Dot Matrix LCD Controller/Driver
1 INTRODUCTION
The ST7669 is a driver & controller LSI for 262K color graphic dot-matrix liquid crystal display systems. It generates 396
Segment and 162 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral
Interface (SPI) or 8-bit/16-bit/18-bit parallel display data and stores in an on-chip display data RAM. It performs display
data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it
contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest
components.
2 FEATURES
♦ 3-line (9-bits) or 4-line( 8-bit) serial interface
Driver Output Circuits
On-chip Low Power Analog Circuit
♦ 396 segment outputs / 162 common outputs
♦ On-chip oscillator circuit
Applicable Duty Ratios
♦ Voltage converter (x1, x2, x3, x4, x5, x6, x7, x8) with
♦ Various partial display
♦ Partial window moving & data scrolling
internal booster capacitors.
♦ Extremely Few Outsider Compoment. (Required
Gray-Scale Display
♦ 4FRC & 31 PWM function circuit to display 64
gray-scale display
outsider components: Three Capacitors)
♦ On-chip Voltage Regulator
♦ On-chip electronic contrast control function
♦ Support 8 color mode (Idle mode)
♦ Voltage follower(LCD bias: 1/5,1/7,1/9,1/10,/11,1/12, 1/13, 1/14)
On-chip Display Data RAM
Operating Voltage Range
♦ Capacity: 132 x 162 x 18 =384,912 bits
♦ Supply Digital Voltage (VDD): 1.65 to 3.0V
Color support by Inteface
♦ Supply Analog Voltage (VDD2, VDD3, VDD4, VDD5): 2.4 to 3.3V
♦ 256 color mode(RGB)=(332) mode (via LUT)
♦ LCD driving voltage (VOP = V0 - VSS): Max: 18V
♦ 4K colors (RGB)=(444) mode (via LUT)
LCD Driving Voltage (OTP)
♦ 65K colors (RGB)=(565) mode
♦ Contrast Adjustment Value is stored in the Built-In
♦ 262K colors (RGB)=(666) mode
OTP-ROM for better display quility.
♦ Truncated 16M colors (RGB)=(888) mode
LCD Driving setting suggestion
Microprocessor Interface
♦ Vop=16.52, Bias=1/10
♦ 8/16/18-bit parallel bi-directional interface with
Package Type
6800-series or 8080-series
ST7669
♦ Application for COG
6800 , 8080 ,4-Line , 3-Line interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.3a
1/216
09/26/2007
ST7669
207 COM 9
206 TRBI
205 TRBO
234 TRUO
233 TRUI
232 COM 59
231 COM 57
3 Pad Arrangement (COG)
Chip Size :
14030 um x 970 um
Bump Pitch :
PAD 1 ~ 30, 31 ~ 35 pitch=27um(min, com/seg)
PAD 200 ~ 204, 205 ~ 737 pitch=27um(min, com/seg)
PAD 36 ~ 199 pitch=80um (I/O)
PAD 87,88 pitch= 79.72um(I/O)
Bump Size :
PAD 1 ~ 35 , PAD 200 ~ 737
Bump width=14um(min, com/seg)
Bump space=13um(min, com/seg)
Bump length=128um(min, com/seg)
Bump area=1800um^2(com/seg)
PAD 36 ~86,89~199(except 87,88)
Bump width=65um(I/O)
Bump space=15um(I/O)
Bump length=63um(I/O)
Bump area=4095um^2
PAD 87,88
Bump width=65um(I/O)
Bump space=14.72um(I/O)
Bump length=63um(I/O)
Bump area=4095um^2
Bump Height : 15 um
Chip Thickness : 400 um
Aligment mark
Ver 1.3a
27 COM 10
28 COM8
29 TLBI
30 TLBO
1 T LUO
2 TLUI
3 COM58
4 COM56
The center of alignment mark: see bellow Table
2/216
3/2/2009
ST7669
4 Pad Center Coordinates
PA
34
COM0
-6668.45 -367.71
35
TGI
-6608.30 -367.71
36
DUMMY
-6491.97 -394.50
NAME
X
Y
1
TLUO
-6897.71
421.50
37
DUMMY
-6411.97 -394.50
2
TLUI
-6897.71
394.50
38
DUMMY
-6331.97 -394.50
3
COM58
-6897.71
337.50
39
VSS
-6251.97 -394.50
4
COM56
-6897.71
310.50
40
VPP
-6171.97 -394.50
5
COM54
-6897.71
283.50
41
VPP
-6091.97 -394.50
6
COM52
-6897.71
256.50
42
VPP
-6011.97 -394.50
7
COM50
-6897.71
229.50
43
VPP
-5931.97 -394.50
8
COM48
-6897.71
202.50
44
DUMMY
-5851.97 -394.50
9
COM46
-6897.71
175.50
45
DUMMY
-5771.97 -394.50
10
COM44
-6897.71
148.50
46
DUMMY
-5691.97 -394.50
11
COM42
-6897.71
121.50
47
DUMMY
-5611.97 -394.50
12
COM40
-6897.71
94.50
48
DUMMY
-5531.97 -394.50
13
COM38
-6897.71
67.50
49
DUMMY
-5451.97 -394.50
14
COM36
-6897.71
40.50
50
DUMMY
-5371.97 -394.50
15
COM34
-6897.71
13.50
51
DUMMY
-5291.97 -394.50
16
COM32
-6897.71
-13.50
52
DUMMY
-5211.97 -394.50
17
COM30
-6897.71
-40.50
53
DUMMY
-5131.97 -394.50
18
COM28
-6897.71
-67.50
54
DUMMY
-5051.97 -394.50
19
COM26
-6897.71
-94.50
55
DUMMY
-4971.97 -394.50
20
COM24
-6897.71 -121.50
56
DUMMY
-4891.97 -394.50
21
COM22
-6897.71 -148.50
57
DUMMY
-4811.97 -394.50
22
COM20
-6897.71 -175.50
58
DUMMY
-4731.97 -394.50
23
COM18
-6897.71 -202.50
59
DUMMY
-4651.97 -394.50
24
COM16
-6897.71 -229.50
60
DUMMY
-4571.97 -394.50
25
COM14
-6897.71 -256.50
61
DUMMY
-4491.97 -394.50
26
COM12
-6897.71 -283.50
62
DUMMY
-4411.97 -394.50
27
COM10
-6897.71 -310.50
63
DUMMY
-4331.97 -394.50
28
COM8
-6897.71 -337.50
64
DUMMY
-4251.97 -394.50
29
TLBI
-6897.71 -394.50
65
DUMMY
-4171.97 -394.50
30
TLBO
-6897.71 -421.50
66
DUMMY
-4091.97 -394.50
31
COM6
-6749.45 -367.71
67
DUMMY
-4011.97 -394.50
32
COM4
-6722.45 -367.71
68
DUMMY
-3931.97 -394.50
33
COM2
-6695.45 -367.71
69
DUMMY
-3851.97 -394.50
D
Ver 1.3a
3/216
3/2/2009
ST7669
70
DUMMY
-3771.97 -394.50
105
D14
-972.25
-394.50
71
DUMMY
-3691.97 -394.50
106
D15
-892.25
-394.50
72
DUMMY
-3611.97 -394.50
107
D16
-812.25
-394.50
73
DUMMY
-3531.97 -394.50
108
D17
-732.25
-394.50
74
DUMMY
-3451.97 -394.50
109
VSS
-652.25
-394.50
75
DUMMY
-3371.97 -394.50
110
VDD
-572.25
-394.50
76
DUMMY
-3291.97 -394.50
111
E_RD
-492.25
-394.50
77
DUMMY
-3211.97 -394.50
112
/RST
-412.25
-394.50
78
DUMMY
-3131.97 -394.50
113
CSEL
-332.25
-394.50
79
DUMMY
-3051.97 -394.50
114
IF1
-252.25
-394.50
80
DUMMY
-2971.97 -394.50
115
IF2
-172.25
-394.50
81
DUMMY
-2891.97 -394.50
116
IF3
-92.25
-394.50
82
DUMMY
-2811.97 -394.50
117
VSS
-12.25
-394.50
83
DUMMY
-2731.97 -394.50
118
VDD
67.75
-394.50
84
DUMMY
-2651.97 -394.50
119
/CS
147.75
-394.50
85
DUMMY
-2571.97 -394.50
120
/EXT
227.75
-394.50
86
CL
-2491.97 -394.50
121
TE
307.75
-394.50
87
CLS
-2411.97 -394.50
122
TCAP
387.75
-394.50
88
VDD
-2332.25 -394.50
123
VDD
467.75
-394.50
89
A0
-2252.25 -394.50
124
VDD
547.75
-394.50
90
RW_WR
-2172.25 -394.50
125
VDD
627.75
-394.50
91
D0
-2092.25 -394.50
126
VDD
707.75
-394.50
92
D1
-2012.25 -394.50
127
VDD
787.75
-394.50
93
D2
-1932.25 -394.50
128
VDD
867.75
-394.50
94
D3
-1852.25 -394.50
129
VSS1
947.75
-394.50
95
D4
-1772.25 -394.50
130
VSS1
1027.75
-394.50
96
D5
-1692.25 -394.50
131
VSS
1107.75
-394.50
97
D6
-1612.25 -394.50
132
VSS
1187.75
-394.50
98
D7
-1532.25 -394.50
133
VSS
1267.75
-394.50
99
D8
-1452.25 -394.50
134
VSS
1347.75
-394.50
100
D9
-1372.25 -394.50
135
VSS2
1427.75
-394.50
101
D10
-1292.25 -394.50
136
VSS2
1507.75
-394.50
102
D11
-1212.25 -394.50
137
VSS2
1587.75
-394.50
103
D12
-1132.25 -394.50
138
VSS2
1667.75
-394.50
104
D13
-1052.25 -394.50
139
VSS2
1747.75
-394.50
Ver 1.3a
4/216
3/2/2009
ST7669
140
VSS2
1827.75
-394.50
175
V0in
4627.75
-394.50
141
VSS2
1907.75
-394.50
176
V0in
4707.75
-394.50
142
VSS2
1987.75
-394.50
177
V0s
4787.75
-394.50
143
VSS2
2067.75
-394.50
178
V0out
4867.75
-394.50
144
VSS2
2147.75
-394.50
179
V0out
4947.75
-394.50
145
VSS2
2227.75
-394.50
180
XV0out
5027.75
-394.50
146
VSS2
2307.75
-394.50
181
XV0out
5107.75
-394.50
147
VSS4
2387.75
-394.50
182
XV0s
5187.75
-394.50
148
VSS4
2467.75
-394.50
183
XV0in
5267.75
-394.50
149
VDD3
2547.75
-394.50
184
XV0in
5347.75
-394.50
150
VDD3
2627.75
-394.50
185
XV0in
5427.75
-394.50
151
VDD4
2707.75
-394.50
186
XV0in
5507.75
-394.50
152
VDD4
2787.75
-394.50
187
Vgout
5587.75
-394.50
153
VDD5
2867.75
-394.50
188
Vgout
5667.75
-394.50
154
VDD5
2947.75
-394.50
189
Vgs
5747.75
-394.50
155
VDD5
3027.75
-394.50
190
Vgin
5827.75
-394.50
156
VDD5
3107.75
-394.50
191
Vgin
5907.75
-394.50
157
VDD5
3187.75
-394.50
192
Vgin
5987.75
-394.50
158
VDD5
3267.75
-394.50
193
Vgin
6067.75
-394.50
159
VDD5
3347.75
-394.50
194
Vgin
6147.75
-394.50
160
VDD5
3427.75
-394.50
195
Vgin
6227.75
-394.50
161
VDD2
3507.75
-394.50
196
Vgin
6307.75
-394.50
162
VDD2
3587.75
-394.50
197
Vgin
6387.75
-394.50
163
VDD2
3667.75
-394.50
198
6467.75
-394.50
164
VDD2
3747.75
-394.50
199
DUMMY
6547.75
-394.50
165
VDD2
3827.75
-394.50
200
TGO
6608.30
-367.71
166
VDD2
3907.75
-394.50
201
COM1
6668.45
-367.71
167
VDD2
3987.75
-394.50
202
COM3
6695.45
-367.71
168
VDD2
4067.75
-394.50
203
COM5
6722.45
-367.71
169
VDD2
4147.75
-394.50
204
COM7
6749.45
-367.71
170
VDD2
4227.75
-394.50
205
TRBO
6897.71
-421.50
171
Vm
4307.75
-394.50
206
TRBI
6897.71
-394.50
172
VREF
4387.75
-394.50
207
COM9
6897.71
-337.50
173
V0in
4467.75
-394.50
208
COM11
6897.71
-310.50
174
V0in
4547.75
-394.50
209
COM13
6897.71
-283.50
Ver 1.3a
5/216
VSS
3/2/2009
ST7669
210
COM15
6897.71
-256.50
245
COM75
6554.18
367.71
211
COM17
6897.71
-229.50
246
COM77
6527.18
367.71
212
COM19
6897.71
-202.50
247
COM79
6500.18
367.71
213
COM21
6897.71
-175.50
248
COM81
6473.18
367.71
214
COM23
6897.71
-148.50
249
COM83
6446.18
367.71
215
COM25
6897.71
-121.50
250
COM85
6419.18
367.71
216
COM27
6897.71
-94.50
251
COM87
6392.18
367.71
217
COM29
6897.71
-67.50
252
COM89
6365.18
367.71
218
COM31
6897.71
-40.50
253
COM91
6338.18
367.71
219
COM33
6897.71
-13.50
254
COM93
6311.18
367.71
220
COM35
6897.71
13.50
255
COM95
6284.18
367.71
221
COM37
6897.71
40.50
256
COM97
6257.18
367.71
222
COM39
6897.71
67.50
257
COM99
6230.18
367.71
223
COM41
6897.71
94.50
258
COM101
6203.18
367.71
224
COM43
6897.71
121.50
259
COM103
6176.18
367.71
225
COM45
6897.71
148.50
260
COM105
6149.18
367.71
226
COM47
6897.71
175.50
261
COM107
6122.18
367.71
227
COM49
6897.71
202.50
262
COM109
6095.18
367.71
228
COM51
6897.71
229.50
263
COM111
6068.18
367.71
229
COM53
6897.71
256.50
264
COM113
6041.18
367.71
230
COM55
6897.71
283.50
265
COM115
6014.18
367.71
231
COM57
6897.71
310.50
266
COM117
5987.18
367.71
232
COM59
6897.71
337.50
267
COM119
5960.18
367.71
233
TRUI
6897.71
394.50
268
COM121
5933.18
367.71
234
TRUO
6897.71
421.50
269
COM123
5906.18
367.71
235
COM61
6743.18
367.71
270
COM125
5879.18
367.71
236
COM63
6716.18
367.71
271
COM127
5852.18
367.71
237
COM65
6689.18
367.71
272
COM129
5825.18
367.71
238
COM67
6662.18
367.71
273
COM131
5798.18
367.71
239
COM69
6635.18
367.71
274
COM133
5771.18
367.71
240
L-Mark
6593.69
234.18
275
COM135
5744.18
367.71
241
COM71
6608.18
367.71
276
COM137
5717.18
367.71
242
L-Mark
6593.69
234.18
277
COM139
5690.18
367.71
243
L-Mark
6593.69
234.18
278
COM141
5663.18
367.71
244
COM73
6581.18
367.71
279
COM143
5636.18
367.71
Ver 1.3a
6/216
3/2/2009
ST7669
280
COM145
5609.18
367.71
315
SEG26
4630.50
367.71
281
COM147
5582.18
367.71
316
SEG27
4603.50
367.71
282
COM149
5555.18
367.71
317
SEG28
4576.50
367.71
283
COM151
5528.18
367.71
318
SEG29
4549.50
367.71
284
COM153
5501.18
367.71
319
SEG30
4522.50
367.71
285
COM155
5474.18
367.71
320
SEG31
4495.50
367.71
286
COM157
5447.18
367.71
321
SEG32
4468.50
367.71
287
COM159
5420.18
367.71
322
SEG33
4441.50
367.71
288
COM161
5393.18
367.71
323
SEG34
4414.50
367.71
289
SEG0
5332.50
367.71
324
SEG35
4387.50
367.71
290
SEG1
5305.50
367.71
325
SEG36
4360.50
367.71
291
SEG2
5278.50
367.71
326
SEG37
4333.50
367.71
292
SEG3
5251.50
367.71
327
SEG38
4306.50
367.71
293
SEG4
5224.50
367.71
328
SEG39
4279.50
367.71
294
SEG5
5197.50
367.71
329
SEG40
4252.50
367.71
295
SEG6
5170.50
367.71
330
SEG41
4225.50
367.71
296
SEG7
5143.50
367.71
331
SEG42
4198.50
367.71
297
SEG8
5116.50
367.71
332
SEG43
4171.50
367.71
298
SEG9
5089.50
367.71
333
SEG44
4144.50
367.71
299
SEG10
5062.50
367.71
334
SEG45
4117.50
367.71
300
SEG11
5035.50
367.71
335
SEG46
4090.50
367.71
301
SEG12
5008.50
367.71
336
SEG47
4063.50
367.71
302
SEG13
4981.50
367.71
337
SEG48
4036.50
367.71
303
SEG14
4954.50
367.71
338
SEG49
4009.50
367.71
304
SEG15
4927.50
367.71
339
SEG50
3982.50
367.71
305
SEG16
4900.50
367.71
340
SEG51
3955.50
367.71
306
SEG17
4873.50
367.71
341
SEG52
3928.50
367.71
307
SEG18
4846.50
367.71
342
SEG53
3901.50
367.71
308
SEG19
4819.50
367.71
343
SEG54
3874.50
367.71
309
SEG20
4792.50
367.71
344
SEG55
3847.50
367.71
310
SEG21
4765.50
367.71
345
SEG56
3820.50
367.71
311
SEG22
4738.50
367.71
346
SEG57
3793.50
367.71
312
SEG23
4711.50
367.71
347
SEG58
3766.50
367.71
313
SEG24
4684.50
367.71
348
SEG59
3739.50
367.71
314
SEG25
4657.50
367.71
349
SEG60
3712.50
367.71
Ver 1.3a
7/216
3/2/2009
ST7669
350
SEG61
3685.50
367.71
385
SEG96
2740.50
367.71
351
SEG62
3658.50
367.71
386
SEG97
2713.50
367.71
352
SEG63
3631.50
367.71
387
SEG98
2686.50
367.71
353
SEG64
3604.50
367.71
388
SEG99
2659.50
367.71
354
SEG65
3577.50
367.71
389
SEG100
2632.50
367.71
355
SEG66
3550.50
367.71
390
SEG101
2605.50
367.71
356
SEG67
3523.50
367.71
391
SEG102
2578.50
367.71
357
SEG68
3496.50
367.71
392
SEG103
2551.50
367.71
358
SEG69
3469.50
367.71
393
SEG104
2524.50
367.71
359
SEG70
3442.50
367.71
394
SEG105
2497.50
367.71
360
SEG71
3415.50
367.71
395
SEG106
2470.50
367.71
361
SEG72
3388.50
367.71
396
SEG107
2443.50
367.71
362
SEG73
3361.50
367.71
397
SEG108
2416.50
367.71
363
SEG74
3334.50
367.71
398
SEG109
2389.50
367.71
364
SEG75
3307.50
367.71
399
SEG110
2362.50
367.71
365
SEG76
3280.50
367.71
400
SEG111
2335.50
367.71
366
SEG77
3253.50
367.71
401
SEG112
2308.50
367.71
367
SEG78
3226.50
367.71
402
SEG113
2281.50
367.71
368
SEG79
3199.50
367.71
403
SEG114
2254.50
367.71
369
SEG80
3172.50
367.71
404
SEG115
2227.50
367.71
370
SEG81
3145.50
367.71
405
SEG116
2200.50
367.71
371
SEG82
3118.50
367.71
406
SEG117
2173.50
367.71
372
SEG83
3091.50
367.71
407
SEG118
2146.50
367.71
373
SEG84
3064.50
367.71
408
SEG119
2119.50
367.71
374
SEG85
3037.50
367.71
409
SEG120
2092.50
367.71
375
SEG86
3010.50
367.71
410
SEG121
2065.50
367.71
376
SEG87
2983.50
367.71
411
SEG122
2038.50
367.71
377
SEG88
2956.50
367.71
412
SEG123
2011.50
367.71
378
SEG89
2929.50
367.71
413
SEG124
1984.50
367.71
379
SEG90
2902.50
367.71
414
SEG125
1957.50
367.71
380
SEG91
2875.50
367.71
415
SEG126
1930.50
367.71
381
SEG92
2848.50
367.71
416
SEG127
1903.50
367.71
382
SEG93
2821.50
367.71
417
SEG128
1876.50
367.71
383
SEG94
2794.50
367.71
418
SEG129
1849.50
367.71
384
SEG95
2767.50
367.71
419
SEG130
1822.50
367.71
Ver 1.3a
8/216
3/2/2009
ST7669
420
SEG131
1795.50
367.71
455
SEG166
850.50
367.71
421
SEG132
1768.50
367.71
456
SEG167
823.50
367.71
422
SEG133
1741.50
367.71
457
SEG168
796.50
367.71
423
SEG134
1714.50
367.71
458
SEG169
769.50
367.71
424
SEG135
1687.50
367.71
459
SEG170
742.50
367.71
425
SEG136
1660.50
367.71
460
SEG171
715.50
367.71
426
SEG137
1633.50
367.71
461
SEG172
688.50
367.71
427
SEG138
1606.50
367.71
462
SEG173
661.50
367.71
428
SEG139
1579.50
367.71
463
SEG174
634.50
367.71
429
SEG140
1552.50
367.71
464
SEG175
607.50
367.71
430
SEG141
1525.50
367.71
465
SEG176
580.50
367.71
431
SEG142
1498.50
367.71
466
SEG177
553.50
367.71
432
SEG143
1471.50
367.71
467
SEG178
526.50
367.71
433
SEG144
1444.50
367.71
468
SEG179
499.50
367.71
434
SEG145
1417.50
367.71
469
SEG180
472.50
367.71
435
SEG146
1390.50
367.71
470
SEG181
445.50
367.71
436
SEG147
1363.50
367.71
471
SEG182
418.50
367.71
437
SEG148
1336.50
367.71
472
SEG183
391.50
367.71
438
SEG149
1309.50
367.71
473
SEG184
364.50
367.71
439
SEG150
1282.50
367.71
474
SEG185
337.50
367.71
440
SEG151
1255.50
367.71
475
SEG186
310.50
367.71
441
SEG152
1228.50
367.71
476
SEG187
283.50
367.71
442
SEG153
1201.50
367.71
477
SEG188
256.50
367.71
443
SEG154
1174.50
367.71
478
SEG189
229.50
367.71
444
SEG155
1147.50
367.71
479
SEG190
202.50
367.71
445
SEG156
1120.50
367.71
480
SEG191
175.50
367.71
446
SEG157
1093.50
367.71
481
SEG192
148.50
367.71
447
SEG158
1066.50
367.71
482
SEG193
121.50
367.71
448
SEG159
1039.50
367.71
483
SEG194
94.50
367.71
449
SEG160
1012.50
367.71
484
SEG195
67.50
367.71
450
SEG161
985.50
367.71
485
SEG196
40.50
367.71
451
SEG162
958.50
367.71
486
SEG197
13.50
367.71
452
SEG163
931.50
367.71
487
SEG198
-13.50
367.71
453
SEG164
904.50
367.71
488
SEG199
-40.50
367.71
454
SEG165
877.50
367.71
489
SEG200
-67.50
367.71
Ver 1.3a
9/216
3/2/2009
ST7669
490
SEG201
-94.50
367.71
525
SEG236
-1039.50
367.71
491
SEG202
-121.50
367.71
526
SEG237
-1066.50
367.71
492
SEG203
-148.50
367.71
527
SEG238
-1093.50
367.71
493
SEG204
-175.50
367.71
528
SEG239
-1120.50
367.71
494
SEG205
-202.50
367.71
529
SEG240
-1147.50
367.71
495
SEG206
-229.50
367.71
530
SEG241
-1174.50
367.71
496
SEG207
-256.50
367.71
531
SEG242
-1201.50
367.71
497
SEG208
-283.50
367.71
532
SEG243
-1228.50
367.71
498
SEG209
-310.50
367.71
533
SEG244
-1255.50
367.71
499
SEG210
-337.50
367.71
534
SEG245
-1282.50
367.71
500
SEG211
-364.50
367.71
535
SEG246
-1309.50
367.71
501
SEG212
-391.50
367.71
536
SEG247
-1336.50
367.71
502
SEG213
-418.50
367.71
537
SEG248
-1363.50
367.71
503
SEG214
-445.50
367.71
538
SEG249
-1390.50
367.71
504
SEG215
-472.50
367.71
539
SEG250
-1417.50
367.71
505
SEG216
-499.50
367.71
540
SEG251
-1444.50
367.71
506
SEG217
-526.50
367.71
541
SEG252
-1471.50
367.71
507
SEG218
-553.50
367.71
542
SEG253
-1498.50
367.71
508
SEG219
-580.50
367.71
543
SEG254
-1525.50
367.71
509
SEG220
-607.50
367.71
544
SEG255
-1552.50
367.71
510
SEG221
-634.50
367.71
545
SEG256
-1579.50
367.71
511
SEG222
-661.50
367.71
546
SEG257
-1606.50
367.71
512
SEG223
-688.50
367.71
547
SEG258
-1633.50
367.71
513
SEG224
-715.50
367.71
548
SEG259
-1660.50
367.71
514
SEG225
-742.50
367.71
549
SEG260
-1687.50
367.71
515
SEG226
-769.50
367.71
550
SEG261
-1714.50
367.71
516
SEG227
-796.50
367.71
551
SEG262
-1741.50
367.71
517
SEG228
-823.50
367.71
552
SEG263
-1768.50
367.71
518
SEG229
-850.50
367.71
553
SEG264
-1795.50
367.71
519
SEG230
-877.50
367.71
554
SEG265
-1822.50
367.71
520
SEG231
-904.50
367.71
555
SEG266
-1849.50
367.71
521
SEG232
-931.50
367.71
556
SEG267
-1876.50
367.71
522
SEG233
-958.50
367.71
557
SEG268
-1903.50
367.71
523
SEG234
-985.50
367.71
558
SEG269
-1930.50
367.71
524
SEG235
-1012.50
367.71
559
SEG270
-1957.50
367.71
Ver 1.3a
10/216
3/2/2009
ST7669
560
SEG271
-1984.50
367.71
595
SEG306
-2929.50
367.71
561
SEG272
-2011.50
367.71
596
SEG307
-2956.50
367.71
562
SEG273
-2038.50
367.71
597
SEG308
-2983.50
367.71
563
SEG274
-2065.50
367.71
598
SEG309
-3010.50
367.71
564
SEG275
-2092.50
367.71
599
SEG310
-3037.50
367.71
565
SEG276
-2119.50
367.71
600
SEG311
-3064.50
367.71
566
SEG277
-2146.50
367.71
601
SEG312
-3091.50
367.71
567
SEG278
-2173.50
367.71
602
SEG313
-3118.50
367.71
568
SEG279
-2200.50
367.71
603
SEG314
-3145.50
367.71
569
SEG280
-2227.50
367.71
604
SEG315
-3172.50
367.71
570
SEG281
-2254.50
367.71
605
SEG316
-3199.50
367.71
571
SEG282
-2281.50
367.71
606
SEG317
-3226.50
367.71
572
SEG283
-2308.50
367.71
607
SEG318
-3253.50
367.71
573
SEG284
-2335.50
367.71
608
SEG319
-3280.50
367.71
574
SEG285
-2362.50
367.71
609
SEG320
-3307.50
367.71
575
SEG286
-2389.50
367.71
610
SEG321
-3334.50
367.71
576
SEG287
-2416.50
367.71
611
SEG322
-3361.50
367.71
577
SEG288
-2443.50
367.71
612
SEG323
-3388.50
367.71
578
SEG289
-2470.50
367.71
613
SEG324
-3415.50
367.71
579
SEG290
-2497.50
367.71
614
SEG325
-3442.50
367.71
580
SEG291
-2524.50
367.71
615
SEG326
-3469.50
367.71
581
SEG292
-2551.50
367.71
616
SEG327
-3496.50
367.71
582
SEG293
-2578.50
367.71
617
SEG328
-3523.50
367.71
583
SEG294
-2605.50
367.71
618
SEG329
-3550.50
367.71
584
SEG295
-2632.50
367.71
619
SEG330
-3577.50
367.71
585
SEG296
-2659.50
367.71
620
SEG331
-3604.50
367.71
586
SEG297
-2686.50
367.71
621
SEG332
-3631.50
367.71
587
SEG298
-2713.50
367.71
622
SEG333
-3658.50
367.71
588
SEG299
-2740.50
367.71
623
SEG334
-3685.50
367.71
589
SEG300
-2767.50
367.71
624
SEG335
-3712.50
367.71
590
SEG301
-2794.50
367.71
625
SEG336
-3739.50
367.71
591
SEG302
-2821.50
367.71
626
SEG337
-3766.50
367.71
592
SEG303
-2848.50
367.71
627
SEG338
-3793.50
367.71
593
SEG304
-2875.50
367.71
628
SEG339
-3820.50
367.71
594
SEG305
-2902.50
367.71
629
SEG340
-3847.50
367.71
Ver 1.3a
11/216
3/2/2009
ST7669
630
SEG341
-3874.50
367.71
665
SEG376
-4819.50
367.71
631
SEG342
-3901.50
367.71
666
SEG377
-4846.50
367.71
632
SEG343
-3928.50
367.71
667
SEG378
-4873.50
367.71
633
SEG344
-3955.50
367.71
668
SEG379
-4900.50
367.71
634
SEG345
-3982.50
367.71
669
SEG380
-4927.50
367.71
635
SEG346
-4009.50
367.71
670
SEG381
-4954.50
367.71
636
SEG347
-4036.50
367.71
671
SEG382
-4981.50
367.71
637
SEG348
-4063.50
367.71
672
SEG383
-5008.50
367.71
638
SEG349
-4090.50
367.71
673
SEG384
-5035.50
367.71
639
SEG350
-4117.50
367.71
674
SEG385
-5062.50
367.71
640
SEG351
-4144.50
367.71
675
SEG386
-5089.50
367.71
641
SEG352
-4171.50
367.71
676
SEG387
-5116.50
367.71
642
SEG353
-4198.50
367.71
677
SEG388
-5143.50
367.71
643
SEG354
-4225.50
367.71
678
SEG389
-5170.50
367.71
644
SEG355
-4252.50
367.71
679
SEG390
-5197.50
367.71
645
SEG356
-4279.50
367.71
680
SEG391
-5224.50
367.71
646
SEG357
-4306.50
367.71
681
SEG392
-5251.50
367.71
647
SEG358
-4333.50
367.71
682
SEG393
-5278.50
367.71
648
SEG359
-4360.50
367.71
683
SEG394
-5305.50
367.71
649
SEG360
-4387.50
367.71
684
SEG395
-5332.50
367.71
650
SEG361
-4414.50
367.71
685
COM160
-5393.18
367.71
651
SEG362
-4441.50
367.71
686
COM158
-5420.18
367.71
652
SEG363
-4468.50
367.71
687
COM156
-5447.18
367.71
653
SEG364
-4495.50
367.71
688
COM154
-5474.18
367.71
654
SEG365
-4522.50
367.71
689
COM152
-5501.18
367.71
655
SEG366
-4549.50
367.71
690
COM150
-5528.18
367.71
656
SEG367
-4576.50
367.71
691
COM148
-5555.18
367.71
657
SEG368
-4603.50
367.71
692
COM146
-5582.18
367.71
658
SEG369
-4630.50
367.71
693
COM144
-5609.18
367.71
659
SEG370
-4657.50
367.71
694
COM142
-5636.18
367.71
660
SEG371
-4684.50
367.71
695
COM140
-5663.18
367.71
661
SEG372
-4711.50
367.71
696
COM138
-5690.18
367.71
662
SEG373
-4738.50
367.71
697
COM136
-5717.18
367.71
663
SEG374
-4765.50
367.71
698
COM134
-5744.18
367.71
664
SEG375
-4792.50
367.71
699
COM132
-5771.18
367.71
Ver 1.3a
12/216
3/2/2009
ST7669
700
COM130
-5798.18
367.71
735
COM64
-6689.18
367.71
701
COM128
-5825.18
367.71
736
COM62
-6716.18
367.71
702
COM126
-5852.18
367.71
737
COM60
-6743.18
367.71
703
COM124
-5879.18
367.71
738
L-Mark
6593.69
-230.09
704
COM122
-5906.18
367.71
705
COM120
-5933.18
367.71
706
COM118
-5960.18
367.71
707
COM116
-5987.18
367.71
708
COM114
-6014.18
367.71
709
COM112
-6041.18
367.71
710
COM110
-6068.18
367.71
711
COM108
-6095.18
367.71
712
COM106
-6122.18
367.71
713
COM104
-6149.18
367.71
714
COM102
-6176.18
367.71
715
COM100
-6203.18
367.71
716
COM98
-6230.18
367.71
717
COM96
-6257.18
367.71
718
COM94
-6284.18
367.71
719
COM92
-6311.18
367.71
720
COM90
-6338.18
367.71
721
COM88
-6365.18
367.71
722
COM86
-6392.18
367.71
723
COM84
-6419.18
367.71
724
COM82
-6446.18
367.71
725
COM80
-6473.18
367.71
726
COM78
-6500.18
367.71
727
COM76
-6527.18
367.71
728
COM74
-6554.18
367.71
729
COM72
-6581.18
367.71
730
L-Mark
-6593.69
234.18
731
L-Mark
-6593.69
234.18
732
COM70
-6608.18
367.71
733
COM68
-6635.18
367.71
734
COM66
-6662.18
367.71
Ver 1.3a
13/216
3/2/2009
ST7669
5 BLOCK DIAGRAM
Ver 1.3a
14/216
3/2/2009
ST7669
6 PIN DESCRIPTION
6.1 Power Supply
Name
I/O
Description
VDD
Supply
Power supply for logic circuit (Digital VDD 1.65V~3.0V)
VDD2
Supply
Power supply for Booster Circuit (Analog VDD 2.4V~3.3V)
VDD3
Supply
Power supply for LCD. (Analog VDD 2.4V~3.3V)
VDD4
Supply
Power supply for LCD. (Analog VDD 2.4V~3.3V)
VDD5
Supply
Power supply for LCD. (Analog VDD 2.4V~3.3V)
VSS
Supply
Ground for logic circuit. Ground system should be connected together.
VSS1
Supply
Ground for OSC circuit. Ground system should be connected together.
VSS2
Supply
Ground for Booster Circuit. Ground system should be connected together.
VSS4
Supply
Ground for LCD. Ground system should be connected together.
6.2 LCD Power Supply Pins
Name
Description
I/O
Positive LCD driver supply voltages.
V0OUT
V0IN
V0OUT is the output voltage of V0 generated by ST7669.
I/O
V0S
V0IN is the input pin of power supply to generate V0 voltage for LCD.
V0S is the input pin of power supply to sense the V0 voltage.
V0OUT 、V0IN & V0S should be connected together in FPC.
Negative LCD driver supply voltages.
XV0OUT
XV0IN
XV0OUT is the output voltage of XV0 generated by ST7669.
I/O
XV0S
XV0IN is the input pin of power supply to generate XV0 voltage for LCD.
XV0S is the input pin of power supply to sense the XV0 voltage.
XV0OUT 、XV0IN & XV0S should be connected together in FPC.
Bias LCD driver supply voltages.
VgOUT is the output voltage of Vg generated by ST7669.
VgIN is the input pin of power supply to generate Vg voltage for LCD.
VgS is the input pin of power supply to sense the Vg voltage.
VgOUT 、VgIN & VgS should be connected together in FPC.
VgOUT
Vm is the I/O pin of LCD bias supply voltage
VgIN
I/O
VgS
Voltages should have the following relationship:
Vm
V0≧ Vg ≧ Vm ≧ VSS ≧ XV0
and
VDDA-0.7V>Vm>0.7V, 2xVDDA≧Vg>1.8V
When the internal power circuit is active, these voltages are generated as following table according
to the state of LCD bias.
Ver 1.3a
LCD bias
Vg
Vm
1/N bias
(2/N) x V0
(1/N) x V0
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6.3 System Control
Name
I/O
CLS
I
Description
When using internal clock oscillator, connect CLS to VDD.
When using external clock oscillator, connect CLS to VSS.
CL
I/O
When using external clock oscillator, it’s clock input.
CSEL
I
TCAP
I/O
Test pin. Left it opens.
VREF
O
Reference voltage output for monitor only. Left it opened.
VPP
I
When writing OTP, it needs outer power supply voltage 7.50~7.75V(>4mA) input to write successfully.
This pin should connect to VDD.
6.4 Microprocessor Interface
Name
I/O
/RST
I
Description
Reset input pin
When /RST is “L”, initialization is executed.
Parallel / Serial data input select input
IF[3:1]
I
IF3
IF2
IF1
MPU interface type
MPU interface type
H
H
H
80 series 16-bit parallel
80 series 16-bit parallel
H
H
L
80 series 8-bit parallel
80 series 8-bit parallel
H
L
H
68 series 16-bit parallel
68 series 16-bit parallel
H
L
L
68 series 8-bit parallel
68 series 8-bit parallel
L
H
H
8-bit serial (4 line)
8-bit serial (4 line)
L
H
L
9-bit serial (3 line)
9-bit serial (3 line)
L
L
H
80 series 18-bit parallel
80 series 18-bit parallel
L
L
L
68 series 18-bit parallel
68 series 18-bit parallel
Note:
1. When fixing IF2=H & IF1=L, IF3 can be defined as P/SX pin (parallel/Serial selection
pin).IF3=H: Parallel interface (80 8-bit); IF3=L: Serial interface (3-line)
2. Refer to Table 7.1-1. for detail interface connecton.
Chip select input pins
/CS
I
Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D17
become high impedance.
Register select input pin
A0 = "H": D0 to D17 or SI are display data
A0
I
A0 = "L": D0 to D17 or SI are control data
** In 3-line/4-line interface this pad will be used for SCL function
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Read / Write execution control pin. (This pin is only used in parallel interface)
MPU type
RW_WR
Description
Read / Write control input pin
6800-series
RW_WR
RW
I
RW = “H” : read
RW = “L” : write
Write enable clock input pin
8080-series
/WR
The data on D0 to D17 are latched at the
rising edge of the /WR signal.
When in the serial interface, connect it to VDD.
Read / Write execution control pin. (This pin is only used in parallel interface)
MPU Type
E_RD
Description
Read / Write control input pin
RW = “H”: When E is “H”, D0 to D17 are in an output.
6800-series
E_RD
E
I
RW = “L”: The data on D0 to D17 are latched at the
falling edge of the E signal.
Read enable clock input pin
8080-series
/RD
When /RD is “L”, D0 to D17 are in an output status.
When in the serial interface, connect it to VDD.
They connect to the standard 8-bit or 16 bit MPU bus via the 8/16/18 –bit bi-directional bus.
When the following interface is selected and /CS pin is high, following pins become high
impedance.
D17 to D0
1.
In 8-bit parallel: D17-D8 pins are in the state of high impedance should connect to VDD.
2.
In 3-line/4-line interface D0 pad will be used for SI function
3.
In 4-line interface D1 pad will be used for A0 function
4.
In Serial interface: The unused pins are in the state of high impedance should connect to
I/O
VDD.
SI is used to input serial data when the serial interface is selected.(3 line and 4 line)
SI
I
In ST7669, D0 is the SI when select serial interface. See Table 7.1.1
SCL is used to input serial clock when the serial interface is selected.
SCL
I
The data is converted in the rising edge. (3 line and 4 line)
In ST7669, RS is the SCL when select serial interface.See Table 7.1.1
TE
O
Tearing effect output.
OTP burn-in control Pin
There is a pull-high resistor between /EXT & VDD in ST7669.
/EXT
I
When burning OTP, please add an external VSS on /EXT. (needs external power supply
voltage VPP=7.5V~7.75V)
NOTE：
1. In any status the control bus and data bus can not floating.
2. The no used pin should connect to VDD (Supply Digital Voltage).
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6.5 LCD DRIVER OUTPUTS
Name
I/O
Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
Segment driver output voltage
Display data
M (Internal)
SEG0
to
O
SEG395
Normal display
Reverse display
H
H
Vg
VSS
H
L
VSS
Vg
L
H
VSS
Vg
L
L
Vg
VSS
VSS
VSS
Sleep-In mode
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
COM0
to
O
COM161
Scan data
M (Internal)
Common driver output voltage
H
H
XV0
H
L
V0
L
H
Vm
L
L
Vm
Sleep-In mode
Name
I/O
TGI
I
TGO
O
TRUI
I
TRUO
O
TLUI
I
TLUO
O
TRBI
I
TRBO
O
TLBI
I
TLBO
O
Ver 1.3a
VSS
Description
TGI must connect to TGO by ITO which run a ring on LCM glass
TRUI must connect to TRUO by ITO
TLUI must connect to TLUO by ITO
TRBI must connect to TRBO by ITO
TLBI must connect to TLBO by ITO
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Driving Waveform
Figure 6.5-1 ST7669 COM/SEG Driving Waveform
ST7669 I/O PIN ITO Resister Limitation
Pin Name
ITO Resister
VDD, VDD2~VDD5, VSS,VSS1,VSS2,VSS4
<100Ω
V0IN, V0OUT, V0S ,XV0IN, XV0OUT ,XV0S , VgIN, VgOUT ,VgS ,Vm
<300Ω
VPP
<50Ω
A0, E_RD, RW_WR, /CS, D0 …D17, (SI), (SCL), TE
<1KΩ
/RST
<10KΩ
IF[3:1], CLS, CSEL, /EXT
<1KΩ
TCAP, CL, VREF
Floating
NOTE: 1. Make sure that the ITO resistance of COM0 ~ COM161 is equal, and so is it of SEG0 ~ SEG395.
These Limitations include the bottleneck of ITO layout.
2. The ITO layout suggestion is shown as below:
Driver Side
Driver Side
V0I
V0I
V0S
V0O
VDD
VDD2
VDD3
VDDx
Separated by
ITO
Separated by
ITO
FPC
PIN
FPC
PIN
FPC
PIN
FPC
PIN
Short by FPC
Short by FPC
Figure 6.5-2 Power ITO layout sugestion
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7 FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
/CS pin is for chip selection. The ST7669 is active when /CS=L. In serial interface mode,the internal shift register and the
counter are reset when /CS=H.
7.1.1
Selecting Parallel / Serial Interface
ST7669 has eight types of interface with an MPU, which are two serial and six parallel interfaces. This parallel or serial
interface is determined by IF pin as shown in Table 7.1-1.
Table 7.1-1Parallel / Serial Interface Mode
I/F Mode
Pin Assignment
IF3
IF2
IF1
H
H
L
H
H
L
I/F Description
/CS
A0
E_RD
RW_WR
Used Data Bus
D1
D0
80 serial 8-bit parallel
/CS
A0
/RD
/WR
D7~D2
D1
D0
H
80 serial 16-bit parallel
/CS
A0
/RD
/WR
D15~D2
D1
D0
L
H
80 serial 18-bit parallel
/CS
A0
/RD
/WR
D17~D2
D1
D0
H
L
L
68 serial 8-bit parallel
/CS
A0
E
R/W
D7~D2
D1
D0
H
L
H
68 serial 16-bit parallel
/CS
A0
E
R/W
D15~D2
D1
D0
L
L
L
68 serial 18-bit parallel
/CS
A0
E
R/W
D17~D2
D1
D0
L
H
H
8-bit SPI mode (4 line)
/CS
SCL
--
--
--
A0
SI
L
H
L
9-bit SPI mode (3 line)
/CS
SCL
--
--
--
---
SI
NOTE: When these pins are set to any other combination, A0, E_RD and RW_WR inputs are disabled and D0
to D17 are to be high impedance.
7.1.2
8-bit or 16-bit Parallel Interface
The ST7669 identifies the type of the data bus signals according to the combination of A0, /RD (E) and /WR (W/R) signals,
as shown inTable 7.1-2.
Table 7.1-2Parallel Data Transfer
Common
6800-series
8080-series
Description
A0
R/W
E
/RD
/WR
H
H
↑
↓
H
Register status read
H
H
↑
↓
H
Display data read out
L
L
↓
H
↑
Instruction write
H
L
↓
H
↑
Display data write
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Figure 7.1-1 Parallel Data Transfer Example Chart
Relation between Data Bus and Gradation Data
ST7669 offers 256 color, 4096 color display, 65K color display, 262K color display, and truncated 16M color display.
When using 256 color, 4096, 65K, 262K, and 16M color display; you can specify color for each of R, G, and B using the
palette function. Use the command for switching between these modes.
(1) 256 color input mode
1. 8-bit interface
D7, D6, D5, D4, D3, D2, D1, D0: RRRGGGBB
1st -write
There is only 1 write operation for 1 pixel data.
1 pixel data is written in the display data RAM when 1st -write operation finishes.
2. 16-bit interface
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXXXXXRRRGGGBB
1st -write
There is only 1 write operation for 1 pixel data.
1 pixel data is written in the display data RAM when 1st –write operation finishes. “X” are ignored dummy bits.
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(2) 4096-color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR
D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB
1st-write
2nd-write
There are 2 write operations for 1 pixel data.
1st pixel data is written in the display data RAM when 2nd –write operation finishes. “X” are ignored dummy bits.
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB
1st-write
There is only 1 write operation for 1 pixel data.
1 pixel data is written in the display data RAM when 1st –write operation finishes. “X” are ignored dummy bits.
(3) 65K color input mode
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG
D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB
1st-write
2nd-write
There are 2 write operations for 1 pixel data.
1st pixel data is written in the display data RAM when 2nd –write operation finishes.
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB
There is only 1 write operation for 1 pixel data.
1 pixel data is written in the display data RAM when 1st –write operation finishes.
(4) 262K color input mode
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXX
1st-write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGXX
2nd-write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXX
3rd-write
There are 3 write operations for 1 pixel data.
1st pixel data is written in the display data RAM when 3rd–write operation finishes. “X” are ignored dummy bits.
2. 16 bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXXGGGGGGXX
1st-write
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXXXXXXXXXXXX
2nd-write
There are 2 write operations for 1 pixel data.
1st pixel data is written in the display data RAM when 2nd –write operation finishes. “X” are ignored dummy bits.
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3. 18 bit mode
D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRGGGGGGBBBBBB
There is only 1 write operation for 1 pixel data.
1 pixel data is written in the display data RAM when 1st –write operation finishes. “X” are ignored dummy bits.
(5) Truncated 16M color input mode
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRR
1st-write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGGG
2nd-write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBB
3rd-write
There are 3 write operations for 1 pixel data.
1st pixel data is written in the display data RAM when 3rd–write operation finishes. “X” are ignored dummy bits.
2. 16 bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRRGGGGGGGG
1st-write
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBBXXXXXXXX
2nd-write
There are 2 write operations for 1 pixel data.
1st pixel data is written in the display data RAM when 2nd –write operation finishes. “X” are ignored dummy bits.
7.1.3
8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial
interface uses three pins /CS, SI and SCL for the same purpose.
Data read is not available in the serial interface. Data entered must be 8 bits. The relation between gray-scale data and
data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation.
(1) 8-bit serial interface (4-line)
th
When entering data (parameters): A0= HIGH at the rising edge of the 8 SCL.
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th
When entering command: A0= LOW at the rising edge of the 8 SCL
When entering reading command:
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(2) 9-bit serial interface (3-line)
st
When entering data (parameters): SI= HIGH at the rising edge of the 1 SCL.
st
When entering command: SI= LOW at the rising edge of the 1 SCL.
When entering reading command :
If /CS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering
succeeding sets of data, you must correctly input the data concerned again.
In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to
initialize the serial-to-parallel conversion counter and the register.
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7.1.4
8-bit and 9-bit Serial Interface Data Color Coding
8-bit serial interface (4-line)
(1) R 3-bit, G 3-bit, B 2-bit, 256 colors
There is 1 pixel ( = 3 sub-pixels ) per byte.
(2) R 4-bit, G 4-bit, B 4-bit, 4,096 colors
There is 1 pixel ( = 3 sub-pixels ) per 2 bytes.
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(3) R 5-bit, G 6-bit, B 5-bit, 65,536 colors
There is 1 pixel ( = 3 sub-pixels ) per 2 byte.
(4) R 6-bit, G 6-bit, B 6-bit, 262,144 colors
There is 1 pixel ( = 3 sub-pixels ) per 3 byte.
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(5) R 8-bit, G 8-bit, B 8-bit, 16M colors
There is 1 pixel ( = 3 sub-pixels ) per 3 byte.
9-bit serial interface (3-line)
(1) R 3-bit, G 3-bit, B 2-bit, 256 colors
There is 1 pixel ( = 3 sub-pixels ) per byte.
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(2) R 4-bit, G 4-bit, B 4-bit, 4,096 colors
There is 1 pixel ( = 3 sub-pixels ) per 2 bytes.
(3) R 5-bit, G 6-bit, B 5-bit, 65,536 colors
There is 1 pixel ( = 3 sub-pixels ) per 2 byte.
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(4) R 6-bit, G 6-bit, B 6-bit, 262,144 colors
There is 1 pixel ( = 3 sub-pixels ) per 3 byte.
(5) R 8-bit, G 8-bit, B 8-bit, 16M colors
There is 1 pixel ( = 3 sub-pixels ) per 3 byte.
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7.2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7669 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus
holder attached to the internal, requiring the cycle time alone without needing the wait time.
For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the
DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is
dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus
in the succeeding read cycle. Figure 7.2-1 illustrates these relations.
In 80-series interface mode:
MPU signal
Read
Operation
A0
/WR
/RD
DATA
N
Dummy
D (N )
D (N +1)
Internal signals
/WR
/RD
INTERNAL LATCH
ADDRESS COUNTER
N
D (N )
D (N )
D (N +1)
D (N +2)
D (N +1)
D (N +2)
D (N +3)
Figure 7.2-1
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7.3 DISPLAY DATA RAM (DDRAM)
7.3.1
DDRAM
It is 132 X 162 X 18 bits capacity RAM prepared for storing dot data. Refer to the following memory map for the RAM
configuration.
Memory Map
RGB alignment
Data control command
Column
(MADCTR) MX=0
(MADCTR) MX=1
Color
0
1
131
131
130
0
R
G
B
R
G
B
R
G
B
0
1
2
3
4
5
393
394
395
Data
Page
(MADCTR)
(MADCTR)
MY=0
SEGout
MY=1
0
161
1
160
2
159
3
158
4
157
5
156
6
155
7
154
:
:
154
7
155
6
156
5
157
4
158
3
159
2
160
1
161
0
You can change position of R and B with MADCTR command.
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7.3.2
Address Control
The address counter sets the addresses of the display data RAM for writing.
Data is written pixel into the RAM matrix of ST7669. The data for one pixel or two pixels is collected (RGB 6-6-6 bit),
according to the data formats. As soon as this pixel-data information is complete, the “Write access” is activated on the
RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0
to Y=161 (A1h). Addresses outside these ranges are not allowed.
Before writing to the RAM, a window must be defined into which will be written. The window is programmable via the
command registers XS, YS designating the start address and XE, YE designating the end address.
For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h)
and XE=131 (83h), YE=161 (A1h).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps
around to YS and X increments to address the next column. In horizontal addressing mode (MV=0), the X-address
increments after each byte, after the last X-address (X=XE), X wraps around to SC and Y increments to address the next
row. After the every last address (X=XE and Y=XE) the address pointers wrap around to address (X=XS and Y=YS). For
flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and “MADCTR” , define flags
MX, MY and MV, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Figure
7.3-1 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data must
be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as below:
Condition
Column Counter
Row Counter
When RAMWR command is accepted
Return to “Start
Return to “Start
Column (XS)”
Row (YS)”
Complete Pixel Read / Write action
Increment by 1
No change
The Column counter value is larger than “End Column (XE)”
Return to “Start
Increment by 1
Column (XS)”
The Column counter value is larger than “End Column (XE)” and
Return to “Start
Return to “Start
the Row counter value is larger than “End Row (YE)”
Column (XS)”
Row (YS)”
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Display
MADCTR
Image in the Host
Image in the Driver
Data
Parameter
(MPU)
(DDRAM)
Direction
MV
MX
MY
Normal
0
0
0
Y-Mirror
0
0
1
X-Mirror
0
1
0
X-Mirror
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Y-Mirror
X-Y
Exchange
X-Y
Exchange
Y-Mirror
X-Y
Exchange
X-Mirror
X-Y
Exchange
X-Mirror
Y-Mirror
Figure 7.3-1 Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
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7.3.3
I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU’s read or write of DDRAM is
performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM when the
LCD is turned on does not cause troubles such as flicking of the display images.
7.3.4
Scroll Address Circuit
The circuit associates pages on DDRAM with COM output. ST7669 processes signals for the liquid crystal display on
1-page basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in
block
7.3.5
Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display
normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in
the DDRAM.
7.3.6
Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, contents of the frame memory within an area where column address is 00h to 83h and row address is 00h to
A1h is displayed.
To display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0).
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SEG130
SEG131
SEG129
:
SEG128
:
SEG4
:
SEG3
SEG2
SEG0
Ver 1.3a
SEG1
Example1) Normal Display On
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ST7669
SEG131
SEG130
SEG129
:
SEG128
:
SEG4
:
SEG3
SEG2
SEG0
7.3.7
SEG1
Example2) Partial Display On: SR[15:0] = 0004h, ER[15:0] = 009Eh, MADCTL (ML)=0
Vertical Scroll/Rolling Scroll
Rolling Scroll
There is just one types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and
“Vertical Scrolling Start Address” (37h).
Figure 7.3-2 Rolling Scroll Definition
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =162. In this case, ‘rolling’ scrolling is applied as shown
below. All the memory contents will be used.
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SEG131
SEG130
SEG129
SEG128
:
:
SEG4
:
SEG3
SEG2
SEG0
SEG1
Example1) Panel size=162 x 132, TFA =3, VSA=157, BFA=2, SSA=4, MADCTL (ML)=0: Rolling Scroll
SEG131
SEG130
SEG129
SEG128
:
:
SEG4
:
SEG3
SEG2
SEG1
SEG0
Example2) Panel size=162 x 132, TFA =2, VSA=157, BFA=3, SSA=4, MADCTL (ML)=1: Rolling Scroll (TFA and BFA are
exchanged)
Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and
“Vertical Scrolling Start Address” (37h).
Case 1: TFA + VSA + BFA<162
N/A. Do not set TFA + VSA + BFA<162. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=162 (Rolling Scrolling)
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Example1) When MADCTL parameter ML=”0”, TFA=0, VSA=162, BFA=0 and VSCSAD=40.
Example2) When MADCTL parameter ML=”1”, TFA=10, VSA=152, BFA=0 and VSCSAD=30.
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7.3.8
Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled
by the Tearing Effect Line Off & On commands. The signal can be used by the MPU to synchronize Frame Memory Writing
when displaying video images.
Tearing Effect Line Modes
FRAME
Frame1
Frame2
COM scan
internal signal
1 st line
2 nd line
3 rd line
142th line
162th line
TE
( mode1)
t VDH
t HDH
t CYCLE
t HDH
TE
( mode2)
t VDH
t HCYC
20 line
142 line
162line
20 line
142 line
162 line
th
Mode 1, the Tearing Effect Output signal consists of V-Sync(tVDH) information. It starts at 142 line signal and ends at the
th
162 line signal. There is one high pulse during each frame.
Mode 2, the Tearing Effect Output signal consists of both H-Sync(tHDH) and V-Sync(tVDH) information. TE pin output
th
th
tHDH pulse on each COM scan signal. During 142 ~ 162 line signal, it output a high pulse which equals 1 tHDH + 1
tVDH.
Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low.
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Tearing Effect Line Timing
The Tearing Effect signal is described below:
Table 7.3-1AC characteristics of Tearing Effect Signal
Idle Mode Off (Frame Rate = 77Hz)
Symbol
Parameter
Min
Typ
Max
Unit
description
tVDL
Vertical Timing Low Duration
--
11.4
12
ms
tVDH
Vertical Timing High Duration
1
1.6
2
ms
tHDL
Horizontal Timing Low Duration
--
75
80
us
tHDH
Horizontal Timing High Duration
3
5.17
5.5
us
Mode1
Mode2
NOTE: The timings in Table 7.3-1 apply when MADCTR B4=0 and B4=1
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
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Example 1: MPU Write is faster than Panel Read.
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of
the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame
refresh has a complete new image:
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Example 2: MPU Write is slower than Panel Read.
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the
Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing
download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position.
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7.4 GRAY-SCALE DISPLAY
ST7669 incorporates a 4FRC & 31 PWM function circuit to display a 64 gray-scale display.
7.5 OSCILLATION CIRCUIT
This is on-chip oscillator without external resistor. When the internal oscillator is used, CLS must connect to VDD; when the
external oscillator is used, CL could be input pin. This oscillator signal is used in the voltage converter and display timing
generation circuit.
7.6 DISPLAY TIMING GENERATOR CIRCUIT
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), which is generated by
oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of
on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 96-bits
display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely
independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC
signal (M), which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing
signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal
instruction. Driving waveform and internal timing signal are shown in Figure 7.3-3.
Figure 7.3-3 2-frame AC Driving Waveform (Duty Ratio: 1/162)
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Figure 7.3-4 N-Line Inversion Driving Waveform (N=10, Duty Ratio=1/162)
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7.7 POWER LEVEL DEFINITION
7.7.1
Power ON/OFF SEQUENCE
VDDI and VDDA can be applied in any order.( VDDI=VDD , VDDA=VDD2,VDD3,VDD4,VDD5)
VDDI and VDDA can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 200msec after /RST
has been released.
During power off, if LCD is in the Sleep In mode, VDDI or VDDA can be powered down minimum 0msec after /RST has
been released.
/CS can be applied at any timing or can be permanently grounded. /RST has priority over /CS.
If /RST line is not held stable by host during Power On Sequence as defined in Sections case1 and case2, then it will be
necessary to apply a Hardware Reset (/RST) after Host Power On Sequence is complete to ensure correct operation.
Otherwise function is not guaranteed.
The power on/off sequence is illustrated below:
Case 1 – /RST line is held High or Unstable by Host at Power On
If /RST line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDDA
and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this
hardware reset.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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Case 2 – /RST line is held Low by host at Power On
If /RST line is held Low (and stable) by the host during Power On, then the /RST must be held low for minimum 10µsec
after both VDD and VDDI have been applied.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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7.7.2
Power Levels
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power
Consumption:
1. Normal Mode On (full display), Idle Mode Off, Sleep Out:
In this mode, the display is able to show maximum 262K colours.
2. Partial Mode On, Idle Mode Off, Sleep Out:
In this mode part of the display is used with maximum 262K colours.
3. Normal Mode On (full display), Idle Mode On, Sleep Out:
In this mode, the full display area is used but with 8 colours.
4. Partial Mode On, Idle Mode On, Sleep Out:
In this mode, part of the display is used but with 8 colours.
5. Sleep In Mode:
In this mode, the DC:DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU
interface and memory works with Digital VDDI power supply. Contents of the memory are safe.
6. Power Off Mode:
In this mode, both Analog VDDA and Digital VDDI are removed.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both
Power supplies are removed.
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7.7.3 POWER FLOW CHART FOR DIFFERENT POWER MODES
Normal display mode on = NORON
Partial mode on = PTLON
Idle mode off = IDMOFF
Power on sequence
Idle mode on = IDMON
Sleep out = SLPOUT
Sleep in = SLPIN
HW reset
SW reset
SLPIN
NORON
PTLON
Sleep out
Normal display mode on
Idle mode off
IDMON
NORON
Sleep in
Normal display mode on
Idle mode off
SLPOUT
IDMOFF
IDMON
PTLON
IDMOFF
SLPIN
Sleep out
Normal display mode on
Idle mode on
Sleep in
Normal display mode on
Idle mode on
SLPOUT
SLPIN
Sleep out
Partial mode on
Idle mode off
IDMON
IDMOFF
IDMON
IDMOFF
SLPIN
PTLON
NORON
Sleep in
Partial mode on
Idle mode off
SLPOUT
Sleep out
Partial mode on
Idle mode on
PTLON
Sleep in
Partial mode on
Idle mode on
SLPOUT
Sleep out
NORON
Sleep in
Note
There is not any abnormal visual effect when there is changing from one power mode to another power mode.
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7.8 COLOR DEPTH CONVERSION LOOK UP TABLE
R input (3bit)
R input (4bit)
R input (5 bit)
R output (6bit)
256 colours
4,096 colors
65,536 colours
262,144 colours
8 bit/pixel mode 12 bit/pixel -mode 16 bit/pixel -mode
18 bit/pixel -mode
RGBSET
Parameter
000
0000
00000
R005 R004 R003 R002 R001 R000
1
001
0001
00001
R015 R014 R013 R012 R011 R010
2
010
0010
00010
R025 R024 R023 R022 R021 R020
3
011
0011
00011
R035 R034 R033 R032 R031 R030
4
100
0100
00100
R045 R044 R043 R042 R041 R040
5
101
0101
00101
R055 R054 R053 R052 R051 R050
6
110
0110
00110
R065 R064 R063 R062 R061 R060
7
111
0111
00111
R075 R074 R073 R072 R071 R070
8
Dummy Input
1000
01000
R085 R084 R083 R082 R081 R080
9
Dummy Input
1001
01001
R095 R094 R093 R092 R091 R090
10
Dummy Input
1010
01010
R105 R104 R103 R102 R127 R100
11
Dummy Input
1011
01011
R115 R114 R113 R112 R111 R110
12
Dummy Input
1100
01100
R125 R124 R123 R122 R121 R120
13
Dummy Input
1101
01101
R135 R134 R133 R132 R131 R130
14
Dummy Input
1110
01110
R145 R144 R143 R142 R141 R140
15
Dummy Input
1111
01111
R155 R154 R153 R152 R151 R150
16
Dummy Input
Dummy Input
10000
R165 R164 R163 R162 R161 R160
17
Dummy Input
Dummy Input
10001
R175 R174 R173 R172 R171 R170
18
Dummy Input
Dummy Input
10010
R185 R184 R183 R182 R181 R180
19
Dummy Input
Dummy Input
10011
R195 R194 R193 R192 R191 R190
20
Dummy Input
Dummy Input
10100
R205 R204 R203 R202 R201 R200
21
Dummy Input
Dummy Input
10101
R215 R214 R213 R212 R211 R210
22
Dummy Input
Dummy Input
10110
R225 R224 R223 R222 R221 R220
23
Dummy Input
Dummy Input
10111
R235 R234 R233 R232 R231 R230
24
Dummy Input
Dummy Input
11000
R245 R244 R243 R242 R241 R240
25
Dummy Input
Dummy Input
11001
R255 R254 R253 R252 R251 R250
26
Dummy Input
Dummy Input
11010
R265 R264 R263 R262 R261 R260
27
Dummy Input
Dummy Input
11011
R275 R274 R273 R272 R271 R270
28
Dummy Input
Dummy Input
11100
R285 R284 R283 R282 R281 R280
29
Dummy Input
Dummy Input
11101
R295 R294 R293 R292 R291 R290
30
Dummy Input
Dummy Input
11110
R305 R304 R303 R302 R301 R300
31
Dummy Input
Dummy Input
11111
R315 R314 R313 R312 R311 R310
32
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G input (3bit)
G input (4bit)
G input (6 bit)
G output (6bit)
256 colours
4,096 colors
65,536 colours
262,144 colours
8 bit/pixel mode 12 bit/pixel -mode 16 bit/pixel -mode
18 bit/pixel -mode
RGBSET
Parameter
000
0000
000000
G005 G004 G003 G002 G001 G000
33
001
0001
000001
G015 G014 G013 G012 G011 G010
34
010
0010
000010
G025 G024 G023 G022 G021 G020
35
011
0011
000011
G035 G034 G033 G032 G031 G030
36
100
0100
000100
G045 G044 G043 G042 G041 G040
37
101
0101
000101
G055 G054 G053 G052 G051 G050
38
110
0110
000110
G065 G064 G063 G062 G061 G060
39
111
0111
000111
G075 G074 G073 G072 G071 G070
40
Dummy Input
1000
001000
G085 G084 G083 G082 G081 G080
41
Dummy Input
1001
001001
G095 G094 G093 G092 G091 G090
42
Dummy Input
1010
001010
G105 G104 G103 G102 G127 G100
43
Dummy Input
1011
001011
G115 G114 G113 G112 G111 G110
44
Dummy Input
1100
001100
G125 G124 G123 G122 G121 G120
45
Dummy Input
1101
001101
G135 G134 G133 G132 G131 G130
46
Dummy Input
1110
001110
G145 G144 G143 G142 G141 G140
47
Dummy Input
1111
001111
G155 G154 G153 G152 G151 G150
48
Dummy Input
Dummy Input
010000
G165 G164 G163 G162 G161 G160
49
Dummy Input
Dummy Input
010001
G175 G174 G173 G172 G171 G170
50
Dummy Input
Dummy Input
010010
G185 G184 G183 G182 G181 G180
51
Dummy Input
Dummy Input
010011
G195 G194 G193 G192 G191 G190
52
Dummy Input
Dummy Input
010100
G205 G204 G203 G202 G201 G200
53
Dummy Input
Dummy Input
010101
G215 G214 G213 G212 G211 G210
54
Dummy Input
Dummy Input
010110
G225 G224 G223 G222 G221 G220
55
Dummy Input
Dummy Input
010111
G235 G234 G233 G232 G231 G230
56
Dummy Input
Dummy Input
011000
G245 G244 G243 G242 G241 G240
57
Dummy Input
Dummy Input
011001
G255 G254 G253 G252 G251 G250
58
Dummy Input
Dummy Input
011010
G265 G264 G263 G262 G261 G260
59
Dummy Input
Dummy Input
011011
G275 G274 G273 G272 G271 G270
60
Dummy Input
Dummy Input
011100
G285 G284 G283 G282 G281 G280
61
Dummy Input
Dummy Input
011101
G295 G294 G293 G292 G291 G290
62
Dummy Input
Dummy Input
011110
G305 G304 G303 G302 G301 G300
63
Dummy Input
Dummy Input
011111
G315 G314 G313 G312 G311 G310
64
Dummy Input
Dummy Input
100000
G325 G324 G323 G322 G321 G320
65
Dummy Input
Dummy Input
100001
G335 G334 G333 G332 G331 G330
66
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Dummy Input
Dummy Input
100010
G345 G344 G343 G342 G341 G340
67
Dummy Input
Dummy Input
100011
G355 G354 G353 G352 G351 G350
68
Dummy Input
Dummy Input
100100
G365 G364 G363 G362 G361 G360
69
Dummy Input
Dummy Input
100101
G375 G374 G373 G372 G371 G370
70
Dummy Input
Dummy Input
100110
G385 G384 G383 G382 G381 G380
71
Dummy Input
Dummy Input
100111
G395 G394 G393 G392 G391 G390
72
Dummy Input
Dummy Input
101000
G405 G404 G403 G402 G401 G400
73
Dummy Input
Dummy Input
101001
G415 G414 G413 G412 G411 G410
74
Dummy Input
Dummy Input
101010
G425 G424 G423 G422 G421 G420
75
Dummy Input
Dummy Input
101011
G435 G434 G433 G432 G431 G430
76
Dummy Input
Dummy Input
101100
G445 G444 G443 G442 G441 G440
77
Dummy Input
Dummy Input
101101
G455 G455 G453 G452 G451 G450
78
Dummy Input
Dummy Input
101110
G465 G464 G463 G462 G461 G460
79
Dummy Input
Dummy Input
101111
G475 G474 G473 G472 G471 G470
80
Dummy Input
Dummy Input
110000
G485 G484 G483 G482 G481 G480
81
Dummy Input
Dummy Input
110001
G495 G494 G493 G492 G491 G490
82
Dummy Input
Dummy Input
110010
G505 G504 G503 G502 G501 G500
83
Dummy Input
Dummy Input
110011
G515 G514 G513 G512 G511 G510
84
Dummy Input
Dummy Input
110100
G525 G524 G523 G522 G521 G520
85
Dummy Input
Dummy Input
110101
G535 G534 G533 G532 G531 G530
86
Dummy Input
Dummy Input
110110
G545 G544 G543 G542 G541 G540
87
Dummy Input
Dummy Input
110111
G555 G554 G553 G552 G551 G550
88
Dummy Input
Dummy Input
111000
G565 G564 G563 G562 G561 G560
89
Dummy Input
Dummy Input
111001
G575 G574 G573 G572 G571 G570
90
Dummy Input
Dummy Input
111010
G585 G584 G583 G582 G581 G580
91
Dummy Input
Dummy Input
111011
G595 G594 G593 G592 G591 G590
92
Dummy Input
Dummy Input
111100
G605 G604 G603 G602 G601 G600
93
Dummy Input
Dummy Input
111101
G615 G614 G613 G612 G611 G610
94
Dummy Input
Dummy Input
111110
G625 G624 G623 G622 G621 G620
95
Dummy Input
Dummy Input
111111
G635 G634 G633 G632 G631 G630
96
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B input (2bit)
B input (4bit)
B input (5 bit)
B output (6bit)
256 colours
4,096 colors
65,536 colours
262,144 colours
8 bit/pixel mode 12 bit/pixel -mode 16 bit/pixel -mode
18 bit/pixel -mode
RGBSET
Parameter
00
0000
00000
B005 B004 B003 B002 B001 B000
97
01
0001
00001
B015 B014 B013 B012 B011 B010
98
10
0010
00010
B025 B024 B023 B022 B021 B020
99
11
0011
00011
B035 B034 B033 B032 B031 B030
100
Dummy Input
0100
00100
B045 B044 B043 B042 B041 B040
127
Dummy Input
0101
00101
B055 B054 B053 B052 B051 B050
102
Dummy Input
0110
00110
B065 B064 B063 B062 B061 B060
103
Dummy Input
0111
00111
B075 B074 B073 B072 B071 B070
104
Dummy Input
1000
01000
B085 B084 B083 B082 B081 B080
105
Dummy Input
1001
01001
B095 B094 B093 B092 B091 B090
106
Dummy Input
1010
01010
B105 B104 B103 B102 B127 B100
107
Dummy Input
1011
01011
B115 B114 B113 B112 B111 B110
108
Dummy Input
1100
01100
B125 B124 B123 B122 B121 B120
109
Dummy Input
1101
01101
B135 B134 B133 B132 B131 B130
110
Dummy Input
1110
01110
B145 B144 B143 B142 B141 B140
111
Dummy Input
1111
01111
B155 B154 B153 B152 B151 B150
112
Dummy Input
Dummy Input
10000
B165 B164 B163 B162 B161 B160
113
Dummy Input
Dummy Input
10001
B175 B174 B173 B172 B171 B170
114
Dummy Input
Dummy Input
10010
B185 B184 B183 B182 B181 B180
115
Dummy Input
Dummy Input
10011
B195 B194 B193 B192 B191 B190
116
Dummy Input
Dummy Input
10100
B205 B204 B203 B202 B201 B200
117
Dummy Input
Dummy Input
10101
B215 B214 B213 B212 B211 B210
118
Dummy Input
Dummy Input
10110
B225 B224 B223 B222 B221 B220
119
Dummy Input
Dummy Input
10111
B235 B234 B233 B232 B231 B230
120
Dummy Input
Dummy Input
11000
B245 B244 B243 B242 B241 B240
121
Dummy Input
Dummy Input
11001
B255 B254 B253 B252 B251 B250
122
Dummy Input
Dummy Input
11010
B265 B264 B263 B262 B261 B260
123
Dummy Input
Dummy Input
11011
B275 B274 B273 B272 B271 B270
124
Dummy Input
Dummy Input
11100
B285 B284 B283 B282 B281 B280
125
Dummy Input
Dummy Input
11101
B295 B294 B293 B292 B291 B290
126
Dummy Input
Dummy Input
11110
B305 B304 B303 B302 B301 B300
127
Dummy Input
Dummy Input
11111
B315 B314 B313 B312 B311 B310
128
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7.9 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage
follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". The
diagram as below shows the referenced combinations in using Power Supply circuits.
DC/DC Booster Block Diagram
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7.9.1 Voltage Regulator Circuits
There is a built-in voltage regulator circuits in ST7669 for generating V0. After internal voltage is regulated by voltage
regulator circuit, V0 is generated. Detail explanation of V0 set is listed below:
SET V0 (Temperatue = 24℃)
V0=3.6+{Vop[8:0] + VopOffset[8:0]+ (EV[6:0]-3Fh)}x0.04
(V)
Example1(V0 setting>12V):
Vop[8:0]=011010010 (D2h)
VopOffset[8:0]=0 00111001 (039h)
EV[6:0]=0111111 (3Fh)
V0=3.6 + { 210 + 57 + (63-63) } x 0.04 =14.28 (V)
Example2(V0 setting<12V):
Vop[8:0]=011010010 (D2h)
VopOffset [8:0]=1 11001110 (1CEh)
EV[6:0]=0111111 (3Fh)
V0=3.6 + { 210 -50 + (63-63) } x 0.04 =10 (V)
V0 restriction:
Because Vg should larger than 1.8V, ST7669 V0 value should be higher than 1.8 x Bias / 2 (V) and lower than 18V.
V0 value outside the available range is undefined. Users has to ensure while selecting the temperature compensation that
under all conditions and including all tolerances that the V0 voltage remains in the range.
V0 setting
Inhibit V0 Range
Min
Max
Bias
1/5
4.5
18.0
1/14
1/6
5.4
18.0
1/7
6.3
18.0
1/11
1/8
7.2
18.0
1/10
1/9
8.1
18.0
1/10
9.0
18.0
1/11
9.9
18.0
1/6
1/12
10.8
18.0
1/5
1/13
11.7
18.0
1/14
12.6
18.0
Available V0 Range
1/13
1/12
1/9
1/8
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0
2
4
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6
8
10
V0(Voltage)
12
14
16
18
3/2/2009
20
ST7669
SET V0 with temperature compansation (Temperatue ≠ 24℃)
There are 16-line slope in each temperature steps and customer can select one line slope of temperature
compensation coefficiency for each temperature step. Each temperature step is 8oC. Please see Figure 7.9-1 as
below.
Figure 7.9-1
In command TEMPSET each MTx, where x=0, 1, 2,…, E, F, has a value between 0 and 15. MTx = 0 results in 0V
increment on V0, MTx = 1 results in Mx=5mV increment, MTx = 15 results in Mx=15x5mV=75mV increment. Note that each
MTx individually corresponds to a temperature interval; The relations between Mx and V0 quantity due to temperature V0(T)
are described in the equations shown as follows:
Temperature range
Equation V0(V) at temperature=T℃
℃
-40℃ ℃ T ＜ -32℃
V0(T) = V0(T24)+ (-32-T)．M0 +( M1 + M2 + M3 + M4 + M5 + M6 + M7)．8
-32℃ ℃ T ＜ -24℃
V0(T) = V0(T24)+ (-24-T)．M1 +( M2 + M3 + M4 + M5 + M6 + M7)．8
-24℃ ℃ T ＜ -16℃
V0(T) = V0(T24)+ (-16-T)．M2 +( M3 + M4 + M5 + M6 + M7)．8
-16℃ ℃ T ＜ -8℃
V0(T) = V0(T24)+ (-8-T)．M3 +( M4 + M5 + M6 + M7)．8
-8℃ ℃ T ＜ 0℃
V0(T) = V0(T24)+ (0-T)．M4 +( M5 + M6 + M7)．8
0℃ ℃ T ＜ 8℃
V0(T) = V0(T24)+ (8-T)．M5 +( M6 + M7)．8
8℃ ℃ T ＜ 16℃
V0(T) = V0(T24)+ (16-T)．M6 + M7．8
16℃ ℃ T ＜ 24℃
V0(T) = V0(T24)+ (24-T)．M7
24℃ ℃ T ＜ 32℃
V0(T) = V0(T24)－(T-24)．M8
32℃ ℃ T ＜ 40℃
V0(T) = V0(T24)－(T-32)．M9－M8．8
40℃ ℃ T ＜ 48℃
V0(T) = V0(T24)－(T-40)．M10－(M9 + M8 )．8
48℃ ℃ T ＜ 56℃
V0(T) = V0(T24)－(T-48)．M11－(M10 + M9 + M8 )．8
56℃ ℃ T ＜ 64℃
V0(T) = V0(T24)－(T-56)．M12－(M11 + M10 + M9 + M8 )．8
64℃ ℃ T ＜ 72℃
V0(T) = V0(T24)－(T-64)．M13－(M12 + M11 + M10 + M9 + M8 )．8
72℃ ℃ T ＜ 80℃
V0(T) = V0(T24)－(T-72)．M14－(M13 + M12 + M11 + M10 + M9 + M8 )．8
80℃ ℃ T ＜ 88℃
V0(T) = V0(T24)－(T-80)．M15－( M14 + M13 + M12 + M11 + M10 + M9 + M8 )．8
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ST7669
The Example of TC Function
(1) Setting example for default TC curve
COMMAND
0xF4
DATA
st
2 : 0x2F
nd
rd
4 : 0x35
th
6 : 0x40
th
8 : 0x13
1 : 0Xff
th
3 : 0x0A
th
5 : 0x31
th
7 : 0xA7
Vop=16.52 Bias=1/10, -0.14%
20.00
18.00
16.00
VOP
14.00
12.00
10.00
8.00
6.00
4.00
2.00
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temp.
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(2) Setting example for -0.06%/℃ TC curve
COMMAND
0xF4
DATA
st
2 : 0x05
nd
rd
4 : 0x05
th
6 : 0x05
th
8 : 0x05
1 : 0x05
th
3 : 0x05
th
5 : 0x05
th
7 : 0x05
Vop=16.52 Bias=1/10, -0.06%
20.00
18.00
16.00
VOP
14.00
12.00
10.00
8.00
6.00
4.00
2.00
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temp.
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(3) Setting example for -0.11%/℃ TC curve
COMMAND
0xF4
DATA
st
2 : 0x09
nd
rd
4 : 0x09
th
6 : 0x09
th
8 : 0x09
1 : 0x09
th
3 : 0x09
th
5 : 0x09
th
7 : 0x09
Vop=16.52 Bias=1/10, -0.11%
20.00
18.00
16.00
VOP
14.00
12.00
10.00
8.00
6.00
4.00
2.00
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temp.
V0 fine tuning
ST7669 has 2 commands for fine tuning V0. These commands are VopOfsetInc (see section 9.1.48) and
VopOfsetDec (see section 9.1.49 ). When writing VopOfsetInc into IC for each time, V0 would increase 40mV; when writing
VopOfsetDec into IC for each time, V0 would decrease 40mV.
Example:
Vop[8:0]=011010010
VopOffSet[7:0]=00111001
EV[6:0]=0111111
VopOfsetInc x2
→ V0=3.6 + { 210 + 57 + (63-63) } x 0.04 + 0.04x2 =14.36 (V)
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7.9.2
Voltage Follower Circuits
There is a build-in voltage follower circuits in ST7669 for generating Vg and Vm. These voltages are decided by bias
ratio selection circuitry which is set by users with software to control 1/5 to 1/14 bias ratios to match the optimum display
performance of LCD panel. Bias driving rule is listed below:
LCD bias
Vg
Vm
1/N bias
(2/N) x V0
(1/N) x V0
N=5 to 14
7.9.3
OTP Setting Flow
ST7669 provides the Write and Read function to write the electronic control value and built-in resistance ratio into
OTP (One-time programming register), and then read them from it. Using the Write and Read functions, you can store
these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel’s
voltage. But using this function must attention the setting procedure. Please see the following diagram.
Figure 7.9-2
OTP programming flow
Note1: This setting flow is used for LCM assembler.
Note2: OTP shouldn’t be written without preceding loading correctly from OTP in order to avoid some errors
during IC operation.
Note3: When writing to OTP, the voltage of VPP must be 7.50~7.75V; the current of Ivpp must be more than 4 mA.
Note4: If the OTP is exposed to a high temperature for hours, data in the memory cell may probably be lost before
the data retention guarantee period. To retain data in the memory cell, keep the memory cell below 90℃.
The data retention guarantee period is specified including the retention period.
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7.10 Frequency Temperature Gradient Compensation Coefficient
7.10.1 Register loading Detection
ST7669 will auto-switch frame rate on different temperature such as Figure 7.10-1. TA, TB and TC are frame rate
switching temperatures which can be defined by customer with command TMPRNG. FA, FB, FC and FD are switched
frame rate which also can be defined by customer with command FRMSEL. The frame rate range is from 37.5Hz to 170Hz.
When the temperature is in increasing state, frame rate changes to the higher step at TA/TB/TC+TH(℃). When the
temperature is in decreasing state, frame rate changes to the lower step at TA/TB/TC. For example: TC=10℃ and TH=5℃,
FC switches to FD at 15℃ but FD switches to FC at 10℃. Please take Figure 7.10-1 for reference.
Figure 7.10-1
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ST7669
7.11 Sleep Out –Command and Self-Diagnostic Functions of the Display Module
7.11.1 Register loading Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module loading
function of factory default values from OTP ROM (or similar device) to registers of the display controller is working properly.
There are compared factory values of the OTP ROM and register values of the display controller by the display
controller (1st step: compare register and OTP ROM values, 2nd step: loads OTP ROM values to registers). If those both
values (OTP ROM and register values) are same, bit-7 of RDDSDR is set to 1, which is defined in command RDDSDR
(The used bit of this command is D7). If those both values are not same, this bit (D7) is set to 0.The flow chart for this
internal function is following:
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7.11.2 Functionality Detection
Sleep Out-command is a trigger for an internal function of the display module.
The internal function (= the display controller) is comparing if the display module is still meeting functionality requirements
(e.g. booster voltage levels, timings, etc.). If functionality requirement is met, bit-6 of RDDSDR is set to 1, which defined in
command Read Display Self-Diagnostic Result (RDDSDR). The used bit of this command is D6. If functionality
requirement is not same, this bit (D6) is set to 0.
The flow chart for this internal function is following:
Note: There is needed 200msec after Sleep Out -command, when there is changing from Sleep In –mode to
Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise,
there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode.
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7.11.3 Chip Attachment Detection (Reserved)
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if bump side of IC is
attached to LCM glass ITO or not.
There is a bit, which is defined in command “Read Display Self-Diagnostic Result” (RDDSDR). The used bit of this
command is D5. If IC is not attached to the circuit route of the flex or display glass, this bit (D5) is “0”. If IC is attached to the
circuit route, the bit5 is “1”.
There are connected together 2 bumps via route of ITO on 4 corners of IC. TLBI connects to TLBO; TLUI connects to
TLUO; TRUI connects to TRUO; TRBI connects to TRBO.
7.11.4 LCM Glass Detection (Reserved)
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display glass of
the display module is broken or not.
There is a bit, which is defined in command “Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR).The used bit of
this command is D4. If this display glass is broken, this bit (D4) is “0”. If this display glass is OK, this bit (D4) is “1”.
The following figure is a reference of how this glass break detection can be implemented. For example, there is
connected together 2 bumps(TGI and TGO) via route of ITO. This route of ITO is the nearest route of the edge of the
display glass.
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8 RESET CIRCUIT
The registers that are initialized are listed below.
Item
After Power On
After Hardware Reset
After Software Reset
Frame memory (RAM data)
Random
No Change
No Change
RDDID
TBD
TBD
TBD
RDDPM
08h
08h
08h
RDDMADCTR
00h
00h
No Change
RDDCOLMOD
06h (18-Bit/Pixel)
06h (18-Bit/Pixel)
No Change
RDDIM
00h
00h
00h
RDDSM
00h
00h
00h
RDDSDR
00h
00h
00h
Sleep In/Out
In
In
In
Display mode (normal/partial)
Normal
Normal
Normal
Display Inversion On/Off
Off
Off
Off
All Pixel Off mode
Disable
Disable
Disable
All Pixel On mode
Disable
Disable
Disable
Contrast (EV)
3Fh
3Fh
3Fh
Display On/Off
Display Off
Display Off
Display Off
Column: Start Address (XS)
00h
Column: End Address (XE)
83h
00h
83h
00h
83h (when MV=0)
A1h (when MV=1)
Row: Start Address (YS)
00h
Row: End Address (YE)
A1h
00h
A1h
00h
A1h (when MV=0)
83h (when MV=1)
Color set
Random
Random
Contents of the look-up
table protected
Partial: Start Address (PS)
00h
00h
00h
Partial: End Address (PE)
A1h
A1h
A1h
Scroll: Top Fixed Area (TFA)
00h
00h
00h
Scroll: Scroll Area (VSA)
A2h
A2h
A2h
Scroll: Bottom Fixed Area (BFA)
00h
00h
00h
TE On/Off
Off
Off
Off
TE Mode
Memory Data Access Control
MY/MX/MV/ML/RGB)
0 (Mode1)
0 (Mode1)
0 (Mode1)
0/0/0/0/0
No Change
No Change
Scroll Start Address (SSA)
00h
00h
00h
Idle Mode On/Off
Off
Off
Off
Interface Color Pixel Format (P)
06h (18Bit/Pixel)
06h (18Bit/Pixel)
No change
ID1
TBD
TBD
TBD
ID2
TBD
TBD
TBD
ID3
TBD
TBD
TBD
Drive Duty
A1h
A1h
A1h
First Common
00h
00h
00h
FOSC Divider
No division
No division
No division
Common scan direction
0→80, 81→161
0→80, 81→161
0→80, 81→161
Vop
042h, 01h
042h, 01h
042h, 01h
Vop Offset increase/decrease
Disable
disable
disable
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ST7669
Item
After Power On
After Hardware Reset
After Software Reset
Bias
1/11 Bias
1/11 Bias
1/11 Bias
Booster setting
8x
8x
8x
Booster Efficiency
01b
01b
01b
Vg source
From VDD2x2
From VDD2x2
From VDD2x2
EPCTIN
0
0
0
OTP selection
Disable
Disable
Disable
Frame Frequency in Normal Color
46Hz/61.5Hz/72Hz/77Hz
46Hz/61.5Hz/72Hz/77Hz
46Hz/61.5Hz/72Hz/77Hz
46Hz/61.5Hz/72Hz/77Hz
46Hz/61.5Hz/72Hz/77Hz
46Hz/61.5Hz/72Hz/77Hz
10℃/10℃/10℃
10℃/10℃/10℃
10℃/10℃/10℃
Temperature Hysteresis (TH)
5℃
5℃
5℃
TEMPSEL
0 mV/℃
0 mV/℃
0 mV/℃
(FA/FB/FC/FD)
Frame Frequency in 8-Color (Idle)
(F8A/F8B/F8C/F8D)
Temperature Range
(TA/TB/TC)
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ST7669
9
COMMANDS
9.1 INSTRUCTION TABLE
Command Table-1 , /EXT= H or L
Hex
Command
A0
/RD /WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Ref
(00h) NOP
0
1
0
0
0
0
0
0
0
0
0
No Operation
9.1.1
(01h) SWRESET
0
1
0
0
0
0
0
0
0
0
1
Software reset
9.1.2
(04h) RDDID
0
1
0
0
0
0
0
0
1
0
0
Read Display ID
9.1.3
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
-
1
0
1
-
1
0
1
0
1
0
0
0
0
0
1
0
0
1
Read Display Status
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 (D31-D24)
-
1
0
1
ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 (D23-D16)
-
1
0
1
ST15 ST14 ST13 ST12 ST11 ST10 ST9
ST8 (D15-D8)
-
1
0
1
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0 (D7-D0)
0
1
0
0
0
0
0
1
0
1
0
Read Display Power Mode
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
D7
D6
D5
D4
D3
D2
0
0
-
0
1
0
0
0
0
0
1
0
1
1
Read Display MADCTR
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
D7
D6
D5
D4
D3
0
0
0
-
0
1
0
0
0
0
0
1
1
0
0
Read Display Pixel Format
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
0
0
0
0
0
D2
D1
D0
0
1
0
0
0
0
0
1
1
0
1
Read Display Image Mode
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
D7
0
D5
D4
D3
0
0
0
-
0
1
0
0
0
0
0
1
1
1
0
Read Display signal Mode
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
D7
D6
0
0
0
0
0
0
-
0
1
0
0
0
0
0
1
1
1
1
1
0
1
-
-
-
-
-
-
-
-
Dummy read
1
0
1
D7
D6
D5
D4
0
0
0
0
-
(09h) RDDST
(0Ah) RDDPM
(0Bh) RDDMADCTR
(0Ch) RDDCOLMOD
(0Dh) RDDIM
(0Eh) RDDSM
(0Fh) RDDSDR
-
Ver 1.3a
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read (D23-D16)
1
ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read (D15-D8)
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ID3 read (D7-D0)
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9.1.4
9.1.5
9.1.6
9.1.7
-
Read Display Self-diagnostic result
9.1.8
9.1.9
9.1.10
3/2/2009
ST7669
Hex
Command
A0
/RD /WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Ref
(10h) SLPIN
0
1
0
0
0
0
1
0
0
0
0
Sleep in & booster off
9.1.11
(11h) SLPOUT
0
1
0
0
0
0
1
0
0
0
1
Sleep out & booster on
9.1.12
(12h) PTLON
0
1
0
0
0
0
1
0
0
1
0
Partial mode on
9.1.13
(13h) NORON
0
1
0
0
0
0
1
0
0
1
1
Partial off (Normal)
9.1.14
(20h) INVOFF
0
1
0
0
0
1
0
0
0
0
0
Display inversion off (normal)
9.1.15
(21h) INVON
0
1
0
0
0
1
0
0
0
0
1
Display inversion on
9.1.16
(22h) APOFF
0
1
0
0
0
1
0
0
0
1
0
All pixel off (Only for test purpose)
9.1.17
(23h) APON
0
1
0
0
0
1
0
0
0
1
1
All pixel on (Only for test purpose)
9.1.18
(25h) WRCNTR
0
1
0
0
0
1
0
0
1
0
1
Write contrast
9.1.19
1
1
0
0
EV6
EV5
EV4
EV3
EV2
EV1
(28h) DISPOFF
0
1
0
0
0
1
0
1
0
0
0
Display off
9.1.20
(29h) DISPON
0
1
0
0
0
1
0
1
0
0
1
Display on
9.1.21
(2Ah) CASET
0
1
0
0
0
1
0
1
0
1
0
Column address set
9.1.22
1
1
0
XS15 XS14 XS13 XS12 XS11 XS10 XS9
XS8 X_ADR start: 0℃XS℃83h
1
1
0
XS7
XS0
1
1
0
XE15 XE14 XE13 XE12 XE11 XE10 XE9
XE8 X_ADR end: XS℃XE ℃83h
1
1
0
XE7
XE6
XE5
XE4
XE3
XE2
XE1
XE0
0
1
0
0
0
1
0
1
0
1
1
1
1
0
YS15 YS14 YS13 YS12 YS11 YS10 YS9
YS8 Y_ADR start: 0℃YS℃A1h
1
1
0
YS7
YS0
1
1
0
YE15 YE14 YE13 YE12 YE11 YE10 YE9
YE8 Y_ADR end: YS℃YE℃A1h
1
1
0
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
1
1
0
1
-
1
1
0
-
-
R5
R4
R3
R2
R1
R0
-
1
1
0
:
:
:
:
:
:
:
:
-
1
1
0
-
-
R5
R4
R3
R2
R1
R0
Red tone (11111)
-
1
1
0
-
-
G5
G4
G3
G2
G1
G0
Green tone (000000)
1
1
0
:
:
:
:
:
:
:
:
1
1
0
-
-
G5
G4
G3
G2
G1
G0
Green tone (111111)
1
1
0
-
-
B5
B4
B3
B2
B1
B0
Blue tone (00000)
1
1
0
:
:
:
:
:
:
:
:
1
1
0
-
-
B5
B4
B3
B2
B1
B0
-
(2Bh) RASET
(2Ch) RAMWR
(2Dh) RGBSET
Ver 1.3a
XS6
YS6
XS5
YS5
XS4
YS4
XS3
YS3
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XS2
YS2
XS1
YS1
EV0 EV = 0 to 127
Row address set
9.1.23
Memory write
9.1.24
Write data
Color set for 256.4k.65K color display
9.1.25
Red tone (00000)
:-
:-
:Blue tone (11111)
3/2/2009
ST7669
Hex
Command
A0
/RD /WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Ref
0
1
0
0
0
1
0
1
1
1
0
1
1
0
-
-
-
-
-
-
-
-
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
PS15 PS14 PS13 PS12 PS11 PS10 PS9
PS8 Start address (0~161)
1
1
0
PS7
PS0
1
1
0
PE15 PE14 PE13 PE12 PE11 PE10 PE9
PE8 End address (0~161)
1
1
0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
0
1
0
0
0
1
1
0
0
1
1
-
1
1
0
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 TFA=0~162
-
1
1
0
VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 VSA=0~162
-
1
1
0
BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 BFA=0~162
(34h) TEOFF
0
1
0
0
0
1
1
0
1
0
0
Tearing effect line off
9.1.29
(35h) TEON
0
1
0
0
0
1
1
0
1
0
1
Tearing effect mode set & on
9.1.30
1
1
0
-
-
-
-
-
-
-
M
“0”: mode1, “1”: mode2
0
1
0
0
0
1
1
0
1
1
0
Memory data access control
1
1
0
MY
MX
MV
-
-
-
-
0
1
0
0
0
1
1
1
1
Scroll start address of RAM
1
1
0
(38h) IDMOFF
0
1
0
0
0
1
1
1
0
0
0
Idle mode off
9.1.33
(39h) IDMON
0
1
0
0
0
1
1
1
0
0
1
Idle mode on
9.1.34
(3Ah) COLMOD
0
1
0
0
0
1
1
1
0
1
0
Interface pixel format
9.1.35
1
1
0
-
-
-
-
-
P2
P1
P0
0
1
0
1
1
0
1
1
0
1
0
Read ID1
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
0
1
0
1
1
0
1
1
0
1
0
Read ID2
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
0
1
0
1
1
0
1
1
0
1
0
Read ID3
-
1
0
1
-
-
-
-
-
-
-
-
Dummy read
-
1
0
1
(2Eh) RAMRD
(30h) PTLAR
-
(33h) SCRLAR
(36h) MADCTR
(37h) VSCSAD
(DAh) RDID1
(DBh) RDID2
(DCh) RDID3
PS6
PS5
PS4
PS3
ML RGB
1
0
PS2
PS1
Memory Read
9.1.26
Partial start/end address set
9.1.27
Scroll Area
9.1.28
9.1.31
9.1.32
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 SSA = 0~161
Interface format
9.1.36
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 (D7-D0)
9.1.37
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 (D7-D0)
9.1.38
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 (D7-D0)
Note 1: When /EXT connects to H or floating, commands which are not defined in “Command Table-1” are treated as NOP (00H)
command.
Note 2: Commands 10H, 12H, 13H, 20H, 21H, 25H, 28H, 29H, 30H, 36H (Bit ML only), 38H and 39H are updated during V-sync when
Ver 1.3a
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ST7669
Module is in Sleep Out Mode to avoid abnormal visual effects.
During Sleep In mode, these commands are updated immediately.
Read status (09H), Read Display Power Mode (0AH), Read Display MADCTR (0BH), Read Display Pixel Format (0CH), Read Display
Image Mode (0DH), Read Display Signal Mode (0EH) and Read Display Self Diagnostic Result (0FH) of these commands is updated
immediately both in Sleep In mode and Sleep Out mode.
Ver 1.3a
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Command Table-2 , /EXT= L
Hex Command
(B0h) DutySet
(B1h) FirstCom
(B3h) OscDiv
(B4h) PTLMOD
A0
/RD /WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
1
1
0
0
0
1
1
1
0
F7
F6
F5
F4
F3
F2
F1
F0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
-
-
-
-
-
-
0
1
0
1
0
1
1
0
1
Function
Ref
Display Duty setting
9.1.39
First Com. Page address
9.1.40
FOSC divider
9.1.41
Saving Power Mode
9.1.42
Du7 Du6 Du5 Du4 Du3 Du2 Du1 Du0
CLD1 CLD0
0
0
Selection
(B5h) NLInvSet
(B7h) ComScanDir
1
1
0
PTLM
0
0
1
1
0
0
0
0
1
0
1
0
1
1
0
1
0
1
1
1
0
M
N6
N5
N4
N3
N2
N1
N0
0
1
0
1
0
1
1
0
1
1
1
N-line control
9.1.43
Com/Seg Scan Direction
9.1.44
for Glass layout
1
1
0
0
1
0
SMY SMX SINV SML
SBGR
0
0
0
1
0
0
0
read modify write control
(B8h) RmwIn
1
0
1
1
9.1.45
IN
read modify write control
(B9h) RmwOut
0
1
0
1
0
1
1
1
0
0
9.1.46
1
Out
0
1
0
1
1
0
1
1
0
-
-
-
-
-
-
-
Vop8
(C1h) VopOfsetInc
0
1
0
1
1
0
0
0
0
0
(C2h) VopOfsetDec
0
1
0
1
1
0
0
0
0
(C3h) BiasSel
0
1
0
1
1
0
0
0
0
1
1
0
-
-
-
-
-
0
1
0
1
1
0
0
0
1
1
0
-
-
-
-
-
0
1
0
1
1
0
0
0
(C0h) VopSet
(C4h) BstBmpXSel
(C5h) BstEffSel
1
1
0
0
0
0
0
0
Vop setting
9.1.47
1
+40mv/setp
9.1.48
1
0
-40mv/setp
9.1.49
1
1
Bias selection
9.1.50
Booster setting
9.1.51
Booster efficiency
9.1.52
Vop7 Vop6 Vop5 Vop4 Vop3 Vop2 Vop1 Vop0
Bias2 Bias1 Bias0
1
0
0
BST2 BST 1 BST0
1
0
1
selection
(C7h) VopOffset
(CBh) VgSorcSel
Ver 1.3a
1
1
0
-
-
1
0
-
-
BTF1 BTF0
0
1
0
1
1
0
0
0
1
1
1
0
1
1
0
-
-
-
-
-
-
-
VOS8
0
1
0
1
1
0
0
1
0
1
1
1
1
0
-
-
-
-
-
-
-
2BT0
1
1
Vop offset fuse bit adjust
9.1.53
Vg with Booster x2 control
9.1.54
VOS7 VOS6 VOS5 VOS4 VOS3 VOS2 VOS1 VOS0
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Hex Command
(CCh) ID1Set
(CDh) ID2Set
(CEh) ID3Set
(D0h) ANASET
(D7h) AutoLoadSet
A0
/RD /WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
1
0
0
0
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
1
0
1
1
1
Function
Ref
ID1 setting
9.1.55
ID2 setting
9.1.56
ID3 setting
9.1.57
Analog circuit setting
9.1.58
mask rom data auto re-load
9.1.59
ID1_7 ID1_6 ID1_5 ID1_4 ID1_3 ID1_2 ID1_1 ID1_0
1
0
0
1
1
0
1
ID2_6 ID2_5 ID2_4 ID2_3 ID2_2 ID2_1 ID2_0
1
0
0
1
1
1
0
ID3_7 ID3_6 ID3_5 ID3_4 ID3_3 ID3_2 ID3_1 ID3_0
control
(DEh) RDTstStatus
(E0h) EPCTIN
1
1
0
EXTE
1
-
ARD
1
1
1
1
0
1
0
1
1
0
1
1
1
1
0
read IC status
1
0
1
-
-
-
-
-
-
-
-
Dummy Read
0
1
0
1
1
1
0
0
0
0
0
Control OTP WR/RD
9.1.61
WR
0
0
0
0
0
1
1
0
0
0
9.1.60
/XRD
(E1h) EPCTOUT
0
1
0
1
1
1
0
0
0
0
1
OTP control cancel
9.1.62
(E2h) EPMWR
0
1
0
1
1
1
0
0
0
1
0
Write to OTP
9.1.63
(E3h) EPMRD
0
1
0
1
1
1
0
0
0
1
1
Read from OTP
9.1.64
(E4h) OTPSEL
0
1
0
1
1
1
0
0
1
0
0
Select OTP
9.1.65
1
1
0
0
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
Programmable rom setting
9.1.66
1
1
0
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
1
High power mode setting
9.1.67
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
Frame Freq Temp range
9.1.68
0
1
0
1
1
1
1
0
0
0
0
(E5h) ROMSET
(EBh) HPMSET
(F0h) FRMSEL
MS1 MS0
HP1 HP0
A,B,C and D
Ver 1.3a
1
1
0
-
-
-
FA4
FA3 FA2 FA1
1
1
0
-
-
-
FB4 FB3 FB2 FB1 FB0
1
1
0
-
-
-
FC4 FC3 FC2 FC1 FC0
1
1
0
-
-
-
FD4 FD3 FD2 FD1 FD0
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FA0
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ST7669
Hex Command
A0
/RD /WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
0
1
Function
Ref
Frame Freq Temp range
(F1h) FRM8SEL
0
1
0
9.1.69
A,B,C and D (idle)
(F2h) TMPRNG
(F3h) TMPHYS
(F4h) TEMPSEL
(F7h) THYS
1
1
0
-
-
-
F8A4 F8A3 F8A2 F8A1 F8A0
1
1
0
-
-
-
F8B4 F8B3 F8B2 F8B1 F8B0
1
1
0
-
-
-
F8C4 F8C3 F8C2 F8C1 F8C0
1
1
0
-
-
-
F8D4 F8D3 F8D2 F8D1 F8D0
0
1
0
1
1
1
1
0
0
1
0
1
1
0
-
TA6
TA5
TA4
TA3
TA2
TA1
TA0
1
1
0
-
TB6 TB5 TB4 TB3 TB2 TB1 TB0
1
1
0
-
TC6 TC5 TC4 TC3 TC2 TC1 TC0
0
1
0
1
1
1
1
1
1
0
-
-
-
-
0
1
0
1
1
1
1
1
1
0
MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00
1
1
0
MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20
1
1
0
MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40
1
1
0
MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60
1
1
0
MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80
1
1
0
MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0
1
1
0
MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0
1
1
0
MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0
0
1
0
1
1
1
0
0
1
1
Temp range A,B and C
9.1.70
Hysteresis value set
9.1.71
TEMPSEL
9.1.72
Temperature detection
9.1.73
TH3 TH2 TH1 TH0
0
1
0
1
1
0
1
0
1
threshold
1
1
0
0
1
0
THYS7 THYS6 THYS5 THYS4 THYS3 THYS2 THYS1 THYS0
Set Frame RGB PWM
(F9h) Frame Set
1
1
1
1
1
0
0
9.1.74
1
value
Ver 1.3a
1
1
0
-
-
-
P14
P13 P12 P11
P10
1
1
0
-
-
-
P24
P23 P22 P21
P20
:
:
:
:
:
:
:
1
1
0
-
-
-
P154 P153 P152 P151 P150
1
1
0
-
-
-
P164 P163 P162 P161 P160
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:
:
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ST7669
9.1.1
NOP: No Operation (00H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
0
0
0
0
0
0
00H
Parameter
No parameter
This command is an empty command; it does not have any effect on the display module.
Description
However it can be used to terminate Frame Memory Write or Read as described in
RAMWR (Memory Write) and RAMRD (Memory Read) Commands.
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Register
Normal Mode On, Idle Mode On, Sleep Out
Yes
Availablility
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
N/A
S/W Reset
N/A
H/W Reset
N/A
Flow Chart
Ver 1.3a
73/216
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ST7669
9.1.2
SWRESET: Software Reset (01H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
0
0
0
0
0
1
01H
Parameter
No parameter
When the Software Reset command is written, it causes a software reset. It resets the commands and
parameters to their S/W Reset default values and all segment & common outputs are set to Vm (display
Description
off: blank display). (See default tables in each command description)
Note: The Frame Memory contents are unaffected by this command
It will be necessary to wait 5msec before sending new command following software reset.
The display module loads all display supplier’s factory default values to the registers during 5msec.
Restriction
If Software Reset is applied during Sleep Out mode, it will be necessary to wait 200msec before
sending Sleep Out command.
Software Reset command cannot be sent during Sleep Out sequence.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Register
Normal Mode On, Idle Mode On, Sleep Out
Yes
Availablility
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
N/A
S/W Reset
N/A
H/W Reset
N/A
74/216
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Flow Chart
Ver 1.3a
75/216
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ST7669
9.1.3
RDDIDIF: Read Display Identification Information (04H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
0
1
0
0
04H
Dummy Read
1
0
1
-
-
-
-
-
-
-
-
-
parameter
1
0
1
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
-
3 parameter
rd
1
0
1
1
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-
th
1
0
1
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
-
2
nd
4 parameter
This read byte returns 24-bit display identification information.
1st Parameter: dummy read.
The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.
Description
The 3rd parameter (ID26 to ID20): LCD module/driver version ID
The 4th parameter (ID37 to ID30): LCD module/driver ID.
NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the
command 04h, respectively.
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Register
Normal Mode On, Idle Mode On, Sleep Out
Yes
Availablility
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default
Ver 1.3a
Default Value
ID1
ID2
ID3
Power On Sequence
Not fixed
Not fixed
Not fixed
S/W Reset
Not fixed
Not fixed
Not fixed
H/W Reset
Not fixed
Not fixed
Not fixed
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Flow Chart
Ver 1.3a
77/216
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ST7669
9.1.4
RDDST: Read Display Status (09H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
0
0
1
09H
Dummy Read
1
0
1
-
-
-
-
-
-
-
-
-
parameter
1
0
1
ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24
-
3 parameter
rd
1
0
1
ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16
-
th
1
0
1
ST15 ST14 ST13 ST12 ST11 ST10
ST9
ST8
-
th
1
0
1
ST7
ST1
ST0
-
2
nd
4 parameter
5 parameter
ST6
ST5
ST4
ST3
ST2
NOTE: “-“ Don’t care
Description
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
ST31
Booster Voltage Status
“1”=Booster on (Booster is OK), “0”=off
ST30
Row Address Order (MY)
“1”=Decrement, “0”=Increment
ST29
Column Address Order (MX)
“1”=Decrement, “0”=Increment
ST28
Row/Column Order (MV)
“1”= Row/column exchange (MV=1)
“0”= Normal (MV=0)
ST27
Scan Address Order (ML)
“1”=Decrement, “0”=Increment
ST26
RGB/BGR Order (RGB)
“1”=BGR, “0”=RGB
ST25
Not Used
“0”
ST24
Not Used
“0”
ST23
Not Used
Interface Color Pixel Format
Definition
“0”
“010” = 8-bit / pixel,
“011” = Reserve
“100” = 12-bit / pixel
“101” = 16-bit / pixel,
“110” = 18-bit / pixel,
“111” = 24-bit / pixel
ST19
Idle Mode On/Off
“1” = On, “0” = Off
ST18
Partial Mode On/Off
“1” = On, “0” = Off
ST17
Sleep In/Out
“1” = Out, “0” = In
ST16
Display Normal Mode On/Off
“1” = Normal Display, “0” = Partial Display
ST15
Vertical Scrolling Status
“1” = Scroll on, “0” = Scroll off
ST14
Not Used
“0”
ST13
Inversion Status
“1” = On, “0” = Off
ST12
All Pixels On
“1” = mode On, “0” = mode Off
ST11
All Pixels Off
“1” = mode On, “0” = mode Off
ST10
Display On/Off
“1” = On, “0” = Off
ST9
Tearing effect line on/off
“1” = On, “0” = Off
ST8
Not Used
“0”
ST7
Not Used
“0”
ST6
Not Used
“0”
ST5
Tearing effect line mode
“0” = mode1, “1” = mode2
ST4
Not Used
“0”
ST3
Not Used
“0”
ST2
Not Used
“0”
ST22
ST21
ST20
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ST1
Not Used
“0”
ST0
Not Used
“0”
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
0000 0000_0101 0001_0000 0000_0000 0000
S/W Reset
0xxx xx00_0xxx 0001_0000 0000_0000 0000
H/W Reset
0000 0000_0101 0001_0000 0000_0000 0000
Flow Chart
Ver 1.3a
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9.1.5
RDDPM:Read Display Power Mode (0AH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
0
1
0
0AH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
D7
D6
D5
D4
D3
D2
0
0
-
1 parameter
2
nd
parameter
Description
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
D7
Booster Voltage Status
“1”=Booster on, “0”=Booster off
D6
Idle Mode On/Off
“1” = Idle Mode On, “0” = Idle Mode Off
D5
Partial Mode On/Off
“1” = Partial Mode On, “0” = Partial Mode
D4
Sleep In/Out
“1” = Sleep Out, “0” = Sleep In
D3
Display Normal Mode On/Off
“1” = Normal Display, “0” = Partial Display
D2
Display On/Off
“1” = Display On, “0” = Display Off
D1
Not Used
“0”
D0
Not Used
“0”
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value (D7 to D0)
Power On Sequence
0000_1000 (08h)
S/W Reset
0000_1000 (08h)
H/W Reset
0000_1000 (08h)
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Ver 1.3a
81/216
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ST7669
9.1.6
RDDMADCTL:Read Display MADCTL (0BH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
0
1
1
0BH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
D7
D6
D5
D4
D3
0
0
0
-
1 parameter
2
nd
parameter
NOTE: “-“ Don’t care
Description
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
D7
Row Address Order (MY)
“1”=Decrement, “0”=Increment
D6
Column Address Order (MX)
D5
Row/Column Order (MV)
“1”=Decrement, “0”=Increment
“1”= Row/column exchange (MV=1)
“0”= Normal (MV=0)
D4
Scan Address Order (ML)
“1”=Decrement, “0”=Increment
D3
RGB/BGR Order (RGB)
“1”=BGR, “0”=RGB
D2
Not Used
“0”
D1
Not Used
“0”
D0
Not Used
“0”
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value (D7 to D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
No change
H/W Reset
0000_0000 (00h)
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Ver 1.3a
83/216
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9.1.7
RDDCOLMOD: Read Display Pixel Format (0CH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
1
0
0
0CH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
0
0
0
0
0
D2
D1
D0
-
1 parameter
2
nd
parameter
NOTE: “-“ Don’t care
Description
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
D7
RGB Interface Color Format
“0” (Not Used)
D6
“0” (Not Used)
D5
“0” (Not Used)
D4
D3
“0” (Not Used)
Control Interface Color Format
D2
D1
D0
“0”
“010”=8 bit/pixel
“011”=Reserve
“100”=12 bit/pixel
“101”=16 bit/pixel
“110”=18 bit/pixel
“110”=24 bit/pixel
The others = not defined
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value (D7 to D0)
Power On Sequence
18 bit/pixel
S/W Reset
No change
H/W Reset
18 bit/pixel
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Ver 1.3a
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9.1.8
RDDIM: Read Display Image Mode (0DH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
1
0
1
0DH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
D7
0
D5
D4
D3
0
0
0
-
1 parameter
2
nd
parameter
Description
This command indicates the current status of the display as described in the table below:
Bit
D7
D6
D5
D4
D3
Description
Command
0
Vertical scrolling off
1
Vertical scrolling is On,
0
No used
1
No used
0
Inversion is Off
1
Inversion is On
0
Normal Mode
1
All Pixels are on
0
Normal Mode
1
All Pixels are off
0
No used
Vertical Scrolling On/Off
Horizontal Scrolling On/Off
Inversion On/Off
All Pixels On
All Pixels Off
D2
D1
Gamma Curve Selection
D0
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value (D7 to D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
0000_0000 (00h)
H/W Reset
0000_0000 (00h)
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Ver 1.3a
87/216
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ST7669
9.1.9
RDDCOLMOD: Read Display Signal Mode (0EH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
1
1
0
0EH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
D7
D6
0
0
0
0
0
0
-
1 parameter
2
nd
parameter
Description
This command indicates the current status of the display as described in the table below:
Command
Bit
Description
D7
Tearing Effect Line On/Off
D6
Tearing Effect Line Output Mode
0
Tearing Effect Line Off.
1
Tearing Effect On.
0
Mode 1
1
Mode 2
D5
Horizontal Sync. (RGB I/F) On/Off
“0” (Not Used)
D4
Vertical Sync. (RGB I/F) On/Off
“0” (Not Used)
D3
Pixel Clock (DCK, RGB I/F) On/Off
“0” (Not Used)
D2
Data Enable (ENABLE, RGB I/F) On/Off
“0” (Not Used)
D1
Not Used
“0”
D0
Not Used
“0”
Restriction
Register
Availablilit
Status
Availability
y
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value (D7 to D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
0000_0000 (00h)
H/W Reset
0000_0000 (00h)
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Flow Chart
Ver 1.3a
89/216
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ST7669
9.1.10 RDDSDR: Read Display Self-Diagnostic Result (0FH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
0
0
1
1
1
1
0FH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
D7
D6
D5
D4
0
0
0
0
-
1 parameter
2
nd
parameter
NOTE: “-“ Don’t care
Description
This command indicates the current status of the display as described in the table below:
Bit
Description
Command
D7
Register Loading Detection
D6
Functionality Detection
D5
Chip Attachment Detection
D4
LCM Glass Direction
D3
Not Used
“0”
D2
Not Used
“0”
D1
Not Used
“0”
D0
Not Used
“0”
See section 7.12.1 , 7.12.2 , 7.12.3
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value (D7 to D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
0000_0000 (00h)
H/W Reset
0000_0000 (00h)
Flow Chart
Ver 1.3a
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Flow Chart
Ver 1.3a
91/216
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9.1.11 SLPIN : Sleep In(10H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
0
1
0
0
0
0
10H
Parameter
Description
No parameter
This command causes the LCD module to enter the minimum power consumption mode.
In this mode the DC/DC converter, Internal oscillator, and panel scanning are all stopped.
MCU interface and memory are still working and the memory keeps its contents.
Restriction
This command has no effect when module is already in sleep in mode. Sleep In Mode can only be left
by the Sleep Out Command (11h).
It will be necessary to wait 5msec before sending next command, this is to allow time for the supply
voltages and clock circuits to stabilise.
It will be necessary to wait 200msec after sending Sleep Out command (when in Sleep In Mode)
before Sleep In command can be sent.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Sleep In Mode
S/W Reset
Sleep In Mode
H/W Reset
Sleep In Mode
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Flow Chart
It takes about 200 msec to get into Sleep In mode (booster off state) after SLPIN command issued.
The results of booster off can be check by RDDST (09h) command Bit31.
Ver 1.3a
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9.1.12 SLPOUT: Sleep Out (11H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
0
1
0
0
0
1
11H
Parameter
Description
No parameter
This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal oscillator is
started, and panel scanning is started.
Restriction
This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be
left by the Sleep In Command (10h).
It will be necessary to wait 5msec before sending next command, this is to allow time for the supply
voltages and clock circuits to stabilise.
The display module loads all display supplier’s factory default values to the registers during this 5msec
and there cannot be any abnormal visual effect on the display image if factory default and register
values are same when this load is done and when the display module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec..
It will be necessary to wait 200msec after sending Sleep In command (when in Sleep Out mode) before
Sleep Out command can be sent.
Register
Availablility
Ver 1.3a
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
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Default
Flow Chart
Status
Default Value
Power On Sequence
Sleep In Mode
S/W Reset
Sleep In Mode
H/W Reset
Sleep In Mode
It takes 200msec to become Sleep Out mode (booster on mode) after SLPOUT command issued.
The results of booster on can be check by RDDST (09h) command Bit31.
Ver 1.3a
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9.1.13 PTLON : Partial Mode On (12H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
0
1
0
0
1
0
12H
Parameter
Description
No parameter
This command turns on partial mode The partial mode window is described by the Partial Area
command (30H).
Exit from PTLON by Normal Display Mode On command (13H)
There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On.
Restriction
This command has no effect when Partial mode is active.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Flow Chart
Ver 1.3a
Status
Default Value
Power On Sequence
Partial mode off
S/W Reset
Partial mode off
H/W Reset
Partial mode off
See Partial Area (30h)
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9.1.14 NORON: Normal Display Mode On (13H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
0
1
0
0
1
1
13H
Parameter
Description
No parameter
This command returns the display to normal mode.
Normal display mode on means Partial mode off.
Exit from NORON by the Partial mode On command (12h)
There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On.
Restriction
This command has no effect when Normal Display mode is active.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Flow Chart
Status
Default Value
Power On Sequence
Normal Mode On
S/W Reset
Normal Mode On
H/W Reset
Normal Mode On
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this
command
Ver 1.3a
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9.1.15 INVOFF: Display Inversion Off (20H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
0
0
0
0
0
20H
Parameter
Description
No parameter
This command is used to recover from display inversion mode.
This command makes no change of contents of frame memory.
This command does not change any other status.
Restriction
This command has no effect when IC is already in inversion off mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Display Inversion Off
S/W Reset
Display Inversion Off
H/W Reset
Display Inversion Off
98/216
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Flow Chart
Ver 1.3a
99/216
3/2/2009
ST7669
9.1.16 INVON: Display Inversion On (21H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
0
0
0
0
1
21H
Parameter
Description
No parameter
This command is used to enter into display inversion mode.
This command makes no change of contents of frame memory. Every bit is inverted from the frame
memory to the display. This command does not change any other status.
Restriction
This command has no effect when IC is already in inversion on mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Display Inversion Off
S/W Reset
Display Inversion Off
H/W Reset
Display Inversion Off
100/216
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Flow Chart
Ver 1.3a
101/216
3/2/2009
ST7669
9.1.17 ALLPOFF : ALL Pixels Off (22H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
0
0
0
1
0
22H
Parameter
Description
No parameter
This command is only used for test purposes e.g. pixel response time (on/off) measurements on the
passive matrix display. Therefore, it is possible that this command is not used for final product software.
There is not used PWM or Mixed FRC/PWM driving method on the display.
All driver outputs become “Low” data state and display becomes black.
This command makes no change of contents of display memory.
This command does not change any other status.
Exit commands are “All Pixels On”, “Normal Display Mode On” and “Partial Display On”.
The display is showing the contents of the frame memory after “Normal Display Mode On” and “Partial
Display On” commands.
Restriction
This command has no effect when IC is already in all pixels off mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
All pixel off mode disable
S/W Reset
All pixel off mode disable
H/W Reset
All pixel off mode disable
102/216
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Flow Chart
Ver 1.3a
103/216
3/2/2009
ST7669
9.1.18 ALLPON: All Pixels On (23H) (Only for Test Purposes)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
0
0
0
1
1
23H
Parameter
Description
No parameter
This command is only used for test purposes e.g. pixel response time (on/off) measurements on the
passive matrix display. Therefore, it is possible that this command is not used for final product software.
There is not used PWM or Mixed FRC/PWM driving method on the display.
All driver outputs become “High” data state and display becomes white.
This command makes no change of contents of display memory.
This command does not change any other status.
Exit commands are “All Pixels On”, “Normal Display Mode On” and “Partial Display On”.
The display is showing the contents of the frame memory after “Normal Display Mode On” and “Partial
Display On” commands.
Restriction
This command has no effect when IC is already in all pixels on mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
All pixel on mode disable
S/W Reset
All pixel on mode disable
H/W Reset
All pixel on mode disable
104/216
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Flow Chart
Ver 1.3a
105/216
3/2/2009
ST7669
9.1.19 WRCNTR: Write Contrast (25H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
0
0
1
0
1
25H
Parameter
1
1
0
0
EV6
EV5
EV4
EV3
EV2
EV1
EV0
00H~7FH
Description
This command is used to fine tuning the contrast of the current display.
This contrast values can effect segment and common outputs.
Parameter range: 0-127dec. MSB is EV6 and LSB is EV0.
Default value: 63dec (3Fh)
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
3Fh
S/W Reset
3Fh
H/W Reset
3Fh
Flow Chart
Ver 1.3a
106/216
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ST7669
9.1.20 DISPOFF: Display Off (28H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
0
1
0
0
0
28H
Parameter
Description
No parameter
This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory
is disabled and blank page inserted.
This command makes no change of contents of frame memory.
This command does not change any other status.
There will be no abnormal visible effect on the display.
Exit from this command by Display On (29h)
Restriction
This command has no effect when module is already in display off mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Display Off
S/W Reset
Display Off
H/W Reset
Display Off
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Ver 1.3a
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9.1.21 DISPON: Display On (29H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
0
1
0
0
1
29H
Parameter
Description
No parameter
Turn on the display screen according to the current display data RAM content and the display
timing and setting.
This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is
enabled.
This command makes no change of contents of frame memory.
This command does not change any other status.
Restriction
This command has no effect when module is already in display on mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Display Off
S/W Reset
Display Off
H/W Reset
Display Off
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Ver 1.3a
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9.1.22 CASET: Column Address Set (2AH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
0
1
0
1
0
2AH
st
1
1
0
XS15 XS14 XS13 XS12 XS11 XS10
XS9
XS8
Note1
parameter
1
1
0
XS7
XS2
XS1
XS0
Note1
3 parameter
rd
1
1
0
XE15 XE14 XE13 XE12 XE11 XE10
XE9
XE8
Note1
th
1
1
0
XE7
XE1
XE0
Note1
1 parameter
2
nd
4 parameter
Description
XS6
XE6
XS5
XE5
XS4
XE4
XS3
XE3
XE2
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of XS[15:0] and XE[15:0] are referred when RAMWR command comes. Each value
represents one column line in the Frame Memory.
Restriction
XS[15:0] always must be equal to or less than XE[15:0]
Note 1: When XS[15:0] or XE[15:0] is greater than 83h (when MADCTL’s MV=0) or A1h (when
MADCTL’s MV=1), data of out of range will be ignored
Register
Availablility
Ver 1.3a
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
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Default
Default Value
Status
XS [15:0]
XE [15:0]
XE [15:0]
(MV=0)
(MV=1)
Power On Sequence
00h
83h
S/W Reset
00h
83h
H/W Reset
00h
83h
A1h
Flow Chart
CASET
1st & 2nd parameter
SC[15:0]
3rd & 4th parameter
EC[15:0]
PASET
1st & 2nd parameter
SP[15:0]
3rd & 4th parameter
EP[15:0]
If needed
RAMWR
Image Data
D1[7:0],D2[7:0]
… … .Dn[7:0]
Any Command
Ver 1.3a
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9.1.23 RASET: Row Address Set (2BH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
0
1
0
1
1
2BH
st
1 parameter
1
1
0
YS15 YS14 YS13 YS12 YS11 YS10
YS9
YS8
Note1
nd
parameter
1
1
0
YS7
YS2
YS1
YS0
Note1
3 parameter
1
1
0
YE15 YE14 YE13 YE12 YE11 YE10
YE9
YE8
Note1
1
1
0
YE7
YE1
YE0
Note1
2
rd
th
4 parameter
Description
YS6
YE6
YS5
YE5
YS4
YE4
YS3
YE3
YE2
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of YS[15:0] and YE[15:0] are referred when RAMWR command comes. Each value
represents one Page line in the Frame Memory.
Restriction
YS[15:0] always must be equal to or less than YE[15:0]
Note 1: When YS[15:0] or YE[15:0] is greater than A1h (When MADCTL’s MV=0) or 83h (When
MADCTL’s MV=1), data of out of range will be ignored.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
YS [15:0]
Ver 1.3a
YE [15:0]
YE [15:0]
(MV=0)
(MV=1)
Power On Sequence
00h
A1h
S/W Reset
00h
A1h
H/W Reset
00h
A1h
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Flow Chart
CASET
1st & 2nd parameter
SC[15:0]
3rd & 4th parameter
EC[15:0]
PASET
1st & 2nd parameter
SP[15:0]
3rd & 4th parameter
EP[15:0]
RAMWR
Image Data
D1[7:0],D2[7:0]
… … .Dn[7:0]
Any Command
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9.1.24 RAMWR: Memory Write (2CH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
0
1
1
0
0
2CH
Write D1[7:0]
1
1
0
D17
D16
D15
D14
D13
D12
D11
D10
00H ~ FFH
…
1
1
0
Dx7
Dx6
Dx5
Dx4
Dx3
Dx2
Dx1
Dx0
00H ~ FFH
Write Dn[7:0]
1
1
0
Dn7
Dn6
Dn5
Dn4
Dn3
Dn2
Dn1
Dn0
00H ~ FFH
Description
This command is used to transfer data from MCU to frame memory.
This command makes no change to the other driver status.
When this command is accepted, the column register and the page register are reset to the Start
Column/Start Page positions.
The Start Column/Start Row positions are different in accordance with MADCTR setting.
Then D[7:0] is stored in frame memory and the column register and the row register incremented. as in
Figure 8.3.
Frame Write can be canceled by sending any other command.
Restriction
In all colour modes, there is no restriction on length of parameters.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is remained
H/W Reset
Contents of memory is remained
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9.1.25 RGBSET : Color Set (2DH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
0
1
1
0
1
2DH
st
1 parameter
1
1
0
-
-
R005 R004 R003 R002 R001 R000
00H~FFH
…
1
1
0
-
-
Rnn5 Rnn4 Rnn3 Rnn2 Rnn1 Rnn0
00H~FFH
parameter
1
1
0
-
-
R315 R314 R313 R312 R311 R310
00H~FFH
33 parameter
1
1
0
-
-
G005 G004 G003 G002 G001 G000
00H~FFH
32
nd
rd
…
1
1
0
-
-
Gnn5 Gnn4 Gnn3 Gnn2 Gnn1 Gnn0
00H~FFH
th
96 parameter
1
1
0
-
-
G635 G634 G633 G632 G631 G630
00H~FFH
th
97 parameter
1
1
0
-
-
B005 B004
B003
B002 B001
B000
00H~FFH
…
1
1
0
-
-
Bnn5 Bnn4
Bnn3
Bnn2 Bnn1
Bnn0
00H~FFH
128 parameter
1
1
0
-
-
B315 B314
B313
B312 B311
B310
00H~FFH
th
NOTE: “-“ Don’t care
Description
This command is used to define the LUT for 8bit-to-18bit /12bit-to-18bit /16bit-to-18bit colour
depth conversions. (See also section 7.8 ) 128 bytes must be written to the LUT regardless of
the colour mode. Only the values in Section 7.8 are referred.
This command has no effect on other commands/parameters and Contents of frame
memory. Visible change takes effect next time the Frame Memory is written to.
Restriction
Do not send any command before the last data is sent or LUT is not defined correctly.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Random values
S/W Reset
Contents of the look-up table protected
H/W Reset
Random values
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9.1.26 RAMRO : Memory Read (2EH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
0
1
1
1
0
2EH
st
1
0
1
x
x
x
x
x
x
x
x
x
1
0
1
D17
D16
D15
D14
D13
D12
D11
D10
00H ~ FFH
1
0
1
Dx7
Dx6
Dx5
Dx4
Dx3
Dx2
Dx1
Dx0
00H ~ FFH
1
0
1
Dn7
Dn6
Dn5
Dn4
Dn3
Dn2
Dn1
Dn0
00H ~ FFH
1 parameter
2
nd
parameter
…
(N+1)th
parameter
Description
This command is used to transfer data from frame memory to MCU.
This command makes no change to the other driver status.
When this command is accepted, the column register and the page register are reset to the Start
Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting. (See 8.3)
Then D[7:0] is read back from the frame memory and the column register and the page register
incremented as in Table 8.3
Frame Read can be stopped by sending any other command.
Restriction
In all colour modes, the Frame Read is always 18bit so there is no restriction on length of parameters.
Note – Memory Read is only possible via the Parallel Interface.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
H/W Reset
Contents of memory is not cleared
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9.1.27 PTLAR: Partial Area (30H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
1
0
0
0
0
30H
st
1
1
0
PS15 PS14 PS13 PS12 PS11 PS10
PS9
PS8
parameter
1
1
0
PS7
PS2
PS1
PS0
3 parameter
rd
1
1
0
PE15 PE14 PE13 PE12 PE11 PE10
PE9
PE8
th
1
1
0
PE7
PE1
PE0
1 parameter
2
nd
00H ~ A1H
4 parameter
Description
PS6
PS5
PS4
PS3
00H ~ A1H
PE6
PE5
PE4
PE3
PE2
This command defines the partial mode’s display area. There are 2 parameters associated with
this command, the first defines the Start Line (PS) and the second the End Line (PE), as illustrated
in the figures below. PS and PE refer to the Frame Memory Line counter.
If End Line > Start Line when MADCTR ML=0:
If End Line > Start Line when MADCTR ML=1:
If End Line < Start Line when MADCTR ML=0:
End Line
PE[15:0]
Displaying Area
Nondisplaying
Area
PS[15:0]
Partial Area
Displaying Area
Start Line
* Row1: Frame memory row address 1.
If End Line = Start Line then the Partial Area will be one line deep.
Restriction
Ver 1.3a
PS[15:0] and PE[15:0] cannot be greater than A1h.
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Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
PS[15:0]=0000H
PE[15:0]=00A1H
S/W Reset
PS[15:0]=0000H
PE[15:0]=00A1H
H/W Reset
PS[15:0]=0000H
PE[15:0]=00A1H
Flow Chart
1. TO Enter Partial Mode:
PLTAR
SR[15:0]
ER[15:0]
PTLON
Partial Mode
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9.1.28 RLAR: Scroll Area (33h)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
SCRLAR
0
1
0
0
0
1
1
0
0
1
1
(33h)
1st parameter
1
1
0
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0
-
2nd parameter
1
1
0
VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
-
3rd parameter
1
1
0
BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
-
NOTE: “-“ Don’t care
Description
This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll.
When MADCTL ML=0
The 1st parameter TFA [7:0] describes the Top Fixed Area (in No. of lines from Top of the Frame
Memoryand Display).
The 2nd parameter VSA [7:0] describes the height of the Vertical Scrolling Area (in No. of lines of the
Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears
immediately after the bottom most line of the Top Fixed Area.
The 3rd parameter BFA [7:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame
Memory and Display).
TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Restriction
The condition is (TFA+VSA+BFA) = 162, otherwise Scrolling mode is undefined.
In Vertical Scroll Mode, MADCTL parameter MV should be set to ‘0’-this only affects the Frame Memory
Write.
TFA[7:0], VSA[7:0] and BFA[7:0] is based on line unit.
TFA[7:0]= 00h, 01h, 02h, 03h, … , A1h
VSA[7:0]= 00h, 01h, 02h, 03h, … , A1h
BFA[7:0]= 00h, 01h, 02h, 03h, … , A1h
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Ver 1.3a
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Default
Default Value
Status
TFA [7:0]
VSA [7:0]
BFA [7:0]
Power On Sequence
00h
A2h
00h
S/W Reset
00h
A2h
00h
H/W Reset
00h
A2h
00h
Flow Chart
Ver 1.3a
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1.To enter Vertical Scroll Mode.
Normal Mode
SCRLAR
1st Parameter
TFA[7:0]
2nd Parameter
VSA[7:0]
3nd Parameter
BFA[7:0]
CASET
1st Parameter
XS[7:0]
2nd Parameter
XE[7:0]
Redefines the Frame
Memory Window that the
scroll data will be written
to See Note
RASET
1st Parameter
YS[7:0]
Only required for
non-rolling scrolling
2nd Parameter
YE[7:0]
MADCTR
Optional - It may be
necessary to redefine the
Frame Memory Write
Direction.
Parameter
RAMWR
Scroll Video Data
VSCSAD
1st Parameter
SSA[7:0]
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be
displayed.
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low Chart
2. Continuous Scroll
Normal Mode
CASET
1st Parameter
XS[7:0]
2nd Parameter
XE[7:0]
RASET
Only required for
non-rolling
scrolling
1st Parameter
YS[7:0]
2nd Parameter
YE[7:0]
RAMWR
Scroll Video Data
VSCSAD
1st Parameter
SSA[7:0]
3. To Exit Vetical Scroll mode
Scroll Mode
DISPOFF
NORON/PTLON
Scroll Mode OFF
RAMWR
Video Data
D1[7:0]...Dn[7:0]
DISPON
NOTE: Scroll Mode can be exit by both the Normal Display Mode On(13h) and Partial Mode On (12h)
commands.
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9.1.29 TEOFF: Tearing Effect Line Off (34H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
1
0
1
0
0
34H
Parameter
No Parameter
Description
This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction
This command has no effect when Tearing Effect output is already OFF.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
Tearing effect off
S/W Reset
Tearing effect off
H/W Reset
Tearing effect off
Flow Chart
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9.1.30 TEON: Tearing Effect Line On (35H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
1
0
1
0
1
35H
st
1
1
0
-
-
-
-
-
-
-
M
-
1 parameter
NOTE: “-“ Don’t care
Description
This command is used to turn ON the Tearing Effect output signal from the TE signal line. This
output is not affected by changing MADCTL bit ML.
The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect
Output Line. (“-“=Don’t Care).
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction
This command has no effect when Tearing Effect output is already ON.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
Tearing effect off & M=0
S/W Reset
Tearing effect off & M=0
H/W Reset
Tearing effect off & M=0
Flow Chart
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9.1.31 MADCTL: Memory Access Control (36H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
1
0
1
1
0
36H
st
1
1
0
MY
MX
MV
ML
RGB
-
-
-
-
1 parameter
Description
This command defines read/write scanning direction of frame memory.
This command makes no change on the other driver status.
Note: ML affects to Partial Area (30h), Vertical Scrolling Definition (33h), Vertical Scrolling Start address
(37h), Partial On (12h) commands
Bit
NAME
DESCRIPTION
MX
Page Address Order
These 3 bits controls MCU to memory write/read
MY
Column Address Order
direction.
MV
Page/Column Selection
ML
Vertical Order
LCD vertical refresh direction control
RGB
RGB-BGR Order
Colour selector switch control
(0=RGB colour filter panel, 1=BGR colour filter panel)
The contents of the frame memory are not changed.
ML:Line(Scan) Address Order
Note: Top-Left (0,0) means a physical memory location.
Restriction
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Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
MY=0,MX=0,ML=0,RGB=0
S/W Reset
No Change
H/W Reset
MY=0,MX=0,ML=0,RGB=0
Flow Chart
Ver 1.3a
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9.1.32 SCSAD: Vertical Scroll Start Address of RAM (37h)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
VSCSAD
0
1
0
0
0
1
1
0
1
1
1
(37h)
Parameter
1
1
0
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
NOTE: “-“ Don’t care
Description
This command is used together with Vertical Scrolling Definition (33h). These two commands
describe the scrolling area and the scrolling mode.
The Vertical Scrolling Start Address command has one parameter which describes which line in the
Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as
illustrated below:
This command Start the scrolling.
Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
When MADCTL ML=0
Example:
When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=162 and Vertical Scrolling
Pointer SSA=’3’.
When MADCTL ML=1
Example:
When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=162 and Vertical Scrolling
Pointer SSA=’3’.
NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at
the next Panel Scan to avoid tearing effect.
SSA refers to the Frame Memory line Pointer.
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Restriction
Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame
Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise
undesirable image will be displayed on the Panel.
SSA [7:0] is based on line unit.
SSA [7:0] = 00h, 01h, 02h, 03h, … , A1h
Register
Availability
Default
Flow Chart
Ver 1.3a
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
No
Partial Mode On, Idle Mode On, Sleep Out
No
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
See Vertical Scrolling Definition (33h) description.
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9.1.33 IDMOFF: Idle Mode Off (38H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
1
1
0
0
0
38H
Parameter
Description
No Parameter
This command is used to recover from Idle mode on.
There will be no abnormal visible effect on the display mode change transition.
In the idle off mode,
1. LCD can display maximum 262,144 colors.
2. Normal frame frequency is applied.
Restriction
This command has no effect when module is already in idle off mode.
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
Idle Off Mode
S/W Reset
Idle Off Mode
H/W Reset
Idle Off Mode
Flow Chart
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9.1.34 IDMON: Idle Mode On (39H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
0
0
0
1
1
1
0
0
1
39H
Parameter
Description
No Parameter
This command is used to enter into Idle mode on.
There will be no abnormal visible effect on the display mode change transition.
In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each
R, G and B in the Frame Memory, 8 color depth data is displayed.
2. 8-Color mode frame frequency is applied.
3. Exit from IDMON by Idle Mode Off (38h) command
Memory contents V.S Display Colour
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1
B5 B4 B3 B2 B1 B0
G0
Black
0XXXXX
0XXXXX
0XXXXX
Blue
0XXXXX
0XXXXX
1XXXXX
Red
1XXXXX
0XXXXX
0XXXXX
Magenta
1XXXXX
0XXXXX
1XXXXX
Green
0XXXXX
1XXXXX
0XXXXX
Cyan
0XXXXX
1XXXXX
1XXXXX
Yellow
1XXXXX
1XXXXX
0XXXXX
White
1XXXXX
1XXXXX
1XXXXX
X=don't care
Restriction
Ver 1.3a
This command has no effect when module is already in idle on mode.
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Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
Idle Off Mode
S/W Reset
Idle Off Mode
H/W Reset
Idle Off Mode
Flow Chart
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ST7669
9.1.35 COLMOD: Interface Pixel Format (3AH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
0
0
1
1
1
0
1
0
3AH
st
1
1
0
-
-
-
-
-
D2
D1
D0
-
1 parameter
NOTE: “-“ Don’t care
Description
This command is used to define the format of RGB picture data, which is transferred via the MCU
Interface. The formats are shown in the table:
Interface Format
D2
D1
D0
Not Defined
0
0
0
Not Defined
0
0
1
8 Bit/Pixel
0
1
0
12 Bit/Pixel
1
0
0
16 Bit/Pixel
1
0
1
18 Bit/Pixel
1
1
0
24 Bit/Pixel
1
1
1
Note: In 8 bit/pixel , 8 bit/pixel or 16 bit/pixel mode, the LUT is applied to transfer data into the
Frame Memory.
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
06h (18Bit/Pixel)
S/W Reset
No Change
H/W Reset
06h (18Bit/Pixel)
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Flow Chart
Ver 1.3a
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ST7669
9.1.36 RDID1: Read ID1 (DAH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
0
1
1
0
1
0
DAH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
-
1 parameter
2
nd
parameter
NOTE: “-“ Don’t care
Description
This read byte returns 8-bit LCD module’s manufacturer ID
D7-D0 (ID17 to ID10): LCD module’s manufacturer ID.
NOTE: See command RDDID (04h), 2nd parameter.
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
Not fixed
S/W Reset
Not fixed
H/W Reset
Not fixed
Flow Chart
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9.1.37 RDID2: Read ID2 (DBH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
0
1
1
0
1
1
DBH
st
1
0
1
x
-
-
-
-
-
-
-
-
1
0
1
1
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-
1 parameter
2
nd
parameter
NOTE: “-“ Don’t care
Description
This read byte returns 8-bit LCD module/driver version ID
D7-D0 (ID27 to ID20): LCD module/driver version ID
Parameter Range: ID=80h to FFh
NOTE: See command RDDID (04h), 3rd parameter.
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
Not fixed
S/W Reset
Not fixed
H/W Reset
Not fixed
Flow Chart
Ver 1.3a
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9.1.38 RDID3: Read ID3 (DCH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
0
1
1
1
0
0
DCH
st
1
0
1
-
-
-
-
-
-
-
-
-
1
0
1
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
-
1 parameter
2
nd
parameter
NOTE: “-“ Don’t care
Description
This read byte returns 8-bit LCD module/driver ID.
D7-D0 (ID37 to ID30): LCD module/driver ID.
NOTE: See command RDDID (04h), 4th parameter.
Restriction
Register
Availablility
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
0Eh
S/W Reset
0Eh
H/W Reset
0Eh
Flow Chart
Ver 1.3a
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9.1.39 DutySet: Display Duty setting (B0H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
DutySet
0
1
0
1
0
1
1
0
0
0
0
(B0h)
Parameter
1
1
0
Du7
Du6
Du5
Du4
Du3
Du2
Du1
Du0 -
NOTE: “-“ Don’t care
Description
This command is used to set display duty. Command set = display duty numbers - 1.
Example:
Command set=
Duty
Du6
Du5
Du4
Du3
Du2
Du1
Du0
Display duty
numbers-1
Example:
0
1
1
1
1
1
1
128-1=127
1/128 duty
Restriction
Display duty must > 4 (1/4 duty)
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
10100001b (A1h)
S/W Reset
10100001b (A1h)
H/W Reset
10100001b (A1h)
(Du[7:0])
Flow Chart
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9.1.40 FirstCom: First Com. Page address (B1H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
FirstCom
0
1
0
1
0
1
1
0
0
0
1
(B1h)
Parameter
1
1
0
F7
F6
F5
F4
F3
F2
F1
F0
-
NOTE: “-“ Don’t care
Description
This command defines the first output COM number that mapping to the RAM page
address 0. For detail setting value, please see the table as below.
F6
0
0
0
0
:
1
F5
0
0
0
0
:
0
F4
0
0
0
0
:
0
F3
0
0
1
1
:
0
F2
F1
1
0
F0
0
1
0
1
:
1
Line address
0
1
2
3
:
69
Example:
If FirstCom=8, common 8 would output the data of RAM page address 0.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
(F[7:0])
Flow Chart
Ver 1.3a
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9.1.41 OscDiv: FOSC Divider (B3H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
OscDiv
0
1
0
1
0
1
1
0
0
1
1
(B3h)
Parameter
1
1
0
-
-
-
-
-
-
CLD1 CLD0
-
NOTE: “-“ Don’t care
Description
This command is used to specify the CL dividing ratio.
CLD1, CLD0: CL dividing ratio. They are used to change number of dividing stages of external or
internal clock.
CLD1
CLD0
CL dividing ratio
0
0
Not divide
0
1
2 divisions
1
0
4 divisions
1
1
8 divisions
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
00b
S/W Reset
00b
H/W Reset
00b
(CLD[0:1])
Flow Chart
Ver 1.3a
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ST7669
9.1.42 PTLMOD: Partial Saving Power Mode Selection (B4H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
OscDiv
0
1
0
1
0
1
1
0
1
0
0
(B4h)
Parameter
1
1
0
PTLM
0
0
1
1
0
0
0
-
NOTE: “-“ Don’t care
Description
Two type partial modes are built in ST7669. One is NORMAL MODE(PTLM=0) and another is
POWER SAVING MODE(PTML=1). When entering power saving mode, IC would change bias, V0,
booster pumping times special partial lines in order to save power consumptions.
Restriction
The power saving power mode is customerlized.
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
18h
S/W Reset
18h
H/W Reset
18h
Flow Chart
Ver 1.3a
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9.1.43 NLInvSet: N-Line control (B5H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
NLInvSet
0
1
0
1
0
1
1
0
1
0
1
(B5h)
Parameter
1
1
0
M
N6
N5
N4
N3
N2
N1
N0
-
NOTE: “-“ Don’t care
Description
This command is used to set the inverted line number with range of 2 to (duty-1) to improve display
quality. When M=0, inversion occurs in every frame; when M=1, inversion is independent from
frames. If N[6:0]=0, N-line inversion function is disable.
Line inversion numbers=N[6:0] +1.
Example:
If N[6:0]=7, inversion occurs per 8 line.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
M
N[6:0]
Power On Sequence
0b
0000000b
S/W Reset
0b
0000000b
H/W Reset
0b
0000000b
Flow Chart
Ver 1.3a
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ST7669
9.1.44 ComScanDir: Com/Seg Scan Direction for glass layout(B7H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
ComScanDir
0
1
0
1
0
1
1
0
1
1
1
(B7h)
Parameter
1
1
0
SMY
SMX
SINV
0
0
0
-
SML SBGR
NOTE: “-“ Don’t care
Description
It is used to specify the common output direction in the pin of CSEL = L. This command helps to improve
Common ITO layout tolerance on the LCM.
When CSEL=L configuration is selected, pins and common outputs are scanned in the order shown below.
Function
0
1
SMY
Inverse the MY setting
Keep MY
Inverse MY
SMX
Inverse the MX setting
Keep MX
Inverse MX
SINV
Inverse the INVON setting
Keep INVON
Inverse INVON
SML
Inverse the ML setting
Keep ML
Inverse ML
SBGR
Inverse the BGR setting
Keep BGR
Inverse BGR
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
00b
S/W Reset
00b
H/W Reset
00b
(CSD[1:0])
Flow Chart
Ver 1.3a
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ST7669
9.1.45 RMWIN: Read Modify Write control in (B8H)
Command
RMWIN
Parameter
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
0
1
1
1
0
0
0
(B8h)
No Parameter
NOTE: “-“ Don’t care
Description
Read modify write control IN
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
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ST7669
9.1.46 RMWOUT: Read Modify Write control out(B9H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
RMWOUT
0
1
0
1
0
1
1
1
0
0
1
(B9h)
Parameter
No Parameter
NOTE: “-“ Don’t care
Description
Read modify write control OUT
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
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ST7669
9.1.47 VopSet: Vop set (C0H)
Command
VopSet
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
1
1
0
0
0
0
0
0
(C0h)
0
1
0
st
1
1
0
nd
1
1
0
1 parameter
2 parameter
Vop7 Vop6 Vop5 Vop4 Vop3 Vop2 Vop1 Vop0 -
-
-
-
-
-
-
Vop8
NOTE: “-“ Don’t care
Description
The command is used to program the optimum LCD supply voltage V0.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value (Vop=12V)
Vop8
Vop[7:0]
Power On Sequence
0
11010010b (D2h)
S/W Reset
0
11010010b (D2h)
H/W Reset
0
11010010b (D2h)
Flow Chart
Ver 1.3a
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9.1.48 VopfsetInc: Vop Increase 1 (C1H)
Command
VopOfsetInc
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
0
0
0
0
0
1
(C1h)
NOTE: “-“ Don’t care
Description
With the VopOfsetInc and VopOfsetDec command the VLCD voltage and therewith the contrast
of the LCD can be adjusted. This command increases the value of Vop offset register by 1.
If you set the electronic control value to 1111111, the control value is set to 0000000 after this
command has been executed.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
Flow Chart
Ver 1.3a
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9.1.49 VopOfsetDec: Vop Decrease 1 (C2H)
Command
VopOfsetDec
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
0
0
0
0
1
0
(C2h)
NOTE: “-“ Don’t care
Description
With the VopOfsetInc and VopOfsetDec command the VLCD voltage and therewith the contrast
of the LCD can be adjusted. This command decreases the value of Vop offset register by 1.
If you set the electronic control value to 0000000, the control value is set to 1111111 after this
command has been executed.
Electronic Control Value
Decimal Equivalent
V0 Offset
0111111
63
+2520 mV
0111110
62
+2480 mV
0111101
61
+2440 mV
…
…
…
0000010
2
+80 mV
0000001
1
+40 mV
0000000
0
0 mV
1111111
-1
-40 mV
1111110
-2
-80 mV
…
…
…
1100010
-61
-2480 mV
1100001
-62
-2520 mV
1100000
-64
-2560mV
Possible Vop[6:0] values
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
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Flow Chart
Ver 1.3a
152/216
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ST7669
9.1.50 BiasSel: Bias Selection(C3H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
BiasSel
0
1
0
1
1
0
0
0
0
1
1
(C3h)
Parameter
1
1
0
-
-
-
-
-
Bias2 Bias1 Bias0
-
NOTE: “-“ Don’t care
Description
Select LCD bias ratio of the voltage required for driving the LCD.
Bais2
Bais1
Bais0
LCD bias
0
0
0
1/14
0
0
1
1/13
0
1
0
1/12
0
1
1
1/11
1
0
0
1/10
1
0
1
1/9
1
1
0
1/7
1
1
1
1/5
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
011b
S/W Reset
011b
H/W Reset
011b
(Bias[2:0])
Flow Chart
Ver 1.3a
153/216
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ST7669
9.1.51 BstPmpXSel: Booster Set(C4H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
BstPmpXSel
0
1
0
1
1
0
0
0
1
0
0
(C4h)
Parameter
1
1
0
-
-
-
-
-
BST2 BST 1 BST0 -
NOTE: “-“ Don’t care
Description
Booster setting
BST2
BST1
BST0
0
0
0
X1 boosting circuit
(Booster off)
0
0
1
X2 boosting circuit
0
1
0
X3 boosting circuit
0
1
1
X4 boosting circuit
1
0
0
X5 boosting circuit
1
0
1
X6 boosting circuit
1
1
0
X7 boosting circuit
1
1
1
X8 boosting circuit
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
111b
S/W Reset
111b
H/W Reset
111b
154/216
(BST[2:0])
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ST7669
Flow Chart
Ver 1.3a
155/216
3/2/2009
ST7669
9.1.52 BstEffSel: Booster Efficiency selection(C5H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
BstEffSel
0
1
0
1
1
0
0
0
1
0
1
(C5h)
Parameter
1
1
0
-
-
1
0
-
-
BTF1 BTF0 -
NOTE: “-“ Don’t care
Description
Booster Efficiency set
BTF1
BTF0
Frequency ( Hz )
0
0
Level 1
0
1
Level 2 (default)
1
0
Level 3
By Booster Stages (2X, 3X, 4X, 5X, 6X, 7X, 8X) and Booster Efficiency (Level1~3) commands, we
could easily set the best Booster performance with suitable current consumption. If the Booster
Efficiency is set to higher level (level3 is higher than level1). The Boost Efficiency is better than lower
level, and it just need few more power consumption current.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value (BTF[1:0])
Power On Sequence
01b
S/W Reset
01b
H/W Reset
01b
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Flow Chart
Ver 1.3a
157/216
3/2/2009
ST7669
9.1.53 VopOffset: Vop offset fuse bit adjust(C7H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
VopOffset
0
1
0
1
1
0
0
0
1
1
1
(C7h)
Parameter1
1
1
0
Parameter2
1
1
0
VOS7 VOS6 VOS5 VOS4 VOS3 VOS2 VOS1 VOS0
-
-
-
-
-
-
-
VOS8
-
NOTE: “-“ Don’t care
Description
The command is used to the Vop offset for V0. For VOS[8:0] setting, please see the following
table:
VOS[8]
0
VOS[7:0]
(Dec)
V0 Offset
11111111
255
+10200 mV
11111110
254
+10160 mV
11111101
253
+10120 mV
…
…
…
00000010
2
+80 mV
00000001
1
+40 mV
00000000
0
0 mV
11111111
-1
-40 mV
11111110
-2
-80 mV
…
…
…
00000010
-253
-10120 mV
00000001
-254
-10160 mV
00000000
-255
-10200 mV
1
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
VOS8
VOS[7:0]
Power On Sequence
0
0
S/W Reset
0
0
H/W Reset
0
0
158/216
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Flow Chart
Ver 1.3a
159/216
3/2/2009
ST7669
9.1.54 V3SorcSel: FV3 with Bst2x control(CBH)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
V3SorcSel
0
1
0
1
1
0
0
1
0
1
1
(CBh)
Parameter
1
1
0
-
-
-
-
-
-
-
2BT0 -
NOTE: “-“ Don’t care
Description
2BT0=0: Vg source comes from VDD2 ;
2BT0=1: Vg source comes from 2-times charge pump.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value (2BT0)
Power On Sequence
0
S/W Reset
0
H/W Reset
0
Flow Chart
Ver 1.3a
160/216
3/2/2009
ST7669
9.1.55 ID1Set : ID1 setting(CCH)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
ID1Set
0
1
0
1
1
0
0
1
1
0
0
(CCh)
Parameter
1
1
0
ID1_7 ID1_6 ID1_5 ID1_4 ID1_3 ID1_2 ID1_1 ID1_0
-
NOTE: “-“ Don’t care
Description
ID1 setting for OPT program data input
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
45h
S/W Reset
45h
H/W Reset
45h
Flow Chart
Ver 1.3a
161/216
3/2/2009
ST7669
9.1.56 ID2Set : ID2 setting(CDH)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
ID2Set
0
1
0
1
1
0
0
1
1
0
1
(CDh)
Parameter
1
1
0
1
ID2_6 ID2_5 ID2_4 ID2_3 ID2_2 ID2_1 ID2_0
-
NOTE: “-“ Don’t care
Description
ID2 setting for OPT program data input
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
0
S/W Reset
0
H/W Reset
0
Flow Chart
Ver 1.3a
162/216
3/2/2009
ST7669
9.1.57 ID3Set : ID3 setting(CEH)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
ID3Set
0
1
0
1
1
0
0
1
1
1
0
(CEh)
Parameter
1
1
0
ID3_7 ID3_6 ID3_5 ID3_4 ID3_3 ID3_2 ID3_1 ID3_0
-
NOTE: “-“ Don’t care
Description
ID3 setting for OPT program data input
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
0
S/W Reset
0
H/W Reset
0
Flow Chart
Ver 1.3a
163/216
3/2/2009
ST7669
9.1.58 ANASET: Analog circuit setting(D0H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
AutoLoadSet
0
1
0
1
1
0
1
0
0
0
0
(D0h)
Parameter
1
1
0
0
0
0
1
1
1
0
1
-
NOTE: “-“ Don’t care
Description
Analog circuit setting.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value D[7:0]
Power On Sequence
1Dh
S/W Reset
1Dh
H/W Reset
1Dh
Flow Chart
Ver 1.3a
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3/2/2009
ST7669
9.1.59 AutoLoadSet : mask rom data auto re-load control(D7H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
AutoLoadSet
0
1
0
1
1
0
1
0
1
1
1
(D7h)
Parameter
1
1
0
EXTE
OTPBE
-
ARD
-
-
-
-
-
NOTE: “-“ Don’t care
Description
Mask rom data auto re-load control
EXTE : External command enable (OTP input), 1: enable, 0: disable
OTPBE: OTPB auto-read enable (OTP input),
ARD : OTP auto read enable control,
1: enable, 0: disable
1: Disable OTP auto read,
0: Enable OTP auto read
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
EXTE
ARD
Power On Sequence
0
0
S/W Reset
0
0
H/W Reset
0
0
Flow Chart
Ver 1.3a
165/216
3/2/2009
ST7669
9.1.60 RDTstStatus : Read IC status(DEH)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
RDTstStatus
0
1
0
1
1
0
1
1
1
1
0
(DEh)
Dummy Read
1
0
1
-
-
-
-
-
-
-
-
Parameter
1
0
1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
-
NOTE: “-“ Don’t care
Description
Read IC status.
Contect of OTP / RDA / PWR_VOP read control
(selection Byte by StusOutByteSel[3:0] control)
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
-
S/W Reset
-
H/W Reset
-
Flow Chart
Ver 1.3a
166/216
3/2/2009
ST7669
9.1.61 EPCTIN: Control OTP WR/RD(E0H)
Command
EPCTIN
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
0
0
0
0
(E0h)
WR
0
0
0
0
0
-
1
1
0
0
0
Parameter
/XRD
NOTE: “-“ Don’t care
Description
WR/XRD: when setting “1” The Write Enable of OTP will be opened.
WR/XRD: when setting “0” The Read Enable of OTP will be opened.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
0
S/W Reset
0
H/W Reset
0
(WR/XRD)
Flow Chart
Ver 1.3a
167/216
3/2/2009
ST7669
9.1.62 EPCOUT: OTP control cancel(E1H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
EPCOUT
0
1
0
1
1
1
0
0
0
0
1
(E1h)
NOTE: “-“ Don’t care
Description
IC exits the OTP control circuit when executing this command.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
Flow Chart
Ver 1.3a
168/216
3/2/2009
ST7669
9.1.63 EPMWR: Write to OTP(E2H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
EPCOUT
0
1
0
1
1
1
0
0
0
1
0
(E2h)
NOTE: “-“ Don’t care
Description
IC actives trigger to start OTP programming when executing this command.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
Flow Chart
Ver 1.3a
169/216
3/2/2009
ST7669
9.1.64 EPMRD: Read from OTP(E3H)
Command
EPMRD
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
0
0
1
1
(E3h)
NOTE: “-“ Don’t care
Description
IC actives trigger to start OTP data download to circuit when executing this command.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
S/W Reset
H/W Reset
Flow Chart
Ver 1.3a
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ST7669
9.1.65
OTPSEL: SEL OTP(E4H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
OTPSEL
0
1
0
1
1
1
0
0
1
0
0
(E4h)
Parameter
1
1
0
MS1
MS0
0
1
1
0
0
0
-
NOTE: “-“ Don’t care
Description
This command defines OTPA/OTPB selection for EEPROM control. Please see the table as below:
MS1
MS0
Mode
0
0
Disable
0
1
OTP
1
0
OTPA
1
1
OTPB
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value
Power On Sequence
00
S/W Reset
00
H/W Reset
00
171/216
(MS[1:0])
3/2/2009
ST7669
Flow Chart
Ver 1.3a
172/216
3/2/2009
ST7669
9.1.66
ROMSET: Programmable rom setting(E5H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
AutoLoadSet
0
1
0
0
1
1
1
0
1
0
1
(E5h)
Parameter
1
1
0
0
0
0
0
1
1
1
0
-
NOTE: “-“ Don’t care
Description
Set the OTP writing timing. Value 0x0e is the best value for ST7669.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value D[7:0]
Power On Sequence
0Fh
S/W Reset
0Fh
H/W Reset
0Fh
Flow Chart
Ver 1.3a
173/216
3/2/2009
ST7669
9.1.67 HPMSET : High Power Mode Setting (EBH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
1
0
1
0
1
1
EBH
st
1 parameter
1
1
0
0
0
0
0
0
0
HP1
HP0
2nd parameter
1
1
0
0
0
0
0
0
0
0
0
Description
High power mode for volatage compensation.
HP1
HP0
Status
0
0
Level 1 (Default)
0
1
Level 2
1
0
Level 3
Restriction
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
HP[3:0]
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
Flow Chart
HPMSEL
1st parameter : 01H
2nd parameter : 00H
Ver 1.3a
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3/2/2009
ST7669
9.1.68 FRMSEL: Frame Freq. in Temp. range (F0H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
1
1
0
0
0
0
F0H
st
1
1
0
-
-
-
DIVA
FA3
FA2
FA1
FA0
Range A
parameter
1
1
0
-
-
-
DIVB
FB3
FB2
FB1
FB0
Range B
3 parameter
rd
1
1
0
-
-
-
DIVC
FC3
FC2
FC1
FC0
Range C
th
1
1
0
-
-
-
DIVD
FD3
FD2
FD1
FD0
Range D
1 parameter
2
nd
4 parameter
Description
Select Frame Freq. in normal display mode.
st
1 parameter : Frame freq. value set in temperature range 30(-30℃) to TA
2
nd
parameter : Frame freq. value set in temperature P range TA to TB
rd
3 parameter : Frame freq. value set in temperature range TB to TC
th
4 parameter : Frame freq. value set in temperature range TC to 145(90℃)
For command setting to frame rate value look-up-table, please see the following table:
DIVx
1
0
Ver 1.3a
Fx[3:0]
Frame Rate (Hz)
(+/- 10% tolerance)
0
75
1
76
2
77
3
80
4
84
5
88
6
92
7
97
8
102
9
108
A
115
B
123
C
133
D
144
E
155
F
170
0~F
(Frame Rate)/2
175/216
3/2/2009
ST7669
Restriction
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
FA[4:0]
FB[4:0]
FC[4:0]
FD[4:0]
Power On Sequence
06h
0Bh
0Dh
12h
S/W Reset
06h
0Bh
0Dh
12h
H/W Reset
06h
0Bh
0Dh
12h
Flow Chart
Ver 1.3a
176/216
3/2/2009
ST7669
9.1.69 FRM8SEL: Frame Freq. in Temp. range (idel-8 color) (F1H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
1
1
0
0
0
1
F1H
st
1
1
0
-
-
-
F8A4 F8A3 F8A2 F8A1 F8A0
Range A
1 parameter
2
nd
parameter
1
1
0
-
-
-
F8B4 F8B3 F8B2 F8B1 F8B0
Range B
rd
3 parameter
1
1
0
-
-
-
F8C4 F8C3 F8C2 F8C1 F8C0
Range C
th
1
1
0
-
-
-
F8D4 F8D3 F8D2 F8D1 F8D0
Range D
4 parameter
Description
Select Frame Freq. in normal display mode.(idle;8 color mode)
st
1 parameter : Frame freq. value set in TEMP range 30(-30℃) to TA
2
nd
parameter : Frame freq. value set in TEMP range TA to TB
rd
3 parameter : Frame freq. value set in TEMP range TB to TC
th
4 parameter : Frame freq. value set in TEMP range TC to 145(90℃)
Restriction
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Ver 1.3a
Default Value
FA[4:0]
FB[4:0]
FC[4:0]
FD[4:0]
Power On Sequence
06h
0Bh
0Dh
12h
S/W Reset
06h
0Bh
0Dh
12h
H/W Reset
06h
0Bh
0Dh
12h
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Flow Chart
FRM8SL
1st parameter. F8A[4:0]
2nd parameter. F8B[4:0]
3rd parameter. F8C[4:0]
4th parameter. F8D[4:0]
Ver 1.3a
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9.1.70 TMPRNG: Temp. range set for Frame Freq. Adj. (F2H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
1
1
0
0
1
0
F2H
st
1
1
0
-
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Range A
parameter
1
1
0
-
TB6
TB5
TB4
TB3
TB2
TB1
TB0
Range B
3 parameter
1
1
0
-
TC6
TC5
TC4
TC3
TC2
TC1
TC0
Range C
1 parameter
2
nd
rd
Description
Temp. range set for automatic frame freq. adj. operation according the current temp. value.
st
1 parameter: Temp. range A value set
2
nd
parameter: Temp. range B value set
rd
3 parameter: Temp. range C value set
TA/TB/TC Temperature(℃) + 40 = TA/TB/TC[6:0]
Example:
If TA wants to be set at 24℃, TA[6:0]=24+40=64(40h),
Restriction
-40℃℃TA℃TA+TH℃TB℃TB+TH℃TC℃87℃
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Ver 1.3a
Default Value
TA[6:0]
TB[6:0]
TC[6:0]
Power On Sequence
1Eh
28h
32h
S/W Reset
1Eh
28h
32h
H/W Reset
1Eh
28h
32h
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Flow Chart
Ver 1.3a
180/216
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9.1.71 TMPHYS: Temp.Hysteresis Set for Frame Freq. Adj.(F3H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
1
0
1
1
1
1
0
0
1
1
F3H
st
1
1
0
-
-
-
-
TH3
TH2
TH1
TH0
1 parameter
Description
Temp. hysteresis range set for frame freq. adj.
Parameter TH[3:0] is used to set Temp. hysteresis range.
The relationship between temp. state and temp. range value is shown below.
TEMP Range Value
TEMP Rising State
TEMP Falling State
Freq. changing point A
TA[6:0]+TH[3:0]
TA[6:0]
Freq. changing point B
TB[6:0]+TH[3:0]
TB[6:0]
Freq. changing point C
TC[6:0]+TH[3:0]
TC[6:0]
TH Temperature(℃) - 1 = TH[3:0]
Example:
If TH wants to set 5℃, TH[3:0]=5-1=4.
Restriction
Temp. hysteresis value should be smaller than the gap of temp. range.
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Ver 1.3a
Status
Default Value(TH[3:0])
Power On Sequence
4H
S/W Reset
4H
H/W Reset
4H
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Flow Chart
Ver 1.3a
182/216
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9.1.72 TEMPSEL: Temp. Set(F4H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
TEMPSEL
0
1
0
1
1
1
1
0
1
0
0
(F4h)
1st
1
1
0
o
o
o
o
MT1x: (-24 C to -32 C)
parameter
MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00
MT0x: (-32 C to -40 C)
o
2nd
o
MT3x: (-8 C to -16 C)
parameter
1
1
0
MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20
o
o
MT2x: (-16 C to -24 C)
o
3
rd
o
MT5x: (8 C to 0 C)
parameter
1
1
0
MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40
o
o
MT4x: (0 C to -8 C)
o
4
th
o
MT7x: (24 C to16 C)
parameter
1
1
0
MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60
o
o
MT6x: (16 C to 8 C)
5
th
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
MT9x: (40 C to 32 C)
parameter
1
1
0
MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80
MT8x: (32 C to 24 C)
6
th
MTBx: (56 C to 48 C)
parameter
1
1
0
MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0
MTAx: (48 C to 40 C)
7th
MTDx: (72 C to 64 C)
parameter
1
1
0
MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0
MTCx: (64 C to 56 C)
8th
MTFx: (87 C to 80 C)
parameter
1
1
0
MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0
MTEx: (80 C to 72 C)
NOTE: “-“ Don’t care
Description
This command defines temperature gradient compensation coefficient. For this command
detail description and opearation, please see Section 7.10.
Parameter n
MT n 3
MT n 2
MT n 1
MT n 0
o
Voltage / C
(+/- 3mv tolerance)
Ver 1.3a
o
0
0
0
0
0
+5 mv / C
1
0
0
0
1
0 mv / C
2
0
0
1
0
-5 mv / C
3
0
0
1
1
-10 mv / C
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
12
1
1
0
0
-55 mv / C
13
1
1
0
1
-60 mv / C
14
1
1
1
0
-65 mv / C
15
1
1
1
1
-70 mv / C
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o
o
o
o
o
o
o
3/2/2009
ST7669
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value (MTn[3:0])
Power On Sequence
1st
S/W Reset
H/W Reset
parameter 0xFF
2
nd
parameter 0x2F
3
rd
parameter 0x0A
4
th
parameter 0x35
5
th
parameter 0x31
6
th
parameter 0x40
7
th
parameter 0xA7
8
th
parameter 0x13
Flow Chart
Ver 1.3a
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9.1.73 THYS : Temperature detection threshold(F7H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
THYS
0
1
0
1
1
1
1
0
1
1
1
(F7h)
Parameter
1
1
0
THYS7 THYS6 THYS5 THYS4 THYS3 THYS2 THYS1 THYS0
-
NOTE: “-“ Don’t care
Description
Temperature detection threshold setting.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value D[7:0]
Power On Sequence
06h
S/W Reset
06h
H/W Reset
06h
Flow Chart
Ver 1.3a
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9.1.74 Frame Set: Frame PWM Set (F9H)
Command
A0
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
1
1
0
0
1
(F9h)
parameter
1
1
0
-
-
-
P14
P13
P12
P11
P10
-
parameter
1
1
0
-
-
-
P24
P23
P22
P21
P20
-
:
:
:
:
:
:
:
:
:
:
:
-
Frame1 Set
1
st
2nd
:
th
parameter
1
1
0
-
-
-
P154
P153
P152
P151
P150
-
16th
parameter
1
1
0
-
-
-
P164
P163
P162
P161
P160
-
15
NOTE: “-“ Don’t care
Description
This command is used to set frame PWM.
Restriction
Register
Status
Availability
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Default
Status
Default Value
Power On Sequence
--
S/W Reset
--
H/W Reset
--
Flow Chart
Ver 1.3a
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The default value of RGB level set
FRAM SET
RGB level0
00
RGB level1
04
RGB level2
05
RGB level3
08
RGB level4
0B
RGB level5
0C
RGB level6
0E
RGB level7
0F
RGB level8
11
RGB level9
12
RGB level10
13
RGB level11
14
RGB level12
16
RGB level13
17
RGB level14
19
RGB level15
1B
1.
All the modulation range of each level for each frame is from 00’H to 1F’H.
2.
The setting value is base on LCD module state.
Ver 1.3a
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10.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Item
Symbol
Value
Unit
Supply voltage (1)
VDD
- 0.3 ~ + 3.0
V
Supply voltage (1)
VDD2,VDD3,VDD4,VDD5
- 0.3 ~ + 4.2
V
Supply voltage (2)
V0 (V0-VSS)
- 0.3 ~ + 18.0
V
Supply voltage (3)
VMAX (V0- XV0)
- 0.3 ~ + 18.0
V
Input voltage range
VIN
- 0.3 ~ VDD + 0.5
V
Output voltage range
VO
- 0.3 ~ VDD + 0.5
V
Operating temperature range
TOPR
- 30 ~ + 85
°C
Storage temperature range
TSTG
- 40 ~ + 125
°C
NOTE:
(1). Voltages are all based on VSS = 0V.
(2). Voltage relationship: V0. Vg. Vm. VSS. XV0 must always be satisfied.
(3). For External Supply
(4).These is the stress ratings only above the table. "Absolute Maximum Ratings" may cause permanent damage to this
device.
Ver 1.3a
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10.2 DC CHARACTERISTICS
10.2.1
Basic Characteristics
(VSS=0V, Ta = -30 to 70°C)
Parameter
Symbol
Conditions
Related Pins
MIN
TYP
MAX
Logic Operating voltage
VDDI
-
*2) VDD
1.65
1.8
3.0
Analog Operating voltage
VDDA
-
*2) VDD2,3,4,5
2.4
2.75
3.3
Driving voltage input
VLCD
V0 - VSS
*3) V0, VSS
-
-
18.0
XVLCD
VSS – XV0
*3) VSS, XV0
-
-
18.0
*1) *2)
0.7VDD
-
VDD
*1) *2)
VSS
-
0.3VDD
0.8VDD
-
VDD
VSS
-
0.2VDD
-1.0
-
+1.0
Unit
V
High level input voltage
VIH
Low level input voltage
VIL
-
High level output voltage
VOH
IOH = -1.0mA
*2) SI, TE
Low level output voltage
VOL
IOL = +1.0mA
Input leakage current
IIL
VIN = VDD or VSS
Driver on resistance (SEG)
RONSEG
Vg = 5.0V
S0 to S395
-
3.5
1.0
Driver on resistance (COM)
RONCOM
V0 = 10.0V
C0 to C161
-
0.4
1.0
External oscillator frequency
fOSC
fFR=77Hz
CL
-
773.4
-
kHz
Booster1 output voltage
V0
VDD2
-
-
18
V
-
1.75
1.8
1.85
V
-
0.7
Vg/2
VDDA-0.7
V
VDD2
1.8
-
VDDAX2
V
VDD2
Vg-18
-
-
V
*1), *2)
µA
KΩ
range
Reference voltage
VREF
No load
Voltage follower output
Vm
Ta = 25°C
voltage
Booster2 output voltage
Vg
range
Booster3 output voltage
XV0
range
NOTE:
*1) Applies to IF0, IF1, IF3, /CS, /RST, /WR, /RD, A0 (SCL) and
D15-D2, D1 (A0) ,D0(SI) pins
*2) *3) When the measurement are performed with LCD module, Measurement Points are like below.
Ver 1.3a
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10.2.2 Current Consumption (Bare die)
Current consumption (mA)
Memory Data
Host
Frame
Mode of operation
I/F
Image
Access Control
(MY:MX:MV)
Host
interface
NOT active
- Normal Mode On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
Host interface active
Typical
Worst case
Frequency
77Hz±10 %
VDDA
VDDI
VDDA
VDDI
Note 1
X;X;X
0.6
0.15
1.0
0.3
Note 2
X;X;X
0.6
0.15
1.0
0.3
Note 3
X;X;X
0.6
0.15
1.0
0.3
Note 4
X;X;X
0.6
0.15
1.0
0.3
Note 5
X;X;X
0.6
0.15
1.0
0.3
Note 7
X;X;X
0.7
0.15
1.0
0.3
- Normal Mode On
- Partial Mode Off
- Idle Mode On
- Sleep Out Mode
- Normal Mode Off
- Partial Mode On
(32 lines)
- Idle Mode Off
- Sleep Out Mode
- Normal Mode Off
- Partial Mode On
(32 lines)
- Idle Mode On
- Sleep Out Mode
- Sleep In Mode
77Hz±10 %
Note 5
X;X;X
0.6
0.15
1.0
0.3
77Hz±10 %
Grey Levels
X;X;X
0.4
0.1
1.0
0.3
77Hz±10 %
Levels
X;X;X
0.4
0.1
1.0
0.3
Note 6
X;X;X
0.6
0.15
1.0
0.3
N/A
N/A
X;X;X
0.003
0.010
0.005
0.020
- Normal Mode On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
77Hz±10 %
65536 Colors
0;0;0
1.4
0.6
2.0
1.0
Note 8
0;0;1
1.4
0.6
2.0
1.0
0;1;0
1.4
0.6
2.0
1.0
0;1;1
1.4
0.6
2.0
1.0
1;0;0
1.4
0.6
2.0
1.0
1;0;1
1.4
0.6
2.0
1.0
1;1;0
1.4
0.6
2.0
1.0
1;1;1
1.4
0.6
2.0
1.0
NOTE:
CPU Access
@ 10fps
X Do not care
1. All pixels black
Typical Case:
TA = 25ºC
2. Checker board one by one
VDDA = 2.75V
3. Checker board 4 by 4
VDD = 1.8V
4. Grey-scale from top to bottom
5. 20% Black, 80%White
Worst Case:
6. Black & White Checker board 8 by 8.
TA = 25ºC
7. Absolute Worst Case Patterns: Defined by Display Supplier
VDDA = 2.4V to 3.3V
8. Absolute Worst Case Patterns and Sequences: Defined by Display Supplier
Includes Process Variance.
9. Absolute worst case VDDA current is less than 1mA in the case of Normal Mode On, Partial Mode Off,
Idle Mode Off, Sleep Out mode.
10. Absolute worst case VDDI current is less than 0.2mA in the case of Normal Mode On, Partial Mode Off,
Idle Mode Off, Sleep Out mode.
Ver 1.3a
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11 TIMING CHARACTERISTICS
11.1 Parallel Interface Characteristics bus (8080-series MCU)
Figure 11.1-1 Parallel Interface Characteristics bus (8080-series MCU)
(VSS=0V, VDDI=1.80V, VDDA=2.4V to 3.3V, Ta = -30 to 70°C)
Signal
A0
/CS
/WR
/RD (ID)
/RD (FM)
D[17:0]
Ver 1.3a
Symbol
TAST
TAHT
TCHW
TCS
TCSH
TRCS
TRCSFM
TCSF
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRATFM
TODH
Parameter
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select hold time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (FM)
Output disable time
191/216
MIN
15
15
10
50
10
60
60
10
230
130
80
160
20
80
250
80
80
50
0
10
MAX
340
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
3/2/2009
ST7669
(VSS=0V, VDDI= 2.8V, VDDA=2.4V to 3.3V, Ta = -30 to 70°C)
Signal
A0
/CS
/WR
/RD (ID)
/RD (FM)
D[17:0]
Symbol
TAST
TAHT
TCHW
TCS
TCSH
TRCS
TRCSFM
TCSF
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRATFM
TODH
Parameter
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select hold time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (FM)
Output disable time
MIN
15
15
0
30
10
60
60
10
150
80
50
140
20
60
160
50
60
30
10
10
MAX
340
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
Figure 11.1-2 Rising and Falling timing for Input and Output signal
Figure 11.1-3 Chip selection (CSX) timing
Ver 1.3a
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Figure 11.1-4 Write to read and Read to write timing
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD for Input signals.
Ver 1.3a
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11.2 Parallel Interface Characteristics bus (6800-series MCU)
Figure 11.2-1 Parallel Interface characteristics (6800-Series MCU)
(VSS=0V, VDDI=1.80V, VDDA=2.4V to 3.3V, Ta = -30 to 70°C)
Signal
A0
/CS
/R/W
E (ID)
E (FM)
D[17:0]
Ver 1.3a
Symbol
TAST
TAHT
TCHW
TCS
TRCS
TRCSFM
TCSF
TCSH
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRATFM
TODH
Parameter
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Chip select hold time
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (FM)
Output disable time
194/216
MIN
15
15
10
50
50
50
10
10
200
50
130
130
30
20
300
40
80
50
10
10
MAX
340
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
3/2/2009
ST7669
(VSS=0V, VDDI=2.8V, VDDA=2.4V to 3.3V,Ta = -30 to 70°C)
Signal
A0
/CS
R/W
E (ID)
E (FM)
D[17:0]
Ver 1.3a
Symbol
TAST
TAHT
TCHW
TCS
TRCS
TRCSFM
TCSF
TCSH
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRATFM
TODH
Parameter
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Chip select hold time
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (FM)
Output disable time
195/216
MIN
15
15
10
30
30
50
10
10
140
30
100
100
30
30
150
30
80
50
10
10
MAX
340
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
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ST7669
11.3 Serial Interface Characteristics (3-pin Serial)
Figure 11.3-1 3-pin Serial Interface Characteristics
(VSS=0V, VDDI=1.80V, VDDA=2.4V to 3.3V,Ta = -30 to 70°C)
Signal
/CS
SCL
SI
(DIN)
(DOUT)
Symbol
TCHW
TCSSW
TCSHW
TSCYCW
TSHW
TSLW
TSDS
TSDH
Parameter
/CS “H” pulse width
/CS-SCL setup time(Write)
/CS-SCL hold time(Write)
Serial clock cycle (Write)
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
Data setup time
Data hold time
MIN
10
10
15
130
90
40
10
MAX
-
Unit
ns
ns
ns
ns
ns
ns
ns
15
-
ns
Description
(VSS=0V, VDDI=2.80V, VDDA=2.4V to 3.3V,Ta = -30 to 70°C)
Signal
/CS
SCL
SI
(DIN)
(DOUT)
Ver 1.3a
Symbol
TCHW
TCSSW
TCSHW
TSCYCW
TSHW
TSLW
TSDS
TSDH
Parameter
/CS “H” pulse width
/CS-SCL setup time(Write)
/CS-SCL hold time(Write)
Serial clock cycle (Write)
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
Data setup time
Data hold time
196/216
MIN
10
10
15
80
50
30
10
MAX
-
Unit
ns
ns
ns
ns
ns
ns
ns
15
-
ns
Description
3/2/2009
ST7669
11.4 Serial Interface Characteristics (4-pin Serial)
Figure 11.4-1 4-pin Serial Interface Characteristics
(VSS=0V, VDDI=1.80V, VDDA=2.4V to 3.3V, Ta = -30 to 70°C)
Signal
/CS
A0
SCL
SI
(DIN)
(DOUT)
Symbol
TCSS
TCSH
TSCC
TCHW
TSAS
TSAH
TSCYCW
TSHW
TSLW
TSDS
TSDH
Parameter
Chip select setup time
Chip select hold time
Chip select setup time
Chip select setup time
Address setup time
Address hold time
Serial clock cycle (Write)
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
Data setup time
Data hold time
MIN
10
15
10
10
15
15
130
90
40
15
MAX
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
-
ns
Description
(VSS=0V, VDDI= 2.80V, VDDA=2.4V to 3.3V, Ta = -30 to 70°C)
Signal
/CS
A0
SCL
SI
(DIN)
(DOUT)
Ver 1.3a
Symbol
TCSS
TCSH
TSCC
TCHW
TSAS
TSAH
TSCYCW
TSHW
TSLW
TSDS
TSDH
Parameter
Chip select setup time
Chip select hold time
Chip select setup time
Chip select setup time
Address setup time
Address hold time
Serial clock cycle (Write)
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
Data setup time
Data hold time
197/216
MIN
10
15
10
10
15
15
80
50
30
15
MAX
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
-
ns
Description
3/2/2009
ST7669
11.5 Ouput access/disable timing measurement method
◆ Parallel interface (8080-series)
◆ Serial interface (3-line)
Note:
1. pull-up/pull-down resistor: 3KΩ ± 5% ; pull-up/pull-down capacitor: 8 or 30 pF ± 10%
2. Capacitances and resistances of the oscilloscope’s probe must be included externals components in these
measurements.
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11.6 Minimum value measurement
◆
Parallel interface (8080-series)
◆
Serial interface (3-line)
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11.7 Maximum value measurement
◆
Parallel interface (8080-series)
◆
Serial interface (3-line)
Ver 1.3a
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ST7669
12 RESET TIMING
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta = -30 to 70°C )
Rating
Item
Reset “L” pulse width
Reset time
Signal
/RST
Symbol
Condition
Units
Min.
Max.
10
—
—
5
tRW
tRT
us
ms
(*note 5)
—
200
ms
(*note 6,7)
Notes:
1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from
EEPROM (or similar device) to registers. This loading is done every time when there is HW reset cancel time
(tRT) within 5 ms after a rising edge of RST
2. Spike due to an electrostatic discharge on RST line does not cause irregular system reset according to the
table below:
RST Pulse
Action
Shorter than 5µs
Reset Rejected
Longer than 9µs
Reset
Between 5µs and 9µs
Reset starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which
maximum time is 200 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep
In -mode.) and then return to Default condition for Hardware Reset.
4. Spike Rejection also applies during a valid reset pulse as shown below:
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5. When Reset applied during Sleep In Mode.
6. When Reset applied during Sleep Out Mode.
7. It is necessary to wait 5msec after releasing RST before sending commands. Also Sleep Out command
cannot be sent for 200msec.
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ST7669
13 Instrunction Setup Flow
13.1
Command Table -- 2 enable Instruction Flow
13.1.1 Initial Flow (Command Table -- 2 ensable)
Note: About ST7669 Initial Code, please refer to “Initial ST7669” as below.
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13.1.2 Burning Flow (Command Table -- 2 ensable)
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void Initial_ST7669(void)
{
//-----------disable autoread + Manual read once ------------------------------Write(COMMAND,0xd7);
// Auto Load Set
Write(DATA,0xdf);
// Auto Load Disable
Write(COMMAND,0xE0);
// EE Read/write mode
Write(DATA,0x00);
// Set read mode
delayms(10);
// Delay 10ms
Write(COMMAND,0xE3);
// Read active
delayms(20);
// Delay 20ms
Write(COMMAND,0xE1);
// Cancel control
//---------------------------------- Sleep OUT --------------------------------------------Write(COMMAND, 0x11 );
// Sleep Out
Write(COMMAND, 0x28 );
// Display OFF
delayms(50);
//Delay 50ms
//--------------------------------Vop setting-----------------------------------------------Write(COMMAND,0xC0);
//Set Vop by initial Module
Write(DATA, 0x04);
//Vop = 14V
Write(DATA, 0x01);
// base on Module
//----------------------------Set
Register------------------------------------------
Write(COMMAND,0xC3);
// Bias select
Write(DATA,0x05);
// 1/9 Bias, base on Module
Write(COMMAND,0xC4);
// Setting Booster times
Write(DATA,0x07);
// Booster X 8
Write(COMMAND,0xC5);
// Booster eff
Write(DATA,0x21);
// BE = 0x01 (Level 2)
Write(COMMAND,0xCB);
// Vg with booster x2 control
Write(DATA,0x01);
// Vg from Vdd2
Write(COMMAND,0xCC);
// ID1 = 00
Write(DATA,0x00);
//
Write(COMMAND,0xCE);
// ID3 = 00
Write(DATA,0x00);
Write(COMMAND,0xB7);
// COM/SEG Direction for glass //
Write(DATA,0x48);
// Setting by LCD module
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Write(COMMAND,0xD0);
// Analog circuit setting
Write(DATA,0x1D);
//
Write(COMMAND, 0xB5 );
// N-Line
Write(DATA, 0x8D);
// Non-RST, 14-line inversion
Write(COMMAND,0xD7);
//Auto read Set
Write(DATA,0x9F);
//OTP Disable
Write(COMMAND,0xB4);
//PTL Mode Select
Write(DATA,0x18);
//PTLMOD Normal Mode
Write(COMMAND,0x3A);
// Color mode = 65k
Write(DATA,0x05);
//
Write(COMMAND,0x36);
// Memory Access Control //
Write(DATA,0xC8);
// Setting by LCD module
Write(COMMAND,0xB0);
// Duty = 160 duty
Write(DATA,0x9F);
Write(COMMAND,0x20);
// Display Inversion OFF
Write(COMMAND,0xF7 );
// command for temp sensitivity.
Write(COMMAND,0x06);
//
1. Set Gamma table for Module, please refer spec ch 9.1.73.
2. Set Temp compensation for Module, please refer spec ch 9.1.71.
Write(COMMAND,0x2A);
// COL//
Write(DATA,0x00);
// 0~127
Write(DATA,0x00);
Write(DATA,0x00);
Write(DATA,0x7F);
Write(COMMAND,0x2B);
// Page //
Write(DATA,0x00);
// 0~159
Write(DATA,0x00);
Write(DATA,0x00);
Write(DATA,0x9F);
}
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void Set_OTP_Register(void)
{
//--------------------------------Set OTP register---------------------------------------Write(COMMAND, 0xC7 );
//Vop offset = 0x00
Write(DATA, 0x00);
//
Write(DATA, 0x00 );
// apply by Module
Note#1
Write(COMMAND, 0xCD );
//ID2
Write(DATA, 0x80 );
Write(COMMAND, 0xB5 );
// N-Line
Write(DATA, 0x8D);
// Non-RST, 14-line inversion
Write(COMMAND,0xD0);
// Analog circuit setting
Write(DATA,0x1D);
//
Write(COMMAND,0xD7);
//Auto read Set
Write(DATA,0x9F);
//OTPB Disable
Write(COMMAND,0xB4);
//PTL Mode Select
Write(DATA,0x18);
//PTLMOD Normal Mode
}
void Fine_Tune_Vop(void)
{
//------------------------------------- Show Map ----------------------------------------------Show_Image();
//Display a image
//------------------------------------ Display ON ----------------------------------------------Write(COMMAND, 0x29 );
// Display On
//--------------------------------Fine tune Vop offset---------------------------------------Write( COMMAND, 0xC1);
//Fine tuning Vop here by command
or
0xc1(VopOffsetInc),0xc2(VopOffsetDec).
Write( COMMAND, 0xC2);
Note#2
}
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void OTP_Writing(void)
{
//--------------------------------Display OFF---------------------------------------Write(COMMAND, 0x28 );
// Display Off
Delayms(50);
// delay 50ms
//--------------------------------OTP writing---------------------------------------Write( COMMAND, 0x00F0 );
// Keep Frame Rate at 77Hz
Write( DATA, 0x0012 );
Write( DATA, 0x0012 );
Write( DATA, 0x0012 );
Write( DATA, 0x0012 );
Write( COMMAND, 0x00E4 );
//OTP selection
Write( DATA, 0x0058 );
// Select OTP
Write( COMMAND, 0x00E5 );
// Set OTP writing setup
Write( DATA, 0x000E );
Write( COMMAND, 0x00E0 );
// Read/write mode setting
Write( DATA, 0x0020 );
// Set Write mode
Delayms(100);
// Delay 100ms
Write( COMMAND, 0x00E2 );
// Write active
Delayms(100);
// Delay 100ms
Write( COMMAND, 0x00E1 );
// Cancel control
}
Note:
#1
If the Vop and display performace is not suitable after burning OTP，the Vop has to refine tune.
#2
In this section”+” & “-“ key button, please execute Write(COMMAND,0xC1) to increase one step at
Vop and execute Write(COMMAND,0xC2) to decrease one step at Vop, if necessary.
#3
The TC is turn on in burning flow. If LCD module is too dark or bright, it’s an effect of backlight.
Ver 1.3a
208/216
3/2/2009
ST7669
13.2
Ver 1.3a
Power ON Flow
209/216
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ST7669
13.3
Ver 1.3a
Power OFF Flow
210/216
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ST7669
14 ITO /FPC Layout Guide
14.1 ITO Layout of Power
VDD, VDD2~VDD5, VSS, VSS1, VSS2 & VSS4:
To avoid the noise in different power system affect other power system, please separate different power source on
ITO layout (VDD can be short together to get better performance).
To reduce the ITO resistance, the power source should have enough trace width (includes ITO width and FPC trace
width). So the separated ITO traces should be connected together by FPC.
=> The recommended solution is shown below.
Short by ITO
Separated by ITO
“Output”, “Input” and “Sensor” of built-in power circuits:
The V0, XV0 and Vg power circuits have output pins, input pins and a sensor input. To avoid the power noise affects
the sensor input of internal power circuits. The trace should be separated by ITO and should be connected together
by FPC. So that the “Sensor” pin has larger ITO resistance (for noise immunity).
The recommended layout topology is shown below: (XV0/Vg should use the same topology as V0)
Separated by ITO
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VPP:
This is the power source for programming the internal OTP. If the ITO resistance is too high, the operation current will
cause the voltage drop while programming OTP. Please try to keep the ITO resistance as low as possible.
14.2 ESD Protection
For ESD protection of the LCM, here are some recommendations:
1.
RST (Reset pin): Please increase the resistance of this pin. Here is an example:
Reset
2.
ESD Protection Ring: “Shielding Ground” is the first protection of ESD. By connecting the “Blue” (ITO) ring to
the FPC, the protection ring is finished.
FPC
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14.3 SPI ITO Suggestion
In order to get good transfer quality, the SI should have enough ITO width to reduce the ITO resistance (Interface SPI
3/4 Line). The recommended layout topology is shown below:
Ver 1.3a
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ST7669
15 Application Note
15.1
Ver 1.3a
8080 series 8-bit parallel
214/216
IF[3:1]
HHL
CLS
H (Internal OSC)
CSEL
H
C1
1uF/25V
C2
1uF/16V
C3
1uF/16V
3/2/2009
ST7669
15.2
Ver 1.3a
9-bit SPI mode (3 line)
215/216
IF[3:1]
LHL
CLS
H (Internal OSC)
CSEL
H
C1
1uF/25V
C2
1uF/16V
C3
1uF/16V
3/2/2009
ST7669
ST7669 Serial Specification Revision History
Version
Date
Description
0.0
2005/12/22
-----
1.0a
2007/01/31
Spec First Issue
1.1a
2007/6/22
Redefine the programming mechanism of
non-volatility memory.
Modify 3/4 -SPI timing chart.
1.2a
2007/9/26
Modify Power OFF Delay time = 200ms
1.3a
2009/01
Modify timing table
Ver 1.3a
Author
216/216
3/2/2009