STB70NF3LL N-channel 30V - 0.0075Ω - 70A - D2PAK Low gate charge STripFET™ II Power MOSFET General features Type VDSS RDS(on) ID STB70NF3LL 30V < 0.0095Ω 70A ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Conduction losses reduced ■ Switching losses reduced 3 1 D²PAK Description This application specific Power MOSFET is the third genaration of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. Internal schematic diagram Applications ■ Switching application Order codes Part number STB70NF3LLT4 July 2006 Marking Package 2 D PAK B70NF3LL@ Rev 7 Packaging Tape & reel 1/13 www.st.com 13 Contents STB70NF3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 ................................................ 8 STB70NF3LL 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol VDS VDGR Parameter Value Unit Drain-source voltage (VGS = 0) 30 V Drain-gate voltage (RGS = 20 kΩ) 30 V ± 16 V VGS Gate- source voltage ID(1) Drain current (continuous) at TC = 25°C 70 A ID Drain current (continuous) at TC = 100°C 50 A Drain current (pulsed) 280 A Total dissipation at TC = 25°C 100 W Derating factor 0.67 W/°C Peak diode recovery voltage slope 5.5 V/ns Single pulse avalanche energy 500 mJ -55 to 175 °C Value Unit IDM (2) PTOT (3) dv/dt EAS (4) Tstg TJ Storage temperature Operating junction temperature 1. Current limited by the package 2. Pulse width limited by safe operating area 3. ISD ≤70A, di/dt ≤350A/µs, VDD ≤V(BR)DSS, TJ ≤TJMAX 4. Starting TJ = 25 oC, ID = 35A, VDD = 25V Table 2. Symbol Thermal data Parameter RthJC Thermal resistance junction-case Max 1.5 °C/W RthJA Thermal resistance junction-ambient Max 62.5 °C/W Tl Maximum lead temperature for soldering purpose 300 °C 3/13 Electrical characteristics 2 STB70NF3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter Drain-source Breakdown voltage ID = 250 µA, VGS = 0 IDSS Zero gate voltage Drain current (VGS = 0) VDS = Max rating VDS = Max rating TC = 125°C IGSS Gate-body leakage Current (VDS = 0) VGS = ± 16 V VGS(th) Gate threshold voltage VDS = VGS ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V VGS = 4.5V ID = 35A ID = 18A V(BR)DSS Table 4. Symbol gfs Ciss Coss Crss 4/13 Test conditions Min Typ Max 30 Unit V 1 10 µA µA ±100 nA 1 V 0.0075 0.0095 0.010 0.012 Ω Ω Dynamic Parameter Test conditions Forward Transconductance VDS = 15V Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V f = 1MHz VGS = 0 ID = 35A Min Typ Max Unit 25 S 1650 540 130 pF pF pF STB70NF3LL Electrical characteristics Table 5. Symbol td(on) tr Switching times Parameter Test conditions Turn-on delay time Rise time ID = 35A VDD = 15V VGS = 4.5V RG = 4.7Ω (Resistive Load Figure 16) Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD= 15V ID= 70A VGS= 4.5V td(off) tf Turn-off delay time Fall time Table 6. Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM Min Typ Max 23 165 24 8.5 12 ns ns 33 27 28 VDD = 15 V ID = 35 A VGS = 4.5 V RG = 4.7Ω, (Resistive Load Figure 16) Unit nC nC nC ns ns Source drain diode Parameter Test conditions Min Typ Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 70 A VGS = 0 Reverse recovery time ISD = 70 A di/dt = 100A/µs TJ = 150°C Reverse recovery charge VDD = 20 V Reverse recovery current (see test circuit Figure 14) 42 52 2.5 Max Unit 70 280 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 5/13 Electrical characteristics STB70NF3LL 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Source-drain diode forward characteristics Figure 6. Static drain-source on resistance 6/13 STB70NF3LL Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 11. Normalized breakdown vs temperature 7/13 Test circuit 3 STB70NF3LL Test circuit Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test switching and diode recovery times circuit Figure 16. Unclamped inductive waveform 8/13 STB70NF3LL 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/13 Package mechanical data STB70NF3LL D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 D1 E 8 10 E1 0.368 0.315 10.4 0.393 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R 0.4 0º 0.015 4º 3 V2 1 10/13 STB70NF3LL 5 Packing mechanical data Packing mechanical data D2PAK FOOTPRINT TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0.075 0.082 inch MAX. MIN. MAX. 330 12.992 13.2 0.504 0.520 26.4 0.960 1.039 0.059 0795 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 MAX. R 50 1.574 T 0.25 0.35 0.0098 0.0137 W 23.7 24.3 0.933 0.956 * on sales type 11/13 Revision history 6 STB70NF3LL Revision history Table 7. 12/13 Revision history Date Revision Changes 21-Jun-2004 6 Preliminary version 25-Jul-2006 7 New template, no content change STB70NF3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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