STEL-1177 Data Sheet STEL-1177 32-Bit Resolution CMOS Phase and Frequency Modulated Numerically Controlled Oscillator R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES ■ ■ ■ ■ ■ ■ ■ HIGH CLOCK FREQUENCY - 60 MHz MAXIMUM OVER COMMERCIAL TEMPERATURE RANGE 40 MHz MAXIMUM OVER FULL MILITARY TEMPERATURE RANGE HIGH FREQUENCY RESOLUTION - 32-BITS, 14 milli-Hz @ 60 MHz WIDE OUTPUT BANDWIDTH - 0 TO 25 MHz @ 60 MHz CLOCK PRECISION PHASE MODULATION - 12-BITS, 0.09° RESOLUTION, CAN BE USED FOR LINEAR PM OR PULSESHAPED PSK PRECISION FREQUENCY MODULATION - 16 BITS RESOLUTION, CAN BE USED FOR LINEAR FM OR PULSE-SHAPED FSK QUADRATURE SIGNAL GENERATION - 12-BIT OUTPUTS WITH INDEPENDENT PHASE MODULATION PER CHANNEL BLOCK HIGH SPECTRAL PURITY - ALL SPURS < –75 dBc MICROPROCESSOR COMPATIBLE INPUTS LOW POWER DISSIPATION - COSINE CHANNEL CAN BE DISABLED TO REDUCE POWER 84 PIN PLCC OR CLDCC PACKAGES AND 84 PIN CERAMIC PGA PACKAGE AVAILABLE ■ ■ ■ TYPICAL ■ ■ ■ ■ APPLICATIONS FREQUENCY SYNTHESIZERS FSK AND PSK MODULATORS DIGITAL SIGNAL PROCESSORS HIGH SPEED HOPPED FREQUENCY SOURCES DIAGRAM PHLD ROUND C LOC K C IN ADDR 4 WRSTB PHSEL DATA SYNC FMSYNC ADDRESS SELEC T LOGIC C SEL 8 SINE PHASE MOD C ONTROL C OSINE PHASE MOD C ONTROL -PHASE BUFFER REGISTER A 12 32 RESET 13 SINE LUT 12 C OSINE LUT 12 SINE -PHASE ALU ALU BUFFER REGISTER PHASE AC C UMULATOR 32 (TO ALL REGISTERS) FRSEL FREQUENC Y MOD C ONTROL FMSUB FMLD SIMLD FMOD RATE SINE PHASE ALU 32 MUX -PHASE BUFFER REGISTER B 13 12 13 16 FMADDR FRLD C OSEN 2 2 STEL-1177 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 C OSINE PHASE ALU 13 C OSINE PIN CONFIGURATION 1. Plastic (PLCC) (/CM) or Ceramic (CLDCC) (/CC and /MC) Leaded Chip Carrier Package: 84 pin CLDCC Thermal coefficient, qja = 34°/W Package: 84 pin PLCC Thermal coefficient, qja = 30°/W 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 Top View 0.145" max. 1 1 8 8 8 8 8 7 7 7 7 7 1 0 9 8 7 6 5 4 3 2 1 4 3 2 1 0 9 8 7 6 5 1 1 8 8 8 8 8 7 7 7 7 7 1 0 9 8 7 6 5 4 3 2 1 4 3 2 1 0 9 8 7 6 5 12 13 14 74 73 0.017" 15 ± 0.004" (2) 16 1.190" ± 0.005" 0.05" nominal (1) 0.018" ± 0.004" (2) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 Top View 0.05" ± 0.005" (1) 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0.200" max. 1.154" ± 0.004" 1.150" ± 0.012" 0.035" nominal Notes: 1. Dimensions shown are for plastic package. Dimensions for ceramic package are similar. 2. Tolerances on pin spacing are not cumulative. 2. Ceramic Pin Grid Array (CPGA) (/CF and /MF) 1 2 3 4 5 6 7 8 9 1011 L K J H G F E D C B A 0.1" ± .005" 0.117" max. 0.18" ± .005" 0.018" ± .001" dia. 1.10" ± .02 "sq.. Notes: 1. 2. 3. 4. Tolerances on pin spacings are not cumulative. Corner pins have integral standoffs which raise the package 0.07" (nominal) above the mounting surface. Orientation determined by extra pin at location C3. Thermal coefficient, θja = 28°C/watt 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1177 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CONNECTIONS (C6) (A6) (A5) (B5) (C5) (A4) (B4) (A3) (A2) (B3) (A1) (B2) (C2) (B1) (C1) (D2) (D1) (E3) (E2) (E1) (F2) VSS FMOD7 FMOD8 FMOD9 FMOD10 FMOD11 FMOD12 FMOD13 FMOD14 FMOD15 VDD DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 WRSTB RESET 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 (F3) (G3) (G1) (G2) (F1) (H1) (H2) (J1) (K1) (J2) (L1) (K2) (K3) (L2) (L3) (K4) (L4) (J5) (K5) (L5) (K6) VSS CLOCK SIMLD ADDR3 ADDR2 ADDR1 ADDR0 CSEL FRSEL VSS VDD PHLD PHSEL CIN FRLD SYNC I.C. COS0(LSB) COS1 COS2 COS3 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 (J6) (J7) (L7) (K7) (L6) (L8) (K8) (L9) (L10) (K9) (L11) (K10) (J10) (K11) (J11) (H10) (H11) (F10) (G10) (G11) (G9) VSS COS4 COS5 COS6 COS7 COS8 COS9 COS10 COS11 VSS VDD SINE0(LSB) SINE1 SINE2 SINE3 SINE4 SINE5 SINE6 SINE7 SINE8 SINE9 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 (F9) (F11) (E11) (E10) (E9) (D11) (D10) (C11) (B11) (C10) (A11) (B10) (B9) (A10) (A9) (B8) (A8) (B6) (B7) (A7) (C7 VSS SINE10 SINE11 RATE0 RATE1 ROUND COSEN VSS FMLD FMSYNC VDD FMSUB FMADDR0 FMADDR1 FMOD0 FMOD1 FMOD2 FMOD3 FMOD4 FMOD5 FMOD6 Numeric pin connections are for PLCC and CLDCC packages, alphanumeric connections in parentheses are for PGA package. Note: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. FUNCTIONAL DESCRIPTION number in the ∆-Phase register represents the phase change for each cycle of the clock. This number is directly related to the output frequency by the following: The STEL-1177 Modulated Numerically Controlled Oscillator (MNCO) uses digital techniques to provide a cost-effective solution for low noise signal sources. The NCO features high frequency resolution with exceptional spectral purity of outputs up to 25 MHz. The STEL-1177 also features both phase and frequency modulation at rates up to 25% of the clock frequency. Separate 12-bit sine and cosine outputs are provided which can be phase modulated independently. The cosine channel can be disabled when not in use, reducing the power consumption by approximately 30%. The device combines low power 1.5µ CMOS technology with a unique architectural design resulting in a power efficient, high-speed sinusoidal waveform generator able to achieve fine tuning resolution and exceptional spectral purity at clock frequencies up to 60 MHz. The NCO is designed to provide a simple interface to an 8-bit microprocessor bus. fo= STEL-1177 232 where: fo is the frequency of the output signal and: fc is the clock frequency. The sine and cosine functions are generated from the 13 most significant bits of the phase accumulator. The frequency of the NCO is determined by the number stored in the ∆-Phase Register, which may be programmed by an 8-bit microprocessor, and the frequency modulation value loaded on the FMOD bus. The carrier frequency and the frequency modulation can be updated independently or simultaneously, using an internal synchronization circuit which ensures glitch-free updates. The NCO maintains a record of phase which is accurate to 32 bits. At each clock cycle, the number stored in the 32-bit ∆-Phase register is added to the previous value of the phase accumulator. The number in the phase accumulator represents the current phase of the synthesized sine and cosine functions. The Powered by ICminer.com Electronic-Library Service CopyRight 2003 fc x ∆-Phase The NCO generates a sampled sine wave where the sampling function is the clock. The practical upper limit of the NCO output frequency is about 40% of the clock frequency due to spurious components that are created by sampling. Those components are at 4 different phase modulation can be applied to the sine and cosine channels. frequencies greater than half the clock frequency, and become more difficult to remove by filtering as the output frequency approaches half the clock frequency. ∆-PHASE BUFFER REGISTERS A & B BLOCK The two ∆-Phase Buffer Registers are used to temporarily store the ∆-Phase data written into the device. This allows the data to be written asynchronously as four bytes per 32-bit ∆-Phase word. The data is transferred from these registers into the ∆Phase ALU after a falling edge on the FRLD input. The phase noise of the NCO output signal may be determined from the phase noise of the clock signal input and the ratio of the output frequency to the clock frequency. This ratio squared times the phase noise power of the clock specified in a given bandwidth is the phase noise power that may be expected in that same bandwidth relative to the output frequency. MUX BLOCK This block is used to select which ∆-Phase Buffer Register is used as the source of frequency data for the ∆-Phase ALU, by means of the FRSEL input. The NCO achieves its high operating frequency by making extensive use of pipelining in its architecture. The pipeline delays within the NCO represent 19 clock cycles. The dual ∆-Phase registers used in the STEL1177 allow the frequency and frequency modulation to be updated as rapidly as every fourth clock cycle, i.e. at 25% of the clock frequency. The pipeline delay associated with the phase modulator is only 12 clock cycles, since the phase modulating function is at the output of the accumulator. The phase modulation may also be changed as rapidly as every fourth clock cycle, at 25% of the clock frequency, resulting in a maximum modulation rate of 15 MHz with a clock frequency of 60 MHz. Note that when a phase or frequency change occurs at the output the change is instantaneous, i.e., it occurs in one clock cycle, with complete phase coherence. FUNCTION BLOCK FREQUENCY MODULATION CONTROL BLOCK This block controls the writing of the frequency modulation (FM) data on the FMOD15-0 bus into the FM Buffer Register, and the loading of this data into the ∆-Phase ALU. This data is multiplied by a factor of 2 0, 2 4, 2 8, or 2 12, according to the state of the FMADDR1-0 inputs, before being loaded into the ∆Phase ALU. This gives a wide range of values for the maximum deviation and resolution. The writing of the FM data can be either manual or automatic. It is controlled by the RATE 1-0 inputs, and the FMLD input or the FMSYNC output, depending on the mode selected. In addition, this block synchronizes the simultaneous updating of the carrier frequency data and FM data when the SIMLD input is high. DESCRIPTION ADDRESS SELECT LOGIC BLOCK This block controls the writing of data into the device via the DATA7-0 inputs. The data is written into the device on the rising edge of the WRSTB input, and the register into which the data is written is selected by the ADDR 3-0 inputs. The CSEL input can be used to selectively enable the writing of data from the bus. ∆-PHASE ALU BLOCK This block controls the updating of the ∆-Phase word used in the Accumulator. The frequency data from the Mux Block is loaded into this block after a falling edge on the FRLD input, and the FM data from the Frequency Modulation Control block is loaded after a falling edge on the FMLD input. However, if the SIMLD input is high, the FMLD input will load both sets of data simultaneously. The FM data is added to or subtracted from the carrier frequency data, the add/subtract operation being selected by the FMSUB input. This block also generates the SYNC output, which indicates the instant at which any phase or frequency change made at the inputs affects the SINE11-0 and COS11-0 output signals, and also the FMSYNC output, which controls the loading of the FM data on the FMOD15-0 bus in the automatic mode. SIN/COS PHASE MODULATION BLOCK This block includes the Phase Modulation Buffer Registers, and controls the source of the phase modulation (PM) data by means of the PHSEL input. When this signal is low, data from the DATA7-0 and ADDR3-0 inputs is written directly into the Phase ALUs after a falling edge on the PHLD input. The same PM data will be applied to both the Sine and Cosine Phase ALUs in this mode. When PHSEL is high, data is written into the Phase Modulation Buffer Registers from the DATA7-0 bus on the rising edge of the WRSTB input. The data will then be transferred into the Sine and Cosine ALUs after the next falling edge of PHLD. The sources of the PM data applied to the Sine and Cosine Phase ALUs will be the independent Sine and Cosine Phase Buffer Registers in this mode, so that ALU BUFFER REGISTER BLOCK This block stores the output from the ∆-Phase ALU for use in the Phase Accumulator. It also controls the time alignment of this data whenever it is changed, so that glitch-free updating of the accumulator pipeline is achieved. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1177 DATA 7 through DATA 0 The 8-bit DATA7-0 bus is used to program the two 32bit ∆-Phase Registers and the two 12-bit Phase Modulation Registers. DATA0 is the least significant bit of the bus. The data programmed into the ∆-Phase registers in this way determines the carrier frequency of the NCO. PHASE ACCUMULATOR BLOCK This block forms the core of the NCO function. It is a high-speed, pipelined, 32-bit parallel accumulator, generating a new sum in every clock cycle. A carry input (the CIN input) allows the resolution of the accumulator to be expanded by means of an auxiliary NCO or phase accumulator. The overflow signal is discarded, since the required output is the modulo(232) sum only. This represents the modulo(2π) phase angle. ADDR 3 through ADDR 0 The four address lines ADDR3-0 control the use of the DATA7-0 bus for writing frequency data to the ∆Phase Buffer Registers, and phase data to the Phase Buffer Registers, as shown in the table: PHASE ALU BLOCKS The two Phase ALUs perform the addition of the sine and cosine PM data to the Phase Accumulator output in the sine and cosine channels, respectively. The PM data words are both 12 bits wide, and these are added to the 13 most significant bits from the Phase Accumulator to form the modulated phase used to address the lookup tables. ADDR3 ADDR1 ADDR0 Register Field SINE AND COSINE LOOKUP TABLE BLOCKS These blocks are the sine and cosine memories. The 13 bits from the Phase ALUs are used to address these memories to generate the 12-bit SINE11-0 and COS11-0 outputs. The Cosine LUT can be disabled when not in use, to conserve power, by means of the COSEN input. 0 0 0 ∆-Phase Bits 0 (LSB)–7 0 0 1 ∆-Phase Bits 8–15 0 1 0 ∆-Phase Bits 16–23 0 1 1 ∆-Phase Bits 24–31 1 0 0 Sine Bits 0(LSB)–3* 1 0 1 Sine Bits 4-11* 1 1 0 Cosine Bits 0(LSB)–3* 1 1 1 Cosine Bits 4-11* ADDR3 ADDR2 INPUT SIGNALS RESET The RESET input is asynchronous and active low, and clears all the registers in the device. When RESET goes low, all registers are cleared within 20 nsecs, and normal operation will resume after this signal returns high. The data on the SINE11-0 and COS11-0 buses will then be invalid for 7 clock cycles, and thereafter will remain at the value corresponding to zero phase until new frequency or modulation (either frequency or phase) data is loaded with the FRLD, FMLD, or PHLD inputs after the RESET returns high. 0 ∆-Phase Buffer Register 'A' 0 1 ∆-Phase Buffer Register 'B' 1 X Phase Buffer Registers WRSTB The Write Strobe input is used to latch the data on the DATA7-0 bus into the device. On the rising edge of the WRSTB input, the information on the 8-bit data bus is transferred to the buffer register selected by the ADDR3-0 bus. FRSEL The Frequency Register Select line is used to control the mux which selects the ∆-Phase Buffer Register in use. When this signal is high ∆-Phase Buffer Register 'A' is selected as the source for the ∆-Phase ALU, and the frequency corresponding to the data stored in this register will be generated by the NCO after the next falling edge on the FRLD input. When this line is low, ∆-Phase Buffer Register 'B' is selected as the source. CSEL The Chip Select input is used to control the writing of data into the chip. It is active low. When this input is high all data writing via the DATA7-0 bus is inhibited. STEL-1177 0 * Note: The Phase Buffer Registers are 12-bit registers. When the least significant bytes of these registers are selected (ADDR3-0 =1XX0), DATA7-4 is written into Bits 3–0 of the registers. In all cases, it is not necessary to reload unchanged bytes, and the byte loading sequence may be random. CLOCK All synchronous functions performed within the NCO are referenced to the rising edge of the CLOCK input. The CLOCK signal should be nominally a square wave at a maximum frequency of 60 MHz. A nonrepetitive CLOCK waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 5 nanoseconds. Powered by ICminer.com Electronic-Library Service CopyRight 2003 Register Selected 6 FRLD The Frequency Load input is used to control the transfer of the data from the ∆-Phase Buffer Registers to the ∆-Phase ALU. The data at the output of the Mux Block must be valid during the clock cycle following the falling edge of FRLD. The data is then transferred during the subsequent cycle. The frequency of the NCO output will change 19 clock cycles after the FRLD command due to pipelining delays. FMADDR 1 through FMADDR 0 The two inputs FMADDR1-0 set the deviation of the frequency modulation by controlling the significance of the FM data in relation to the carrier frequency data. The FM data word will be multiplied by 20, 24, 28, or 212 according to the state of FMADDR1-0, and the consequent resolution and maximum values of the deviation are shown in the table below. The values shown are for a clock frequency of 60 MHz. PHSEL The Phase Source Select input selects the sources of data for the Phase ALUs. When it is high the sources are the Sine and Cosine Phase Buffer Registers. They are loaded from the DATA7-0 bus by setting address line ADDR3 high, as shown in the tables. When PHSEL is low, the sources for the phase modulation data are the DATA7-0 and ADDR3-0 inputs, and the data will be loaded independently of the states of WRSTB and CSEL. The data on these 12 lines is presented directly as a parallel 12-bit word to both Phase ALUs, allowing high-speed phase modulation. The 12-bit value is latched into the Phase ALUs by means of the PHLD input. The data on the ADDR3-0 lines is mapped onto Phase Bits 3 to 0 and the data on the DATA7-0 lines are mapped onto Phase Bits 11 to 4 in this case. When using the parallel phase load mode CSEL and/or WRSTB should remain high to ensure that the phase data is not written into the phase and frequency buffer registers of the STEL-1177. FMFM- Mult. factor Maximum ADDR1 ADDR0 of FM data deviation 0 0 1 1 0 20 1 2 4 ± 14.6 KHz 0.22 Hz 2 8 ± 234 KHz 2 12 ± 3.75 MHz 57 Hz 0 1 14 mHz 3.6 Hz FMLD The FM Load input controls the writing of the frequency modulation data on the FMOD15-0 bus and the FMSUB input into the device. When RATE1-0= 00 the data at the output of the Frequency Modulation Control Block must be valid during the clock cycle following the falling edge of FMLD. The data is then transferred during the subsequent cycle. When RATE1-0= 01, 10 or 11 are selected the FM data will be loaded automatically without the use of the FMLD input. Note that FMLD must be held low during automatic operation, otherwise the loading will be inhibited. PHLD The Phase Load input is used to control the latching of the Phase Modulation data into the Phase ALUs. The 12-bit data at the output of the Phase Modulation Control Block must be valid during the clock cycle following the falling edge of PHLD. The data is then transferred during the subsequent cycle. The 12-bit phase data is added to the 12 most significant bits of the accumulator output, so that the MSB of the phase data represents a 180° phase change. The source of this data will be determined by the state of PHSEL. The phase of the NCO output will change 12 clock cycles after the PHLD command, due to pipelining delays. SIMLD The Simultaneous Load input allows the carrier frequency data from the Mux Block and the FM data to be updated simultaneously. When SIMLD is low, only the FM data will be updated after a falling edge on FMLD. When this input is high, both the FM data and carrier frequency data will be updated simultaneously. When SIMLD is low at least four clock cycles are required between falling edges of FMLD and FRLD to ensure glitch-free changes in the outputs. FMOD 15 through FMOD 0 The Frequency Modulation bus is a 16-bit bus on which the FM data is loaded into the STEL-1177. The data should be a 16-bit unsigned number. R A T E 1-0 The RATE1-0 signals control the rate at which the FM data on the FMOD15-0 bus is added to or subtracted from the carrier frequency, as shown in the table below: FMSUB The FM Subtract input controls the Add/Subtract operation of the ∆-Phase ALU. When it is high the FM data on the FMOD15-0 bus will be subtracted from the carrier frequency, and when it is low the FM data will be added to the carrier frequency. In this way the FM data can be treated as a 17-bit signed-magnitude number, where the FMSUB signal is the sign bit. FMSUB is latched at the same time as FMOD15-0. RATE1 RATE0 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ± 915 Hz Resolution Modulation Update Rate 0 0 Manual, with FMLD signal 0 1 Every 4th clock cycle 1 0 Every 8th clock cycle 1 1 Every 16th clock cycle STEL-1177 C O S 11-0 The signal appearing on the COS 11-0 outputs is derived from the 13 most significant bits of the Phase Accumulator. The 12-bit cosine function is presented in offset binary format. When the phase accumulator is zero, e.g., after a reset, the decimal value of the output is 4095 (FFFH). When the phase modulation is zero the value of the output for a given phase value follows the relationship: CIN The Carry Input is an arithmetic carry to the least significant bit of the Accumulator. Normal operation of the NCO requires that CIN be set at a logic 0. When CIN is set at a logic 1 the effective value of the ∆-Phase register is increased by one. This allows the resolution of the accumulator to be expanded for higher frequency resolution. ROUND The ROUND input controls the precision of the SINE11-0 and COS11-0 outputs. When the ROUND input is set high, the sine and cosine signals appearing on the SINE11-0 and COS11-0 buses are accurate to 12 bits. In some instances it may be desirable to use only the 8 MSBs of these outputs. In such circumstances the outputs appearing on the SINE11-0 and COS11-0 buses can be rounded to present a more accurate 8-bit representation of the signal by setting the ROUND input low. COS11-0=2047 x cos (360 x (phase+0.5)/8192)°+2048 The result is accurate to within 1 LSB. However, when ROUND is set low, the value appearing on the COS110 outputs will be rounded and will follow the relationship: COS11-4=127 x cos (360 x (phase+0.5)/8192)°+128 The data appearing on the COS3-0 outputs will not be meaningful under these circumstances. SYNC The Sync output indicates the instant in time when the frequency, FM, or PM change made at the inputs affects the SINE11-0 and COS11-0 output signals. The normally high SYNC output goes low for one clock cycle 19 clock cycles after an FRLD or FMLD command, and 12 clock cycles after a PHLD command, to indicate the end of the pipeline delay and the start of the new steady state condition. COSEN The Cosine Enable input controls the power supply to the Cosine Lookup Table. When it is low the cosine lookup table in the STEL-1177 is disabled, and only the SINE11-0 outputs will be valid. This reduces the power consumption of the device by approximately 30%. OUTPUT SIGNALS FMSYNC The FM Sync output indicates the instant in time when the FM data on the FMOD bus is written into the device. The FMSYNC output is normally high and goes low for one clock cycle at a frequency depending on the state of the RATE1-0 inputs. In the automatic modulation modes (RATE1-0 ≠ 00) the data on the FMOD15-0 bus will be written into the FM Buffer Register on the rising edge of the clock following the falling edge of FMSYNC. This signal can be used to synchronize the updating of the FM data externally. S I N E 11-0 The signal appearing on the SINE 11-0 outputs is derived from the 13 most significant bits of the Phase Accumulator. The 12-bit sine function is presented in offset binary format. When the phase accumulator is zero, e.g., after a reset, the decimal value of the output is 2049 (801H). When the phase modulation is zero the value of the output for a given phase value follows the relationship: SINE11-0=2047 x sin (360 x (phase+0.5)/8192)°+2048 The result is accurate to within 1 LSB. However, when ROUND is set low, the value appearing on the SINE11-0 outputs will be rounded and will follow the relationship: SINE11-4=127 x sin (360 x (phase+0.5)/8192)°+128 The data appearing on the SINE3-0 outputs will not be meaningful under these circumstances. STEL-1177 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. All voltages are referenced to VSS. Symbol Tstg Parameter Range Units –40 to +125 –65 to +150 Storage Temperature °C (Plastic package) °C (Ceramic package) VDDmax Supply voltage on VDD –0.3 to + 7 volts VI(max) Input voltage –0.3 to VDD + 0.3 volts Ii DC input current ± 10 mA RECOMMENDED Symbol VDD Ta OPERATING CONDITIONS Parameter Range Units Supply Voltage +5 ± 5% +5 ± 10% Volts (Commercial) Volts (Military) 0 to +70 –55 to +125 °C (Commercial) °C (Military) Operating Temperature (Ambient) D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS = 0 V, Ta = –55° to 125° C, Military) Symbol Parameter IDD(Q) Supply Current, Quiescent IDD Supply Current, Operational VIH(min) High Level Input Voltage Min. Typ. Max. 1.0 7.0 Units Conditions mA Static, no clock mA/MHz Standard Operating Conditions 2.0 volts Logic '1' Extended Operating Conditions 2.25 volts Logic '1' 0.8 volts Logic '0' 110 µA CIN and CSEL, VIN = VDD VIL(max) Low Level Input Voltage IIH(min) High Level Input Current IIH(min) High Level Input Current 10 µA All other inputs, VIN = VDD IIL(max) Low Level Input Current –10 µA CIN and CSEL, VIN = VSS IIL(max) Low Level Input Current –15 –45 –130 µA All other inputs, VIN = VSS VOH(min) High Level Output Voltage 2.4 4.5 volts IO = –4.0 mA VOL(max) Low Level Output Voltage IOS Output Short Circuit Current CIN COUT 10 35 0.2 0.4 volts IO = +4.0 mA 20 65 130 mA VOUT = VDD, VDD = max –10 –45 –130 mA VOUT = VSS, VDD = max pF pF All inputs All outputs Input Capacitance Output Capacitance 2 4 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1177 NCO RESET SEQUENCE t RS RESET 6 CLOCK EDGES CLOCK 1 SINE 11-0 COS 11-0 NCO 2 3 4 5 6 801H NOT VALID FREQUENCY CHANGE SEQUENCE CSEL ADDR 3-0 DON'T CARE DON'T CARE tSU WRSTB tHD DATA 7-0 tWR DON'T CARE DON'T CARE 19 CLOCK EDGES CLOCK tSU tCH tCL FRLD tW FSYNC tCD OLD FREQUENCY SINE 11-0 COS 11-0 STEL-1177 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 NEW FREQUENCY NCO 1. PHASE PHSEL=0. CHANGE DIRECT SEQUENCE LOADING. 12 CLOCK EDGES CLOCK tSU DATA 7-0 ADDR 3-0 DON'T CARE DON'T CARE tHD tSU PHLD tW PSYNC OLD PHASE NEW PHASE SINE 11-0 COS 11-0 ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ± 5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ± 10%, VSS=0 V, Ta=–55° to 125° C, Military) Commercial Symbol Parameter Military Min. Typ. Max. Min. Typ. Max. Units tRS RESET pulse width 20 25 nsec. tSR RESET to CLOCK Setup 10 12 nsec. tSU DATA, ADDR or CSEL 5 5 nsec. 5 5 nsec. Conditions to WRSTB or PHLD Setup and FRLD, PHLD, FMLD or FMOD to CLOCK Setup tHD DATA, ADDR or CSEL to WRSTB or PHLD Hold and FRLD, PHLD, FMLD or FMOD to CLOCK Hold 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1177 NCO PHASE CHANGE SEQUENCE 2. PHSEL=1. BUS LOADING. CSEL ADDR 3-0 DON'T CARE DON'T CARE tSU WRSTB tHD DATA 7-0 tWR DON'T CARE DON'T CARE 12 CLOCK EDGES CLOCK tSU PHLD tW PSYNC OLD PHASE NEW PHASE SINE 11-0 COS 11-0 ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ± 5%, VSS=0 V, Ta= 0° to 70° C, Chimerical VDD= 5.0 V ± 10%, VSS=0 V, Ta=–55° to 125° C, Military) Commercial Symbol tCH Parameter CLOCK high Military Min. Typ. Max. Min. Typ. Max. Units 5 nsec. fCLK = 60 MHz nsec. fCLK = 40 MHz nsec. fCLK = 60 MHz 8 nsec. fCLK = 40 MHz 8 nsec. 8 tCH tW CLOCK low WRSTB, FRLD, PHLD 5 5 Conditions or FMLD pulse width tCD CLOCK to output delay 7 12 (All outputs) STEL-1177 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 3 20 nsec. Load = 15 pF NCO FREQUENCY MODULATION SEQUENCE 1 . RATE = 00. MANUAL LOADING. 19 CLOCK EDGES CLOCK tHD tSU FMOD 15-0 DON'T CARE VALID DON'T CARE tSU FMLD tW FMSYNC tCD SYNC OLD FREQUENCY NEW FREQUENCY SINE 11-0 COS 11-0 2 . RATE ≠ 00. AUTOMATIC LOADING. (RATE = 01 shown) 4 CLOCK CYCLES CLOCK FMOD 15-0 DON'T CARE VALID DON'T CARE VALID DON'T CARE tHD tSU FMSYNC SINE 11-0 COS 11-0 FMLD 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1177 HIGH-SPEED FREQUENCY CHANGE SIMLD is high). In the diagram below, ∆-Phase Buffer Register A is being loaded in clock cycles 1 through 4, while the contents of ∆-Phase Buffer Register B are being transferred, because FRSEL was low during the falling edge of FRLD. The reverse process happens during clock cycles 5 through 8, and the process then repeats starting in clock cycle 9. The FRLD signal can be used to clock a bistable latch to generate the FRSEL signal. The maximum update rate is 25%. The frequency of the STEL-1177 NCO can be changed as rapidly as 25% of the clock frequency. This is done by synchronizing the writing to the two ∆-Phase Buffer Registers, and updating both every eight clock cycles. The timing for this procedure is shown below. Each ∆-Phase Buffer Register is loaded while the contents of the other are being transferred into the ALU Buffer Register. The sequence for a load cycle begins on the rising edge of the clock following a falling edge of FRLD (or a falling edge of FMLD if 1 2 3 4 5 6 7 8 9 CLOCK WRSTB ADDR 0111 0000 0001 0010 0011 0100 0101 0110 0111 0000 FRLD FRSEL be slightly more than half the clock period at high speeds some advantage can be gained by generating the clock by inverting the WRSTB signal, rather than the other way around. This makes the propagation delay of the inverter used work for the timing requirements instead of against them, since the hold time requirement from the previous rising edge of the clock (tHD) is 2 nsec. It is possible to update the frequency at up to 25% of the clock frequency using only one buffer register. The timing for this procedure is shown in the diagram below, and must be adhered to rigorously in order to assure adequate setup and hold times. The most critical factor is the setup time (tSU) for the WRSTB relative to the clock (rising edge to rising edge). This must be 8 nsec. for correct operation. Since this may 1 2 3 4 5 6 7 8 9 CLOCK tSU tHD WRSTB ADDR 3-0 0001 0010 0011 0000 0001 FRLD FRSEL=1 STEL-1177 Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 0010 0011 0000 0001 APPLICATIONS INFORMATION USING THE STEL-1177 IN A HIGH-SPEED PHASE MODULATOR WRITE FROM FREQ. LOAD µC DATA 0-7 ADDR 0-3 By routing the data and address lines from the microcontroller via 2:1 multiplexers (e.g. 74HC157) the MNCO can be set up from the microcontroller and then phase modulated at high-speed from an external source. The PHSEL line should be set to a logic 0 to enable this mode of operation. The FROM PHASE system shown modulates all 12 bits. In a typical PSK system only MOD. 1 to 4 bits of modulation will be used, simplifying the system considerably. APPLICATION CONTROL PROCESSOR FREQUENCY MODULATOR EXAMPLE STEL1177 NCO - A WRSTB FRLD 4 4 4 PHASE0-11 FREQ./PH SEL PHASE LOAD 4 4 4 B A/B A B A/B A B A/B FM CARRIER BPF 12-25 MHz D/A 12 D0 . . D3 D4 . . STEL-1177 D7 MNCO A0 . . A3 PHLD HIGH-LINEARITY SINE A GENERATOR BPF 95-108 MHz 95-108 MHz CLK ÷2 120 MHz OSCILLATOR The STEL-1177 can be used for high-linearity frequency modulation. The FM port has 16-bit resolution and linearity, and this can be used to generate a very high-quality signal for FM broadcasting in the 88-108 MHz frequency band. The audio signal can be digitized at a very high sampling rate, either directly or by interpolation, to maximize the performance capability of the system. SPECTRAL PURITY The sine and cosine signals generated by the STEL1177 have 12 bits of amplitude resolution and 13 bits of phase resolution which results in spurious levels which are theoretically at least 75 dB down. The highest output frequency the NCO can generate is half the clock frequency (f c/2), and the spurious components at frequencies greater than fc/2 can be removed by filtering. As the output frequency fo of In many applications the NCO is used with a digital to analog converter (DAC) to generate an analog waveform which approximates an ideal sinewave. The spectral purity of this synthesized waveform is a function of many variables including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the DAC. 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1177 the NCO approaches fc/2, the "image" spur at fc– fo (created by the sampling process) also approaches fc/2 from above. If the programmed output frequency is very close to fc/2 it will be virtually impossible to remove this image spur by filtering. For this reason, the maximum practical output frequency of the NCO should be limited to about 40% of the clock frequency. the second harmonic frequency will be higher than the Nyquist frequency, 50% of the clock frequency. When this happens, the image of the harmonic at the frequency fc– 2fo, which is not harmonically related to the output signal, will become intrusive since its frequency falls as the output frequency rises, eventually crossing the fundamental output when its frequency crosses through fc/3. It would be necessary to select a DAC with better dynamic linearity to improve the harmonic spur levels. (The dynamic linearity of a DAC is a function of both its static linearity and its dynamic characteristics, such as settling time and slew rates.) At higher output frequencies the waveform produced by the DAC will have large output changes from sample to sample. For this reason, the settling time of the DAC should be short in comparison to the clock period. As a general rule, the DAC used should have the lowest possible glitch energy as well as the shortest possible settling time. A spectral plot of the NCO output after conversion with a DAC (Sony CX20202A-1) is shown below. In this case, the clock frequency is 60 MHz and the output frequency is programmed to 6.789 MHz. This 10-bit DAC gives better performance than any of the currently available 12-bit DACs at clock frequencies higher than 10 or 20 MHz. The maximum nonharmonic spur level observed over the entire useful output frequency range in this case is –74 dBc. The spur levels are limited by the dynamic linearity of the DAC. It is important to remember that when the output frequency exceeds 25% of the clock frequency, TYPICAL SPECTRUM Center Frequency: 6.7 MHz Frequency Span: 10.0 MHz Reference Level: –5 dBm Resolution Bandwidth: 1 KHz Video Bandwidth: 3 kHz Scale: Log, 10 dB/div Output frequency: 6.789 MHz Clock frequency: 60 MHz STEL-1177 Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. For Further Information Call or Write INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 Copyright © Intel Corporation, December 15, 1999. All rights reserved Powered by ICminer.com Electronic-Library Service CopyRight 2003