STK22C48 16 Kbit (2K x 8) AutoStore nvSRAM Features Functional Description ■ 25 ns and 45 ns access times ■ Hands off automatic STORE on power down with external 68 µF capacitor ■ STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power down ■ RECALL to SRAM initiated by software or power up ■ Unlimited Read, Write, and Recall cycles ■ 1,000,000 STORE cycles to QuantumTrap The Cypress STK22C48 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. A hardware STORE is initiated with the HSB pin. ■ 100 year data retention to QuantumTrap ■ Single 5V+10% operation ■ Commercial and industrial temperatures ■ 28-pin 300 mil and (330 mil) SOIC package ■ RoHS compliance Logic Block Diagram VCC Quantum Trap 32 X 512 A5 A7 A8 A9 DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 STATIC RAM ARRAY 32 X 512 RECALL STORE/ RECALL CONTROL HSB COLUMN I/O INPUT BUFFERS DQ 1 POWER CONTROL STORE ROW DECODER A6 VCAP COLUMN DEC A 0 A 1 A 2 A 3 A 4 A 10 DQ 7 OE CE WE Cypress Semiconductor Corporation Document Number: 001-51000 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 30, 2009 [+] Feedback STK22C48 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC V CC V CAP 1 28 NC 2 27 WE A7 3 26 HSB 25 A8 A6 4 A5 5 A4 6 A3 7 A2 8 24 A9 23 NC Top View 22 OE (Not To Scale) 21 A 10 28-SOIC A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 V SS 14 15 DQ3 Table 1. Pin Definitions Pin Name Alt A0–A10 IO Type Input DQ0-DQ7 Description Address Inputs. Used to select one of the 2,048 bytes of the nvSRAM. Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. VSS Ground Ground for the Device. The device is connected to ground of the system. VCC Power Supply Power Supply Inputs to the Device. HSB Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). VCAP Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No Connect No Connect. This pin is not connected to the die. Document Number: 001-51000 Rev. ** Page 2 of 14 [+] Feedback STK22C48 SRAM Read The STK22C48 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–10 determines the 2,048 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA (Read cycle 1). If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (Read cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. :( N2KP 9FF N2KP 9&$3 +6% 5) %\SDVV The STK22C48 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK22C48 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. Figure 2. AutoStore Mode 5) Y Device Operation 9VV In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 μF capacitor. In this mode, the AutoStore function of the STK22C48 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms STORE cycle. To prevent unneeded STORE operations, automatic STOREs and those initiated by externally driving HSB LOW are ignored, unless at least one WRITE operation takes place since the most recent STORE or RECALL cycle. An optional pull up resistor is shown connected to HSB. This is used to signal the system that the AutoStore cycle is in progress. AutoStore Inhibit mode If an automatic STORE on power loss is not required, then VCC is tied to ground and +5V is applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK22C48 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered with the HSB pin. It is not permissible to change between these three options “on the fly”. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor between 68 µF and 220 µF (+20%) rated at 6V should be Document Number: 001-51000 Rev. ** Page 3 of 14 [+] Feedback STK22C48 Data Protection 9FF :( N2KP 9&$3 N2KP 5) %\SDVV Figure 3. AutoStore Inhibit Mode +6% The STK22C48 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the STK22C48 is in a Write mode (both CE and WE are low) at power up after a RECALL or after a STORE, the Write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The STK22C48 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. 9VV Hardware STORE (HSB) Operation The STK22C48 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK22C48 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a Write to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver. SRAM Read and Write operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK22C48 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM Read operations take place. If a Write is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the STK22C48 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK22C48 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Hardware Protect The STK22C48 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage conditions. When VCAP<VSWITCH, all externally initiated STORE operations and SRAM Writes are inhibited. AutoStore can be completely disabled by tying VCC to ground and applying +5V to VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs are only initiated by explicit request using either the software sequence or the HSB pin. Low Average Active Power CMOS technology provides the STK22C48 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between ICC and Read or Write cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK22C48 depends on the following items: ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of Reads to Writes ■ CMOS versus TTL input levels ■ The operating temperature ■ The VCC level ■ IO loading Hardware RECALL (Power Up) During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. Document Number: 001-51000 Rev. ** Page 4 of 14 [+] Feedback STK22C48 device drives HSB LOW for 20 ns at the onset of a STORE. When the STK22C48 is connected for AutoStore operation (system VCC connected to VCC and a 68 μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK22C48 attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and abort the STORE attempt. Figure 4. Current Versus Cycle Time (Read) Best Practices nvSRAM products have been used effectively for over 15 years. While ease of use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware should not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. ■ Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). ■ The VCAP value specified in this data sheet includes a minimum and a maximum value size. The best practice is to meet this requirement and not exceed the maximum VCAP value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger VCAP value to make sure there is extra store charge should discuss their VCAP size selection with Cypress. Figure 5. Current Versus Cycle Time (Write) Preventing Store The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it must overpower the internal pull down device. This Table 2. Hardware Mode Selection CE WE HSB A10–A0 Mode IO Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active[1] L L H X Write SRAM Input Data Active X X L X Nonvolatile STORE Output High Z ICC2[2] Notes 1. I/O state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE. 2. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode, inhibiting all operations until HSB rises. Document Number: 001-51000 Rev. ** Page 5 of 14 [+] Feedback STK22C48 Maximum Ratings Voltage on DQ0-7 or HSB .......................–0.5V to Vcc + 0.5V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Temperature under bias.............................. –55°C to +125°C Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V Voltage on Input Relative to Vss............ –0.6V to VCC + 0.5V Power Dissipation ......................................................... 1.0W DC Output Current (1 output at a time, 1s duration).... 15 mA Operating Range Range Commercial Industrial Ambient Temperature VCC 0°C to +70°C 4.5V to 5.5V -40°C to +85°C 4.5V to 5.5V DC Electrical Characteristics Over the operating range (VCC = 4.5V to 5.5V) [3] Parameter Description Average VCC Current ICC1 ICC2 ICC3 ICC4 Average VCC Current during STORE Average VCC Current at tRC= 200 ns, 5V, 25°C Typical ISB1[4] Average VCAP Current during AutoStore Cycle Average Vcc Current (Standby, Cycling TTL Input Levels) ISB2[4] VCC Standby Current IILK IOLK VIH Input Leakage Current Off State Output Leakage Current Input HIGH Voltage VIL VOH VOL VBL VCAP Input LOW Voltage Output HIGH Voltage Output LOW Voltage Logic ‘0’ Voltage on HSB Output Storage Capacitor Test Conditions Min Max 85 65 90 65 Unit mA mA mA mA 3 mA 10 mA 2 mA 25 18 26 19 1.5 mA mA mA mA mA -1 -5 +1 +5 μA μA 2.2 VCC + 0.5 0.8 V tRC = 25 ns Commercial tRC = 45 ns Dependent on output loading and cycle Industrial rate. Values obtained without output loads. IOUT = 0 mA. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE WE > (VCC – 0.2V). All other inputs cycling. Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE tRC = 25 ns, CE > VIH Commercial tRC = 45 ns, CE > VIH Industrial CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL IOUT = –4 mA except HSB IOUT = 8 mA except HSB IOUT = 3 mA Between VCAP pin and Vss, 6V rated. 68 uF -10%, +20% nom. VSS – 0.5 2.4 61 0.4 0.4 220 V V V V µF Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 100 Years 1,000 K Notes 3. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 4. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-51000 Rev. ** Page 6 of 14 [+] Feedback STK22C48 Capacitance In the following table, the capacitance parameters are listed.[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 8 pF 7 pF 28-SOIC (300 mil) 28-SOIC (330 mil) Unit TBD TBD °C/W TBD TBD °C/W TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Thermal Resistance In the following table, the thermal resistance parameters are listed.[5] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Figure 6. AC Test Loads R1 963Ω R1 963Ω For Tri-state Specs 5.0V 5.0V Output Output 30 pF R2 512Ω 5 pF R2 512Ω AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% to 90%) ...................... <5 ns Input and Output Timing Reference Levels .................... 1.5V Note 5. These parameters are guaranteed by design and are not tested. Document Number: 001-51000 Rev. ** Page 7 of 14 [+] Feedback STK22C48 AC Switching Characteristics SRAM Read Cycle Parameter Cypress Alt Parameter tELQV tACE tAVAV, tELEH tRC [6] tAVQV tAA [7] tGLQV tDOE tAXQX tOHA [7] tELQX tLZCE [8] tEHQZ tHZCE [8] [8] tGLQX tLZOE tGHQZ tHZOE [8] tELICCH tPU [5] [5] tEHICCL tPD 25 ns Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Min 45 ns Max Min 25 Max 45 25 45 25 10 45 20 5 5 5 5 10 15 0 0 10 15 0 0 25 45 Unit ns ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7] W5& $''5(66 W $$ W2+$ '4'$7$287 '$7$9$/,' Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6] W5& $''5(66 W$&( W3' W/=&( &( W+=&( 2( W+=2( W'2( W/=2( '4'$7$287 '$7$9$/,' W 38 ,&& $&7,9( 67$1'%< Notes 6. WE and HSB must be High during SRAM Read cycles. 7. Device is continuously selected with CE and OE both Low. 8. Measured ±200 mV from steady state output voltage. Document Number: 001-51000 Rev. ** Page 8 of 14 [+] Feedback STK22C48 SRAM Write Cycle Parameter Cypress Parameter 25 ns Description Alt tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [8,9] tLZWE [8] Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 45 ns Max 25 20 20 10 0 20 0 0 Min Max 45 30 30 15 0 30 0 0 10 5 14 5 Unit ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 9. SRAM Write Cycle 1: WE Controlled [10, 11] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 10. SRAM Write Cycle 2: CE Controlled [10, 11] tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 9. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 10. HSB must be high during SRAM Write cycles. 11. CE or WE must be greater than VIH during address transitions. Document Number: 001-51000 Rev. ** Page 9 of 14 [+] Feedback STK22C48 AutoStore or Power Up RECALL Parameter Alt tHRECALL [12] tSTORE [14, 15] tDELAY [13] VSWITCH VRESET tVSBL[10] tRESTORE tHLHZ tHLQZ , tBLQZ Description Power up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level Low Voltage Trigger (VSWITCH) to HSB Low STK22C48 Min Max 550 10 1 4.0 4.5 3.6 300 Unit μs ms μs V V ns Switching Waveform Figure 11. AutoStore/Power Up RECALL WE Notes 12. tHRECALL starts from the time VCC rises above VSWITCH. 13. CE and OE low for output behavior. 14. CE and OE low and WE high for output behavior. 15. HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store takes place. Document Number: 001-51000 Rev. ** Page 10 of 14 [+] Feedback STK22C48 Hardware STORE Cycle Parameter Alt Description tDHSB [13, 16] tRECOVER, tHHQX Hardware STORE High to Inhibit Off tPHSB tHLHX tHLBL Hardware STORE Pulse Width Hardware STORE Low to STORE Busy STK22C48 Min Max Unit 700 ns 300 ns 15 ns Switching Waveform Figure 12. Hardware STORE Cycle Note 16. tDHSB is only applicable after tSTORE is complete. Document Number: 001-51000 Rev. ** Page 11 of 14 [+] Feedback STK22C48 STK22C48 - N F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 25 - 25 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SOIC Ordering Information Speed (ns) 25 45 Ordering Code Package Diagram Package Type STK22C48-NF25TR 51-85026 28-pin SOIC (300 mil) STK22C48-NF25 51-85026 28-pin SOIC (300 mil) STK22C48-SF25TR 51-85058 28-pin SOIC (330 mil) STK22C48-SF25 51-85058 28-pin SOIC (330 mil) STK22C48-NF25ITR 51-85026 28-pin SOIC (300 mil) STK22C48-NF25I 51-85026 28-pin SOIC (300 mil) STK22C48-SF25ITR 51-85058 28-pin SOIC (330 mil) STK22C48-SF25I 51-85058 28-pin SOIC (330 mil) STK22C48-NF45TR 51-85026 28-pin SOIC (300 mil) STK22C48-NF45 51-85026 28-pin SOIC (300 mil) STK22C48-SF45TR 51-85058 28-pin SOIC (330 mil) STK22C48-SF45 51-85058 28-pin SOIC (330 mil) STK22C48-NF45ITR 51-85026 28-pin SOIC (300 mil) STK22C48-NF45I 51-85026 28-pin SOIC (300 mil) STK22C48-SF45ITR 51-85058 28-pin SOIC (330 mil) STK22C48-SF45I 51-85058 28-pin SOIC (330 mil) Operating Range Commercial Industrial Commercial Industrial All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts Document Number: 001-51000 Rev. ** Page 12 of 14 [+] Feedback STK22C48 Package Diagrams Figure 13. 28-Pin (300 mil) SOIC (51-85026) NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT 14 DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. 1 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.39] MIN. MAX. 4. PACKAGE WEIGHT 0.85gms 0.300[7.62] 0.394[10.01] * 0.419[10.64] 15 28 PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.026[0.66] 0.032[0.81] SEATING PLANE 0.697[17.70] 0.713[18.11] 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.050[1.27] 0.013[0.33] 0.004[0.10] 0.019[0.48] 0.0118[0.30] * TYP. 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] * 51-85026-*D Figure 14. 28-Pin (330 mil) SOIC (51-85058) 51-85058-*A Document Number: 001-51000 Rev. ** Page 13 of 14 [+] Feedback STK22C48 Document History Page Document Title: STK22C48 16 Kbit (2K x 8) AutoStore nvSRAM Document Number: 001-51000 Rev. ECN No. Orig. of Change Submission Date ** 2625139 GVCH/PYRS 01/30/09 Description of Change New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-51000 Rev. ** Revised January 30, 2009 Page 14 of 14 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback