INTEGRATED CIRCUITS DATA SHEET TDA2579C Synchronization circuit with synchronized vertical divider system for 60 Hz Preliminary specification File under Integrated Circuits, IC02 Philips Semiconductors January 1994 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C FEATURES Vertical part Synchronization and horizontal part • fV = 60 Hz (M) system • Horizontal sync separator and noise inverter • Vertical synchronization pulse separator without external components and two integration times • Horizontal oscillator • Zener diode reference voltage source for the vertical sawtooth generator and vertical comparator • Horizontal output stage • Horizontal phase detector (sync to oscillator) • Divider system with three different reset enable windows • Triple current source in the phase detector with automatic selection • Synchronization is set to 528 divider ratio when no vertical sync pulse and no video transmitter is identified • Normal phase detector time constant is increased to fast during the vertical blanking period (external switching for VTR conditions not necessary) • Divider window is forced to wide window when a vertical sync pulse is detected within the window provided by reset divider and end of vertical blanking period, on condition that the voltage on pin 18 is ≤1.2 V • Slow phase detector time constant and gated sync pulse operation are automatically switched on by an internal sync pulse noise level detection circuit • Divider ratio is 528 (fV = 60 Hz) for DC signal on pin 5 • Linear negative-going sawtooth generated via the divider system (no frequency adjustment) • Fast phase detector time is switched on for locking • Time constant externally switchable • Comparator with low DC level feedback signal • Inhibit of horizontal phase detector and video transmitter identification circuit during equalizing pulses and vertical sync pulse • Output stage driver • fV = 60 Hz identification output combined with mute function • Inhibit of horizontal phase detector during separated vertical sync pulse • Start of vertical blanking is shifted to the start of the pre-equalizing pulses when the divider ratio is between 522 and 528 lines per picture • Second phase detector for storage compensation of the line output stage • Guard circuit which generates the vertical blanking pulse level on the sandcastle output pin 17 when the feedback level at pin 2 is not within the specified limits. • 3-level sandcastle pulse generator • Automatic adaption of the burst key pulse width • Video transmitter identification circuit • Stabilizer and supply circuit for starting the horizontal oscillator and output stage directly from the mains rectifier GENERAL DESCRIPTION The TDA2579C is an integrated circuit generating all requirements for synchronization of its horizontal oscillator and output stage plus those of the vertical part which comprises a divider system, sawtooth generator, comparator and output stage. The TDA2579C is almost identical to the TDA2579B. It is optimized for the M (60 Hz) TV system. • Horizontal output current with constant duty factor value of 55% • Duty factor of the horizontal output pulse is 55% when the horizontal flyback pulse is absent. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE TDA2579C 18 DIL plastic SOT102 January 1994 2 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply I16 minimum required current for starting horizontal oscillator and output stage 6.2 − − mA V10 main supply voltage − 12 − V I10 supply current − 70 − mA Input signals V5-9 sync pulse input amplitude 0.05 − 1 V I12 horizontal flyback pulse input current 0.2 1 − mA V2 vertical comparator input voltage AC (peak-to-peak value) − 0.8 − V DC − 1 − V Output signals V11 horizontal output voltage (open collector) I11 = 25 mA − − 0.5 V V1 vertical output stage driver (emitter follower) I1 = 1.5 mA 5 − − V V17 sandcastle output voltage levels burst key 9.8 − − V horizontal blanking − 4.5 − V vertical blanking − 2.5 − V VIDEO TRANSMITTER IDENTIFICATION OUTPUT; note 1 V13 output voltage no sync pulse present − − 0.32 V I13 output current no sync pulse present − − 5 mA V13 output voltage sync pulse present; divider ratio <576 − 7.6 − V Note 1. Open collector loaded with external resistor to positive supply. January 1994 3 January 1994 mute 60 Hz 22 Ω 4 12 V 15 k Ω 47 nF 22 µF R S = 5.6 k Ω 2.2 µF video signal input COINCIDENCE DETECTOR NOISE INVERTER VERTICAL/ HORIZONTAL SYNC SEPARATOR 5 150 pF 150 nF vertical feedback 2 4.7 k Ω sandcastle output 17 15 100 nF 14 SUPPLY SWITCH 10 12 V 1 nF flyback pulse input 12 9 11 MGA791 TDA2579C TOO LOW CURRENT PROTECTION HORIZONTAL OUTPUT PHASE DETECTOR ϕ2 FLYBACK PULSE PROTECTION REFERENCE ϕ2 16 22 µF START CIRCUIT STABILIZER 2.7 nF 6.2 mA HORIZONTAL OSCILLATOR 33 k Ω PULSE WIDTH MODULATOR SANDCASTLE OUTPUT BURST KEY ANTITOP NOISE DETECTOR Fig.1 Block diagram. vertical drive 1 VERTICAL OUTPUT VERTICAL GUARD CIRCUIT VERTICAL BLANKING ϕ1 REFERENCE SYNC PULSE NOISE LEVEL DETECTOR 4.7 nF VERTICAL COMPARATOR VERTICAL ZENER REFERENCE DIVIDER GATING to vertical deflection current measuring resistor 3 8 1.2 k Ω PHASE DETECTOR ϕ1 68 nF I to pin 16 6.8 k Ω horizontal drive Synchronization circuit with synchronized vertical divider system for 60 Hz 220 k Ω 4 VERTICAL/ OSCILLATOR SAWTOOTH GENERATOR VIDEO TRANSMITTER IDENTIFICATION 150 k Ω 13 18 7 6 1 kΩ 6.8 µF Philips Semiconductors Preliminary specification TDA2579C Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C PINNING SYMBOL PIN DESCRIPTION VOUT 1 vertical driver output FB 2 vertical feedback input SAW 3 vertical sawtooth generator VDC 4 vertical deflection current output VID 5 video signal input CSL 6 slicing level storage capacitor RSL 7 slicing level resistor ϕ1 8 phase detector ϕ1 GND 9 VP VOUT 1 18 DET FB 2 17 SC SAW 3 16 STAB VDC 4 15 H OSC ground (0 V) VID 5 14 H SHIFT 10 main supply voltage (+12 V) CSL 6 13 MUTE HOUT 11 horizontal driver output RSL 7 12 FLYB FLYB 12 horizontal flyback pulse input ϕ1 8 11 H OUT MUTE 13 mute output GND 9 10 HSHIFT 14 horizontal picture shift capacitor VP HOSC 15 horizontal oscillator frequency setting STAB 16 start circuit stabilizer input SC 17 sandcastle output DET 18 coincidence detector output TDA2579C MGA790 Fig.2 Pin configuration. divider system for generating the vertical sawtooth at pin 3. Thus no vertical frequency adjustment is required. FUNCTIONAL DESCRIPTION The TDA2579C generates both horizontal and vertical drive signals, a 3-level sandcastle output pulse, a transmitter identification signal and 60 Hz window information. The circuit operation is restricted to the M (fV = 60 Hz) system. Vertical part (pins 1, 2, 3 and 4) The horizontal oscillator and horizontal output stage functions are started via the supply current into pin 16. The required current has a typical value of 5 mA which can be taken directly from the mains rectifier. The horizontal output transistor at pin 11 is not conducting until the supply current at pin 16 has reached its typical value. The starting circuit has a hysteresis of approximately 1 mA. The horizontal output current of pin 11 starts at a duty cycle of 60%. All other IC functions are enabled via the main supply voltage on pin 10. The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an internal frequency doubling circuit, thus the horizontal oscillator is operating at its nominal line frequency and one line period equals 2 clock pulses. No vertical frequency adjustment is required due to the divider system. The divider system operates with 3 different reset windows for maximum interference/disturbance protection. The pin 16 supply system enables slaved synchronized switch mode systems in which the horizontal output signal of the TDA2579C is used as master signal. In such a system the 12 V supply (main supply at pin 10) can be generated by the line output stage. The windows are activated via an up/down counter. The counter increases its value by 1 each time the separated vertical sync pulse is within the window being searched. The count is reduced by 1 when the vertical sync pulse is not present. An internal Zener diode reference voltage is used for the vertical processing part. The IC embodies a synchronized The reset of the counter system (clock pulse 0) is at half a line period after the start of the vertical pulse at pin 5. January 1994 5 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C When the up/down counter reaches the value of 14 approved M TV-norm pulses the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode. The standard TV-norm condition provides maximum protection for video recorders playing tapes with anti-copy guards. In accordance with the convention for the M system, field one line 1 number 1 starts at the first equalizing pulse, the reset of the divider system is at the start of line 4 for the first field and in the middle of line 265 for the second field. Divider system MODE A: LARGE (SEARCH) WINDOW Divider ratio between 488 and 576. This mode is valid for the following five conditions: 1. Divider is locking to a new transmitter. MODE D: NO TV TRANSMITTER FOUND 2. Divider ratio found, not being within the narrow window limits. At pin 18 the voltage level is less than 1.2 V. 3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1. In this condition, only noise is present and no vertical sync pulse is detected, the divider is reset to count 528. In this way a stable picture display at normal height is achieved. 4. External forced setting. This can be achieved by loading pin 18 with a 220 Ω resistor to earth or by connecting a 3.6 V stabistor diode between pin 18 and ground. MODE E: VIDEO TAPE RECORDERS IN FEATURE MODE NTSC (M system) 3-speed video tape recorders 5. A vertical sync pulse was detected within the interval provided by reset divider (at 528) and the end of the vertical blanking while the voltage at pin 18 is ≤1.2 V. It should be noted that some VTRs operating in the picture search mode, generate such distorted pictures that the no TV transmitter detection circuit can be activated as the voltage on pin 18 drops below 1.2 V. This would imply a rolling picture (Mode D). In general VTRs do use a re-inserted vertical pulse in the feature mode. Therefore the divider system has been designed such that the divider is forced to the wide window mode when V18 is below 1.2 V and a vertical sync pulse is detected within the window provided by the reset divider at 528 and the end of the vertical blanking period. MODE B: NARROW WINDOW Divider ratio between 522 and 528. The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved vertical sync pulses in the large window mode. When count 12 is reached the vertical sync pulse is tested for the standard TV-norm being the divider ratio 525. When this value is valid for the 12th vertical pulse, the up/down counter is reset to 0 and the up/down counter tests for a valid 525 divider ratio. When at the 12th vertical pulse the divider ratio is not equal to n = 525 then the divider system remains in the narrow window mode and remains testing for the standard TV-norm. When the divider operates in this mode and a vertical sync pulse is missing within the window the divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the divider system switches over to the large window mode. General The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync pulse. The width of this pulse depends on the divider mode. For the divider mode A the start is generated at the reset of the divider. In modes B and C the anti-top-flutter pulse starts at the beginning of the first equalizing pulse sequence. The anti-top-flutter ends after the second equalizing pulse sequence. The vertical blanking pulse is also generated via the divider system. The start is at the reset of the divider while the blanking pulse ends at count 34, the middle of line 21 of field 1 and at the end of line 283 of field 2. MODE C: STANDARD TV-NORM Divider ratio 525; fV = 60 Hz. The vertical blanking pulse generated at the sandcastle output pin 17 is made by adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of the first equalizing pulse when the divider operates in the B or C mode. When the up/down counter has reached its maximum value of 12 in the narrow window mode and the divider ratio equals n = 525 the information applied to the up/down counter is changed such that now the standard divider ratio value is tested and the up/down counter is reset to 0. January 1994 6 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz Vertical sawtooth Integration time of the vertical synchronization pulse separator To generate a vertical linear sawtooth voltage a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF. The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the capacitor is monitored by a comparator which is also activated at reset. When the capacitor has reached a voltage value of 5.0 V the voltage is kept constant until the charging period ends. The charging period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is discharged by an npn transistor current source the value of which can be set by an external resistor connected between pin 4 and ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current source at pin 3. The pnp current source on pin 4 is connected to an internal Zener diode reference voltage which has a typical voltage of 7.5 V. The recommended operating current range is 10 to 75 µA. The resistor at pin 4 should be 100 to 770 kΩ. By using a double current mirror concept the vertical sawtooth pre-correction voltage can be set to the required value by external components connected between pins 3 and 4 or by superimposing a correction voltage in series with the earth connection of the resistor connected to pin 4. The vertical amplitude is set by the current of pin 4. The vertical sync separator has two integration times: • long time; typical 19 µs, valid for 1.8 ≤ V18 ≤ 7.8 V (no noise detected) • short time; typical 12 µs, valid for noise detected and V18 ≥ 1.2 V. When V18 drops below 1.2 V, the integration time is forced back to 19 µs to prevent switching of the divider system to the wide window mode for noise only conditions. Sync separator, phase detector and TV-station identification (pins 5, 6, 7 and 18) SYNC SEPARATOR The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level is stored in the capacitor at pin 6. The slicing level value can be chosen by the value of the external resistor connected between pins 6 and 7. The value is given by the formula: RS p = ---------------------- × 100 ( R S value in kΩ ) . 5.3 × R S Vertical feedback Where RS is the resistor connected between pins 6 and 7 and the top sync levels equals 100%. The recommended resistor value is 5.6 kΩ. The vertical feedback voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and AC = 0.8 V (p-p). The low DC voltage value improves the picture bounce behaviour as less parabola compensation is required. Even a DC-coupled feedback circuit is possible. BLACK LEVEL DETECTOR A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with a duty factor of 50% and the flyback pulse at pin 12. In this way the TV transmitter identification operates also for all DC conditions at input pin 5 (no video modulation, plain carrier only). During the vertical blanking interval the slicing detector is inhibited by a signal which starts with the anti-top-flutter pulse and ends with the reset of the vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced and separation of the vertical sync pulse is improved. An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. Vertical guard The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous voltage level of 2.5 V in the sandcastle output signal of pin 17. This results in blanking of the picture displayed, thus preventing a burnt-in horizontal line. Vertical driver output The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately 170 Ω. The output pin is also connected to an internal current source with a sink current of 0.25 mA. January 1994 TDA2579C 7 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz For quick locking of a new TV station starting from a noise only signal condition (normal time constant) a special circuit is incorporated. A new TV station which is not locked to the horizontal oscillator will result in a voltage decrease below 0.1 V at pin 18. This will activate a field period counter which switches the phase detector to fast for 3 field periods during the vertical scan period. The horizontal oscillator will now lock to the new TV station and as a result, the voltage on pin 18 will increase to approximately 6.5 V. When pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is switched off and the divider is set to the large window. In general the mute signal is switched off within 5 ms (C18 = 47 nF) after reception of a new TV signal. When the voltage on pin 18 reaches a level of 5 V, usually within 15 ms, the field counter is switched off and the time constant is switched from fast to normal during the vertical scan period. NOISE LEVEL DETECTOR The IC also embodies a built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at the middle of the horizontal sync pulse. When a signal-to-noise level (S/N) of ≤19 dB is detected a counter circuit is activated. Video voltage (black-to-white signal) S/N = 20 log -----------------------------------------------------------------------------------------------Noise (RMS) A video input signal is processed as "acceptable noise free" when 12 out of 15 sync pulses have a noise level below 19 dB for successive field periods. The sync pulses are processed during a 15 line width gating period generated by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. The use of a filter of 1 kΩ and 150 pF in front of pin 5 reduces the noise content of the CVBS signal by approximately 6 dB. When the "acceptable noise free" condition is found the phase detector of pin 8 is switched to not gated and normal time constant. When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync pulse detection. At the same time the integration time of the vertical sync pulse separator is reduced providing V18 > 1.2 V. PHASE DETECTOR (SEE If the new TV station is weak, the sync noise detector is activated. This will result in a change over of pin 18 voltage from 6.5 V to approximately 10 V. When pin 18 exceeds the level of 7.8 V the phase detector is switched to slow time constant and gated sync pulse condition. The phase detector output current during the blanking period is now reduced from 2 mA to 1.35 mA. When desired, most conditions of the phase detector can also be set by external means in the following way: • fast time constant, TV transmitter identification circuit not active, connect pin 18 to ground (pin 9) FIG.3) The phase detector circuit is connected to pin 8. This circuit consists of 3 separate phase detectors which are activated depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. For normal and fast time constants all three phase detectors are activated during the vertical blanking period, this with the exception of the anti-top-flutter pulse period, and the separated vertical sync pulse time. As a result, phase jumps in the video signal related to the video head, take over of video recorders are quickly restored within the vertical blanking period. At the end of the blanking period the phase detector time constant is increased by a factor of 1.4. In this way there is no requirement for external VTR time constant switching, and thus all station numbers are suitable for signals from VTR, video games or home computers. January 1994 TDA2579C • fast time constant, TV transmitter identification circuit active, connect a 220 kΩ resistor between pin 18 and ground; this condition can also be set by using a 3.6 V stabistor diode instead of a resistor • slow time constant (with the exception of the vertical blanking period), connect pin 18 via a 10 kΩ resistor to +12 V (pin 10); in this condition the transmitter identification circuit is not active • no switching to slow time constant required (transmitter identification circuit active), connect a 6.8 V Zener diode between pin 18 and ground. 8 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C mute (pin 13) 1 gating ϕ 1 detector 1 ϕ 1 detector I 8 0.35 mA 1 ϕ 2 detector I 8 1.0 mA not gated 1 ϕ 3 detector I 8 0.65 mA not gated 1 0 0 0 0 0 A voltage (pin 18) B 0.1 V C 1.2 V D 1.8 V E 3.5 V F 5V G 7.8 V MGA792 Fig.3 Operation of the three phase detector circuits. Explanation of areas A to G shown in Fig.3 A switching over to new TV station activates 3 field period counter B noise only condition C TV transmitter identification hysteresis range D fast time constant C-E fast time constant hysteresis range F normal time constant G sync pulse noise level detection circuit forces pin 18 to >7.8 V while signal-to-noise level <19 dB; slow time constant and gated sync pulse operation. January 1994 Supply (pins 9, 10 and 16) The IC has been designed such that the horizontal oscillator and output stage operate a very low supply current into pin 16. The horizontal oscillator starts at a supply current of approximately 4 mA (V16 approximately 6 V). The horizontal output stage is forced into the non-conducting stage until the supply current has reached a typical value of 5 mA. The circuit has been designed such that after starting the horizontal output function, a current drop of approximately 1 mA is allowed. The starting circuit has the ability to derive the main supply (pin 10) from the horizontal output stage. The horizontal output signal can also be used as oscillator signal for synchronized switched-mode power supplies. 9 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz The horizontal output pulse duration is 29 µs HIGH for storage times between 1 µs and 17 µs (flyback pulse of 12 to 29 µs). A higher storage time increases the HIGH time. Horizontal picture shift is possible by forcing an external charge or discharge current into the capacitor at pin 14. The maximum allowed starting current is 9.7 mA (Tamb = 25 °C). The main supply should be connected to pin 10 and pin 9 should be used for ground. When the voltage on pin 10 increases from zero to its final value (typ. 12 V) a part of the supply current of the starting circuit is taken from pin 10 via internal diodes and the voltage on pin 16 will stabilize on a typical value of 9.3 V. In stabilized conditions (V10 > 10 V) the minimum required supply current into pin 16 is approximately 2.5 mA. All other IC functions are switched on via the main supply voltage on pin 10. When this voltage reaches a value of approximately 7 V the horizontal phase detector is activated and the vertical ramp on pin 3 is started. The second phase detector circuit and burst pulse circuit are started when the voltage on pin 10 reaches the stabilized voltage value of pin 16 typical 9.3 V. Mute output and 60 Hz identification (pin 13) The collector of an npn transistor is connected to pin 13. When the voltage on pin 18 drops below 1.2 V (no TV transmitter) the npn transistor is switched on. When the voltage on pin 18 increases to a level of approximately 1.8 V (new TV transmitter found) the npn transistor is switched off. This function is available when pin 13 is connected to pin 10 (+12 V) via an external pull-up resistor of 10 to 20 kΩ. When no TV transmitter is identified the voltage on pin 13 will be LOW (<0.5 V). When an M-system TV transmitter with a divider ratio <576 (60 Hz) is found an internal pnp transistor with its emitter connected to pin 13 will force the output voltage down to approximately 7.6 V. To close the second phase detector loop a flyback pulse must be applied to pin 12. When no flyback pulse is detected the duty factor of the horizontal output stage is 50%. For remote switch-off pin 16 can be connected to ground (via a npn transistor with a collector series resistor of approximately 500 Ω) which decreases pin 16 voltage to ≤5 V and switches off the horizontal output pulse. Sandcastle output (pin 17) The sandcastle output pulse generated at pin 17 has three different voltage levels. The highest level (10.4 V) can be used for burst gating and black level clamping. The second level (4.5 V) is obtained from the horizontal flyback pulse at pin 12 and is used for horizontal blanking. The third level (2.5 V) is used for vertical blanking and is derived via the vertical divider system. For 60 Hz the blanking pulse duration is 34 clock pulses started from the reset of the vertical divider system. Horizontal oscillator, horizontal output transistor and second phase detector The horizontal oscillator is connected to pin 15. The frequency is set by an external RC combination between pin 15 and ground (pin 9). The open collector horizontal output stage is connected to pin 11. An internal Zener diode configuration limits the open voltage of pin 11 to approximately 14.5 V. The horizontal output transistor at pin 11 is blocked until the current into pin 16 reaches a value of approximately 5 mA. A higher current results in a horizontal output signal at pin 11, which starts with a duty factor of approximately 40% HIGH. The duty factor is set by an internal current-source-loaded npn emitter follower stage connected to pin 14 during starting. When pin 16 changes over to voltage stabilization the npn emitter follower and current source load at pin 14 are switched off and the second phase detector is activated, provided a horizontal flyback pulse is present at pin 12. When no flyback pulse is detected at pin 12 the duty factor of the horizontal output stage is set to 50%. The phase detector circuit at pin 14 compensates for storage time in the horizontal deflection output state. January 1994 TDA2579C For TV signals which have a divider ratio between 522 and 528 the vertical blanking pulse is started at the first equalizing pulse. 10 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT I16 start current − 9.7 mA VP supply voltage − 13.2 V Ptot total power dissipation − 1.2 W Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −25 +70 °C V10 = 0 V THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER THERMAL RESISTANCE from junction to ambient in free air 50 K/W CHARACTERISTICS VP = V10 = 12 V; I16 = 6.2 mA; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage (pin 10) I16 supply current (pin 16) 10 12 13.2 V V10 = 0 V 6.2 − 9.7 mA V10 = 1 to 10 V; Tamb ≤ 70 °C 6.2 − 8.7 mA V10 > 10 V 2.5 − 9.7 mA note 1 V16 stabilized voltage (pin 16) 8.8 9.3 9.7 V I10 current consumption (pin 10) − 70 85 mA 1.5 3.1 3.75 V Video input (pin 5) V5 top sync level V5(p-p) sync pulse amplitude (peak-to-peak value) note 2 0.05 0.6 1 V SL slicing level note 3 35 50 65 % td delay between video input and detector output see Fig.5 0.2 0.3 0.55 µs S/N signal-to-noise ratio with sync pulse noise level detector circuit active CVBS = 1 V without filter at pin 5; note 4 − 19 − dB − 3 − dB − 0.7 1 V Sync pulse HYS noise level detector circuit hysteresis Noise gate (pin 5) V5 switching level January 1994 11 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz SYMBOL PARAMETER TDA2579C CONDITIONS MIN. TYP. MAX. UNIT First control loop (pin 8) horizontal oscillator to synchronization signal ∆f holding range ±700 ±800 − Hz ∆f catching range ±700 ±800 ±1100 Hz αCS control sensitivity video with respect to burst key and flyback pulse: slow time constant note 5 − 2 − kHz/µs normal time constant note 6 − 5 − kHz/µs fast time constant note 6 − 3 − kHz/µs ϕ10 phase modulation due to hum on the supply note 7 line (peak-to-peak value) − 0.2 − µs/V ϕ16 phase modulation due to hum on the input current (peak-to-peak value) − 0.08 − µs/V note 8 Second control loop (pin 14) horizontal flyback to horizontal oscillator ∆td/∆to control sensitivity 200 300 600 µs/µs td control range td = 10 µs 1 − 45 µs td control range for constant duty factor horizontal output 1 29 − tFB − control edge of horizontal output signal (pin 11) − positive − − 25 − µA/µs − − ±60 µA µs Phase adjustment (pin 14) via second control loop αCS control sensitivity I14 maximum allowed control current td = 10 µs Horizontal oscillator (pin 15) Cosc = 2.7 nF; Rosc = 34.2 kΩ fH frequency (no sync) − 15 625 − Hz ∆fH spread (fixed external components, no sync) − − ±4 % ∆fH frequency deviation between starting point output signal and stabilized condition − +5 +8 % TC temperature coefficient − −1.10-4 − K Horizontal output (pin 11) open collector V11H HIGH level output voltage − − 13.2 V V11 start voltage protection (internal Zener diode) 13 − 15.8 V I16L LOW level input current protection output enabled − 5.0 6.2 mA V11L LOW level output voltage start condition I11 = 10 mA − 0.1 0.5 V δ duty factor output current during starting I16 = 6.2 mA 50 60 70 % V11L LOW level output voltage normal condition I11 = 25 mA − 0.3 0.5 V δ duty factor output current without flyback pulse pin 12 45 50 55 % January 1994 12 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz SYMBOL PARAMETER tOH duration of output pulse HIGH TC ∆HW/Hd TDA2579C CONDITIONS storage time horizontal deflection stage = 10 µs MIN. TYP. MAX. 31 UNIT µs 27 29 temperature coefficient − −4.10-2 − K influence of delay time on pulse width of horizontal output signal − 0.16 − µs/µs controlled edge − positive − 9.8 10.4 − V Sandcastle output signal (pin 17) V17 output voltage during: burst key horizontal blanking Iload = 1 mA 4.1 4.5 4.9 V vertical blanking Iload = 0.3 mA 2.1 2.5 2.9 V 0.7 − V V17 zero level output voltage Isink = 0.5 mA − tP burst key pulse width 60 Hz 3.4 3.65 4 µs V12 horizontal blanking level − 1 − V 2.3 2.7 3.1 µs − − 9.1 µs vertical blanking td1 phase position burst key time between middle sync pulse at pin 5 and start burst key pulse at pin 17 td2 phase position burst key time between start sync pulse at pin 5 and end of burst key pulse at pin 17 note 9 60 Hz Coincidence detector, video transmitter identification circuit and time constant switching levels (see Fig.1) I18 detector output current − 0.25 − mA V18 voltage level for in sync condition ϕ1 normal 5.8 6.4 7 V V18 voltage level for noisy sync pulse ϕ1 slow and gated 9 10.1 − V V18 voltage level for noise only note 10 − 0.3 − V V18 switching level: <3.2 3.5 3.8 V normal to fast <1.0 1.2 1.4 V field period counter 3 periods fast <0.08 0.12 0.16 V normal to fast mute output inactive locking >1.5 1.75 2 V fast to normal locking >4.7 5 5.3 V normal to slow gated sync pulse >7.4 7.8 8.2 V mute output active and fast to normal Video transmitter identification output (pin 13) V13 output voltage active no sync; I13 = 2 mA − 0.15 0.32 V I13 sink current active no sync; V13 = 1 V − − 5 mA I13 output current inactive sync 60 Hz − − 1 µA note 11 7.2 7.65 8.1 V 60 Hz identification (pin 13) R13 positive supply 15 kΩ V13 pnp emitter follower voltage January 1994 13 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz SYMBOL PARAMETER TDA2579C CONDITIONS MIN. TYP. MAX. UNIT Flyback input pulse (pin 12) V12 switching voltage level − 0.9 − V I12 input current 0.2 − 3 mA V12(p-p) input pulse (peak-to-peak value) − − 12 V R12 input resistance − 3.5 − kΩ td phase position without shift; time between the middle of the sync pulse at pin 5 and the middle of the horizontal blanking pulse at pin 17 2.1 2.5 2.9 µs Vertical ramp generator (pin 3) tc charge current pulse width − 26tclk − I3 charge current − 3 − mA V3 top level ramp signal voltage divider in 60 Hz mode note 12 4.55 4.85 5.25 V V3(p-p) ramp amplitude (peak-to-peak value); R4 = 330 kΩ; fV = 60 Hz C3 = 150 nF; note 12 − 2.5 − V output voltage I4 = 20 µA 7 7.5 7.9 V I4 allowed current range Tamb = 25 to 70 °C 10 − 75 µA TC temperature coefficient output voltage I4 = 40 µA − 50 − 10-6/K Current source (pin 4) V4 Current source (pin 3) I3/4 current ratio pin 3/pin 4 I4 = 35 µA; V3 = 2 V − 1.05 − TC temperature coefficient I3 I4 = 40 µA; R4 fixed − 100 − 10-6/K Comparator (pin 2) V2 input voltage DC level R4 = 330 kΩ; C3 = 150 nF 0.98 1.075 1.17 V V2(p-p) input voltage AC level (peak-to-peak value) R4 = 330 kΩ; C3 = 150 nF − 0.8 − V I2 input current V2 = 0 V − − 1 µA I1 = +1.5 mA; note 12 5 5.5 6.3 V Vertical output stage (pin 1) npn emitter follower V1 maximum output voltage RS sync separator resistor − 170 − Ω Isink continuous sink current − 0.25 − mA Vertical guard circuit (pin 2) V2H active switching level HIGH V17 = 2.5 V; note 12 >1.7 1.85 2.0 V V2L active switching level LOW V17 = 2.5 V; note 12 <0.25 0.35 0.45 V January 1994 14 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz SYMBOL PARAMETER TDA2579C CONDITIONS MIN. TYP. MAX. UNIT Internal vertical sync pulse separator td1 delay between video signal at pin 5 and internally separated vertical sync pulse; normal signal condition td2 delay between video signal at pin 5 and internally separated vertical sync pulse; noisy signal condition V18 ≥ 1.2 V 12 19 25 µs − − −17 µs Notes to the characteristics 1. Value inclusive RL pin 11 to pin 16 = 6.8 kΩ. 2. Up to 1 V peak-to-peak the slicing level is constant, at amplitudes exceeding 1 V peak-to-peak the slicing level will increase. 3. The slicing level is fixed by the formula: Rs p = --------------------- × 100%. 5.3 × R s Where RS is the resistor between pins 6 and in kΩ; top sync = 100%. Video voltage (black-to-white signal) 4. S/N = 20 log -----------------------------------------------------------------------------------------------Noise (RMS) A low-pass filter of 1 kΩ and 150 pF decreases the noise content of the CVBS signal by 6 dB. 5. Undercompensated. 6. Overcompensated. 7. Measured between pin 5 and sandcastle output pin 17. 8. Measured with 3.3 µF feedback capacitor between pin 16 and 6.8 µF capacitor in PLL filter pin 8. 9. Maximum divider ratio (60 Hz): 2×f n = -------------H- = 576 (2 clock pulses per video line). fV Start vertical blanking: − search (large) window mode (60 Hz) − reset divider = start vertical sync pulse plus 1 clock pulse − small/standard window mode (60 Hz) − clock pulse 517. Stop vertical blanking: − all window modes (60 Hz) − clock pulse 34. 10. Depends on DC level of pin 5, value given is valid for V5 ≈ 5 V. 2 × fH 11. Valid for -------------- < 576. fV 12. Value related to internal Zener diode reference voltage. Spread includes complete spread of reference voltage. January 1994 15 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz 0 start 10 vertical sawtooth charge pulse blocking pulse phase detector 1 vertical blanking TDA2579C search mode end of blocking pulse (60 Hz) 26 end of vertical sawtooth charge pulse 34 end of vertical blanking (60 Hz) 130 noise detector window 160 488 517 search 60 Hz window identification start blocking pulse phase detector 1 (60 Hz) vertical blanking (60 Hz) 525 normal reset 528 reset divider when mute is active; no vertical sync found 576 MGA793 One video line equals two counter pulses. Reset counter 32 µs after start of vertical sync pulse at pin 5. Reset counter = counter state 0. Fig.4 Counter system. January 1994 normal and narrow window 16 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz video input signal V 5-9 TDA2579C 4.7 µ s separated horizontal sync pulse ϕ 1 detector reference ϕ 1 detector output I 8 ϕ 1 reference level ϕ 2 reference level 0.3 µs horizontal oscillator sawtooth horizontal flyback pulse 3.75 µs 3.75 µs internal gating pulse 7.5 µ s coincidence detector output I 18 ϕ 2 detector reference 2.5 µs external horizontal flyback pulse V 12-9 switching level 0V storage time horizontal deflection stage 1/2 t FB 1/2 t FB t FB ϕ 2 detector output I14 horizontal output signal V 11-9 29 µs sandcastle output signal V 17-9 0.2 µs 10.4 V 4.5 V 6 µs tP 2.5 V 0.7 V 12 µs divider in search window mode 60 Hz: 34 clock pulses other divider modes 60 Hz: 42 clock pulses Two counter pulses equals one video line. Fig.5 Timing diagram. January 1994 17 MGA794 January 1994 18 150 pF 1 kΩ 5 3.5 kΩ noise detector 2 kΩ VIDEO INPUT 9 kΩ B 7 B 6 kΩ 10 k Ω 1 kΩ 10.5 kΩ 11 kΩ 4.3 kΩ SYNC SEPARATOR C 360 Ω 5.6 k Ω 22 µF 22 Ω 6.2 kΩ A 200 Ω 1.5 k Ω 3 150 nF 1.3 kΩ 4 150 kΩ 1.5 k Ω I A I 8.4 kΩ 4.7 kΩ 880 Ω C 560 Ω 2 kΩ 43 k Ω 4.7 µF 2.15 kΩ 2.4 kΩ 3.6 kΩ 2 6.8 µF 18 kΩ D K 0V K F 6.2 kΩ 1 150 Ω 160 Ω 4.3 kΩ 2 kΩ start up E 250 µA 250 µA 18 5.1 k Ω 100 nF 1 kΩ Iϕ 2 14 II I 100 nF 12 kΩ 1.2 kΩ H G pin 16 pin 10 F HORIZONTAL FLYBACK 2.2 k Ω 3.9 k Ω 2.2 k Ω 12 3.0 mA 0.2 mA 13 12 V 15 k Ω 12 k Ω 6 kΩ 60 Hz identification TRANSMITTER IDENTIFICATION ϕ2 DETECTOR COINCIDENCE DETECTOR TDA2579C D E Fig.6 Internal circuitry 4.3 kΩ stabilizer 33 k Ω 4.7 k Ω HORIZONTAL OSCILLATOR 220 Ω 15 2.7 nF VERTICAL DRIVER 2.4 kΩ Vref 2.8 V 36 k Ω 2 V reference 1.2 k Ω ϕ 1 DETECTOR 880 Ω C 560 Ω 8 VERTICAL COMPARATOR 880 Ω C 560 Ω Vstabilizer 4 kΩ 9.5 kΩ 68 nF G 0.8 mA 17 2.7 kΩ 160 Ω 11 kΩ 1.8 k Ω 1 kΩ MGA796 9 16 10 pin 16 1.4 mA SANDCASTLE SUPPLY stabilizer 1.4 mA 5.6 kΩ 11 HORIZONTAL OUTPUT start up 11 kΩ ϕ detector 2 H G pin 10 pin 16 6.8 k Ω 12 V Synchronization circuit with synchronized vertical divider system for 60 Hz 220 k Ω 7.7 kΩ V stab VERTICAL SAWTOOTH GENERATOR 2 kΩ A A 5.6 kΩ 6 2.2 µF Philips Semiconductors Preliminary specification TDA2579C Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C VERTICAL DEFLECTION CIRCUIT TDA3654 9 8 7 6 5 4 3 2 1 100 µF BAX12 220 µF 4.7 Ω (1) 10 nF 1 nF 560 Ω (1) 26 V 470 pF DEFLECTION COIL 270 Ω 1000 µF video input 2.2 µF 6.8 22 µF µF 68 nF 1.2 k Ω 9 8 7 43 k Ω 1 kΩ 4.7 µF 220 kΩ 1 k Ω 150 kΩ 6 4.3 k Ω 3.6 k Ω 150 pF 22 Ω 5.6 k Ω 4.3 k Ω 5 0.5 Ω 4.7 nF 1 kΩ 150 nF 4 3 2 1 15 16 17 18 TDA2579C 10 11 12 13 14 6.8 k Ω horizontal drive sandcastle 12 k Ω 0.2 to 3.0 mA 39 k Ω 100 µF 100 nF 47 kΩ 12 V transmission identification 60 Hz identification horizontal shift 100 33 kΩ kΩ 4.7 kΩ fo adj. horizontal flyback 2.7 nF 10 nF 22 µF 100 nF 6.2 mA to 9.7 mA start voltage MGA795 (1) Dependent on printed-circuit board layout. Fig.7 TDA2579C and TDA3654 combination 110° Flat Square picture tube. January 1994 19 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C PACKAGE OUTLINE seating plane 22.00 21.35 8.25 7.80 3.7 max 4.7 max 3.9 3.4 0.51 min 0.85 max 2.54 (8x) 0.53 max 0.254 M 0.32 max 7.62 1.4 max 9.5 8.3 MSA259 18 10 6.48 6.14 1 9 Dimensions in mm. Fig.8 18-lead dual in-line; plastic (SOT102). SOLDERING REPAIRING SOLDERED JOINTS Plastic dual in-line packages Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s. BY DIP OR WAVE The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. January 1994 20 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz TDA2579C DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1994 21 Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz NOTES January 1994 22 TDA2579C Philips Semiconductors Preliminary specification Synchronization circuit with synchronized vertical divider system for 60 Hz NOTES January 1994 23 TDA2579C Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)829-1166, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. 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(0)4806 960 India: PEICO ELECTRONICS & ELECTRICALS Ltd., Components Dept., Shivsagar Estate, Block 'A', Dr. Annie Besant Rd., Worli, BOMBAY 400 018, Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.1, Fax. (02)6752.3350 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, KOKIO 108, Tel. (03)3740 5101, Fax. (03)3740 0570 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)757 5511, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Tel. (040)78 37 49, Fax. (040)78 83 99 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (22)74 8000, Fax. (22)74 8341 Philips Semiconductors Pakistan: Philips Markaz, M.A. Jinnah Rd., KARACHI 3, Tel. (021)577 039, Fax. (021)569 1832 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 911, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: Av. Eng. Duarte Pacheco 6, 1009 LISBOA Codex, Tel. (01)683 121, Fax. (01)658 013 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: 195-215 Main Road, Martindale, P.O. Box 7430,JOHANNESBURG 2000, Tel. (011)470-5433, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. (01)488 2211, Fax. (01)481 7730 Taiwan: 69, Min Sheng East Road, Sec 3, P.O. Box 22978, TAIPEI 10446, Tel. (2)509 7666, Fax. (2)500 5899 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna - Trad Road Km. 3 Prakanong, BANGKOK 10260, Tel. (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080 Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL, Tel. (0212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD27 © Philips Electronics N.V. 1993 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 9397 725 20011