TI THS3202DGN

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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
FEATURES
DESCRIPTION
D Unity Gain Bandwidth: 2 GHz
The THS3202 is part of the high performing current
feedback amplifier family developed in BiCOM−ΙΙ
technology. Designed for low-distortion with a high slew
rate of 9000 V/µs, the THS320x family is ideally suited for
applications driving loads sensitive to distortion at high
frequencies.
D High Slew Rate: 9000 V/µs
D IMD3 at 120 MHz: −89 dBc (G = 5, RL = 100 Ω,
VCC = 15 V)
D OIP3 at 120 MHz: 44 dBm (G = 5, RL = 100 Ω,
The THS3202 provides well-regulated ac performance
characteristics with power supplies ranging from
single-supply 6.6-V operation up to a 15-V supply. The
high unity gain bandwidth of up to 2 GHz is a major
contributor to the excellent distortion performance. The
THS3202 offers an output current drive of ±115 mA and a
low differential gain and phase error that make it suitable
for applications such as video line drivers.
VCC = 15 V)
D High Output Current: ±115 mA into 20 Ω RL
D Power Supply Voltage Range: 6.6 V to 15 V
APPLICATIONS
The THS3202 is available in an 8 pin SOIC and an 8 pin
MSOP with PowerPAD packages.
D High-Speed Signal Processing
D Test and Measurement Systems
RELATED DEVICES AND DESCRIPTIONS
D High-Voltage ADC Preamplifier
THS3001
±15-V 420-MHz Low Distortion CFB Amplifier
D RF and IF Amplifier Stages
THS3061/2
±15-V 300-MHz Low Distortion CFB Amplifier
THS3122
±15-V Dual CFB Amplifier With 350 mA Drive
THS4271
+15-V 1.4-GHz Low Distortion VFB Amplifier
D Professional Video
THS3202
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OIP3
vs
FREQUENCY
−50
Test Instrument Measurement Limit
48
−60
46
G=5
RL = 500 Ω
VCC = 15 V
Rf = 420 Ω
f = 10 MHz
−70
−80
2nd Harmonic
−90
40
28
2
4
6
8
10
12
VO − Output Voltage − Vpp
G=5
+
36
30
−120
Spectrum Analyzer
_
VCC = ±6 V
38
32
3rd Harmonic
−110
Output Power
VCC = ±7 V
42
34
−100
0
VCC = ±7.5 V
44
OIP 3 − dBc
HD − Hormonic Distortion − dB
TEST CIRCUIT FOR
IMD3 / OIP3
50
50 Ω
50 Ω
RL = 100 Ω,
G = 5,
RF = 536 Ω,
VO = 2VPP_Envelope
∆f = 200 kHz
VCC = ±5 V
26
10
60
110
160
210
260
fc − Frequency − MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
!"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%&
'!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2.
"!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&.
Copyright  2002 − 2004, Texas Instruments Incorporated
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
16.5 V
Supply voltage, VS
±3 V
Differential Input voltage, VID
Output current, IO
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
±VS
Input voltage, VI
(2)
175 mA
Continuous power dissipation
See Dissipation Rating Table
PACKAGE DISSIPATION RATINGS
Maximum junction temperature, TJ (3)
150°C
Maximum junction temperature, continuous
operation, long term reliability TJ (4)
125°C
PACKAGE
θJC
(°C/W)
θJA(1)
(°C/W)
Operating free-air temperature range, TA
−40°C to 85°C
D (8 pin)
38.3
97.5
Storage temperature range, Tstg
−65°C to 150°C
DGN (8 pin)
4.7
DGK (8 pin)
54.2
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings:
3000 V
CDM
1500 V
MM
200 V
TA ≤ 25°C
1.32 W
TA = 85°C
410 mW
58.4
1.71 W
685 mW
260
385 mW
154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
300°C
HBM
POWER RATING(2)
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The THS3202 may incorporate a PowerPAD on the underside
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
(3) The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
Supply voltage,
(VS+ and VS−)
MIN
MAX
Dual supply
±3.3
±7.5
Single supply
6.6
15
−40
85
Operating free-air temperature
range
NUMBER OF
CHANNELS
2
PLASTIC SOIC-8(1)
(D)
THS3202D
PLASTIC MSOP-8(1)
(DGN)
SYM
(DGK)
THS3202DGN
BEP
THS3202DGK
SYM
BEV
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS3202DR).
PIN ASSIGNMENTS
TOP VIEW
1VOUT
1VIN −
1VIN +
VS−
2
D, DGN, DGK
1
8
2
7
3
6
4
5
VS+
2VOUT
2VIN −
2VIN+
V
°C
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
PLASTIC MSOP-8(1)
PowerPAD
UNIT
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±5 V: Rf = 500 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3202
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
UNITS
MIN/TYP/
MAX
MHz
Typ
380
MHz
Typ
875
MHz
Typ
V/µs
Typ
ns
Typ
ns
Typ
dBc
Typ
dBc
Typ
25°C
25°C
0°C to
70°C
−40°C
to 85°C
AC PERFORMANCE
Small-signal bandwidth, −3 dB
(VO = 100 mVPP)
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
G = +1, Rf= 500 Ω
1800
G = +2, Rf = 402 Ω
975
G = +5, Rf = 300 Ω
780
G = +10, Rf = 200 Ω
550
G = +2, VO = 100 mVpp,
Rf = 536 Ω
G = +2, VO = 4 Vpp, Rf = 536 Ω
G = −1, 5-V step
5100
G = +2, 5-V step
4400
Rise and fall time
G = +2, VO = 5-V step
0.45
Settling time to 0.1%
G = −2, VO = 2-V step
19
G = −2, VO = 2-V step
118
Slew rate (25% to 75% level)
0.01%
Harmonic distortion
G = +2, f = 16 MHz, VO = 2 Vpp
2nd harmonic
RL = 100 Ω
RL = 500 Ω
−64
3rd harmonic
RL = 100 Ω
RL = 500 Ω
−67
−67
−69
−64
dBc
Typ
Input voltage noise
G = +5, fc = 120 MHz,
∆f = 200 kHz,
VO(envelope) = 2 Vpp
f > 10 MHz
1.65
nV/√Hz
Typ
Input current noise (noninverting)
f > 10 MHz
13.4
pA/√Hz
Typ
Input current noise (inverting)
f > 10 MHz
20
pA/√Hz
Typ
Crosstalk
G = +2, f = 100 MHz
−60
dB
Typ
Differential gain (NTSC, PAL)
G = +2, RL = 150 Ω
0.008%
Typ
Differential phase (NTSC, PAL)
G = +2, RL = 150 Ω
0.03°
Typ
VO = ±1 V, RL = 1 kΩ
VCM = 0 V
300
200
140
120
kΩ
Min
±0.7
±3
±3.8
±4
mV
Max
VCM = 0 V
VCM = 0 V
±10
±13
µV/°C
Typ
±13
±60
±80
±85
µA
Max
VCM = 0 V
VCM = 0 V
±300
±400
nA/°C
Typ
Input bias current (noninverting)
±14
±35
±45
±50
µA
Max
Average bias current drift (+)
VCM = 0 V
±300
±400
nA/°C
Typ
3rd order intermodulation distortion
DC PERFORMANCE
Open-loop transimpedance gain
Input offset voltage
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (−)
3
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±5 V: Rf = 500 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3202
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
±2.6
±2.5
±2.5
71
60
58
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
±2.5
V
Min
58
dB
Min
kΩ
Typ
INPUT
Common-mode input range
Common-mode rejection ratio
Input resistance
Input capacitance
VCM = ±2.5 V
Noninverting
780
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
RL = 1 kΩ
RL = 100 Ω
±3.65
±3.5
±3.45
±3.4
±3.45
±3.3
±3.25
±3.2
V
Min
OUTPUT
Voltage output swing
RL = 20 Ω
RL = 20 Ω
115
105
100
100
mA
Min
Current output, sinking
100
85
80
80
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Current output, sourcing
POWER SUPPLY
Minimum operating voltage
Absolute minimum
Maximum quiescent current
Per amplifier
Power supply rejection (+PSRR)
VS+ = 4.5 V to 5.5 V
VS− = −4.5 V to –5.5 V
Power supply rejection (−PSRR)
4
±3
±3
±3
V
Min
14
16.8
19
20
mA
Max
69
63
60
60
dB
Min
65
58
55
55
dB
Min
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
VS = 15 V: Rf = 500 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3202
PARAMETER
TEST CONDITIONS
TYP
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
MHz
Typ
AC PERFORMANCE
G = +1, Rf= 550 Ω
2000
G = +2, Rf = 550 Ω
1100
G = +5, Rf = 300 Ω
850
G = +10, Rf = 200 Ω
750
Bandwidth for 0.1 dB flatness
G = +2, VO = 100 mVpp,
Rf= 536 Ω
500
MHz
Typ
Large-signal bandwidth
G = +2, VO = 4 Vpp, Rf= 536 Ω
1000
MHz
Typ
G = +5, 5-V step
7500
G = +2, 10-V step
9000
V/µs
Typ
G = +2, VO = 10-V step
G = −2, VO = 2-V step
0.45
ns
Typ
23
ns
Typ
G = −2, VO = 2-V step
112
ns
Typ
G = +2, f = 16 MHz, VO = 2 Vpp
RL = 100 Ω
−69
dBc
Typ
dBc
Typ
Small-signal bandwidth, −3dB
(VO = 100 mVPP)
Slew rate (25% to 75% level)
Rise and fall time
Settling time to 0.1%
0.01%
Harmonic distortion
2nd harmonic
RL = 500 Ω
RL = 100 Ω
−73
−90
−89
dBc
Typ
Input voltage noise
RL = 500 kΩ
G = +5, fc = 120 MHz,
∆f = 200 kHz,
VO(envelope) = 2 Vpp
f > 10 MHz
1.65
nV/√Hz
Typ
Input current noise (noninverting)
f > 10 MHz
13.4
pA/√Hz
Typ
Input current noise (inverting)
f > 10 MHz
20
pA/√Hz
Typ
Crosstalk
G = +2, f = 100 MHz
−60
dB
Typ
Differential gain (NTSC, PAL)
G = +2, RL = 150 Ω
0.004%
Typ
Differential phase (NTSC, PAL)
G = +2, RL = 150 Ω
0.006°
Typ
3rd harmonic
3rd order intermodulation distortion
−80
DC PERFORMANCE
Open-loop transimpedance gain
Input offset voltage
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (−)
VO = 6.5 V to 8.5 V, RL = 1 kΩ
VCM = 7.5 V
VCM = 7.5 V
VCM = 7.5 V
Input bias current (noninverting)
VCM = 7.5 V
VCM = 7.5 V
Average bias current drift (+)
VCM = 7.5 V
300
200
140
±1.3
±4
±4.8
±10
±80
±300
±16
±14
±60
±35
120
kΩ
Min
±5
mV
Max
±13
µV/°C
Typ
±85
µA
Max
±400
nA/°C
Typ
±45
±50
µA
Max
±300
±400
nA/°C
Typ
5
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS continued
VS = 15 V: Rf = 500 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
THS3202
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
−40°C
to 85°C
UNITS
MIN/TYP/
MAX
2.4 to
12.6
2.5 to
12.5
2.5 to
12.5
2.5 to
12.5
V
Min
69
60
58
58
INPUT
Common-mode input range
Common-mode rejection ratio
Input resistance
Input capacitance
VCM = 5 V to 10 V
Noninverting
dB
Min
780
kΩ
Typ
Inverting
11
Ω
Typ
Noninverting
1
pF
Typ
V
Min
OUTPUT
RL = 1 kΩ
1.5 to
13.5
1.6 to
13.4
1.7 to
13.3
1.7 to
13.3
RL = 100 Ω
1.7 to
13.3
1.8 to
13.2
2.0 to
13.0
2.0 to
13.0
120
105
100
100
mA
Min
Current output, sinking
RL = 20 Ω
RL = 20 Ω
115
95
90
90
mA
Min
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
Ω
Typ
Voltage output swing
Current output, sourcing
POWER SUPPLY
Maximum quiescent current/channel
Per amplifier
15
18
21
21
mA
Max
Power supply rejection (+PSRR)
VS+ = 14.50 V to 15.50 V
VS− = −0.5 V to +0.5 V
69
63
60
60
dB
Min
65
58
55
55
dB
Min
Power supply rejection (−PSRR)
6
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Small signal frequency response
1−14
Large signal frequency response
15−18
Harmonic distortion
vs Frequency
19−30
Harmonic distortion
vs Output voltage
31−45
IMD3
OIP3
vs Frequency
46, 47
vs Frequency
48, 49
S parameter
vs Frequency
51−54
Input current noise density
vs Frequency
55
Voltage noise density
vs Frequency
56
Transimpedance
vs Frequency
57
Output impedance
vs Frequency
58
Test circuit for IMD3 / OIP3
50
Impedance of inverting input
59
Supply current/channel
vs Supply voltage
60
Input offset voltage
vs Free-air temperature
61
Offset voltage
vs Common-mode input voltage range
62
vs Free-air temperature
63
vs Input common-mode range
64
Positive power supply rejection ratio
vs Positive power supply
65
Negative power supply rejection ratio
vs Negative power supply
Positive output voltage swing
vs Free-air temperature
67, 68
Negative output voltage swing
vs Free-air temperature
69, 70
Output current sinking
vs Power supply
Output current sourcing
vs Power supply
Input bias current
Overdrive recovery time
Slew rate
66
71
72
73, 74
vs Output voltage
Output voltage transient response
75, 76, 77
78
Settling time
79, 80
DC common-mode rejection ratio high
vs Input common-mode range
Power supply rejection ratio
vs Frequency
81
Differential gain error
vs 150 Ω loads
84, 85, 88
Differential phase error
vs 150 Ω loads
86, 87, 89
82, 83
7
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
44
Small Signal Gain − dB
11
00
Rf = 619 Ω
−2
−2
G=1
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
−4
−4
−5
−5
0.1 M
1M
0
100 M
1G
Rf = 619 Ω
−1
−2
−3
−4
10 M
4
1
G=1
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
−5
0.1 M
10G
1M
f − Frequency − Hz
8
Rf = 402 Ω
7
Small Signal Gain − dB
Small Signal Gain − dB
9
8
6
Rf = 536 Ω
4
1
0
0.1 M
Rf = 650 Ω
G=2
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
1M
10 M
1G
5
10
4
Rf = 650 Ω
3
2
G=2
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
100 M
1G
Rf = 649 Ω
G=2
RL = 500 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
f − Frequency − Hz
Figure 7
8
Rf = 536 Ω
7
6
5
4
Rf = 649 Ω
3
1M
1G
10 G
100 M
1G
10 G
Figure 6
SMALL SIGNAL FREQUENCY RESPONSE
16
12
Rf = 500 Ω
G=5
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
1M
10 M
14
13
f − Frequency − Hz
Figure 8
1G
10 G
Rf = 402 Ω
12
Rf = 500 Ω
11
10
9
100 M
Rf = 300 Ω
15
Rf = 402 Ω
13
10
0.1 M
10 M
f − Frequency − Hz
14
11
100 M
9
G=2
RL = 500 Ω
VCC = 15 V
VO = 100 mVPP
0
0.1 M
10 G
15
3
10 G
1
Rf = 300 Ω
5
1G
2
SMALL SIGNAL FREQUENCY RESPONSE
Small Signal Gain − dB
Small Signal Gain − dB
11
Rf = 536 Ω
8
6
100 M
Figure 3
Figure 5
Rf = 536 Ω
10 M
f − Frequency − Hz
16
4
1M
f − Frequency − Hz
9
0
0.1 M
−4
0.1 M
10 G
6
0
0.1 M
10 G
SMALL SIGNAL FREQUENCY RESPONSE
1
1G
7
Figure 4
2
100 M
Rf = 402 Ω
f − Frequency − Hz
7
Rf = 750 Ω
−3
12
1
100 M
0
−1
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
9
2
Rf = 619 Ω
1
Figure 2
SMALL SIGNAL FREQUENCY RESPONSE
3
2
f − Frequency − Hz
Figure 1
5
10 M
3
G=1
RL = 500 Ω
VCC = ±5 V
VO = 100 mVPP
−2
Small Signal Gain − dB
−3
−3
5
Small Signal Gain − dB
Small Signal Gain − dB
22
−1
−1
6
Rf = 500 Ω
2
Small Signal Gain − dB
Rf = 500 Ω
33
8
SMALL SIGNAL FREQUENCY RESPONSE
3
8
0.1 M
G=5
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
100 M
f − Frequency − Hz
Figure 9
1G
10 G
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
14
14
11
11
10
10
0.1 M
Rf = 420 Ω
Rf = 500 Ω
G=5
RL = 500 Ω
VCC = 15 V
VO = 100 mVPP
1M
10 M
14
13
Rf = 420 Ω
12
Rf = 500 Ω
11
10
9
100 M
1G
8
0.1 M
10 G
G=5
RL = 500 Ω
VCC = ±5 V
VO = 100 mVPP
1M
Figure 10
10 M
100 M
1G
Rf = 450 Ω
Rf = 550 Ω
G = −1
RL = 100 Ω
VCC = ±5 V
VO = 100 mVPP
1M
10 M
100 M
−1
−3
−5
0.1 M
10 G
VCC = ±5 V
−2
−4
1G
VCC = 15 V
0
G=1
RL = 500 Ω
Rf = 450 Ω
VO = 100 mVPP
1M
10 M
100 M
1G
14
10
12
10
6
4
VO = 1 VPP
0
−2
VO = 0.5 VPP
−8
VCC = 15 V, G = 1, RL = 100 Ω
−10
−12
100 K 1 M
10 M
100 M
1G
f − Frequency − Hz
Figure 16
VO = 1 VPP
2
0
−2
VO = 0.5 VPP
−4
−6
−8
−10
−12
100 K
1M
10 G
10 M
100 M
f − Frequency − Hz
1G
10 G
LARGE SIGNAL FREQUENCY RESPONSE
VO = 4 VPP
VO = 2 VPP
0
VO = 1 VPP
−4
−6
−8
VO = 2 VPP
14
12
2
−2
10 G
Figure 15
8
6
4
1G
4
Normalized Amplitude − dB
Normalized Amplitude − dB
Normalized Amplitude − dB
VO = 2 VPP
100 M
6
10 G
LARGE SIGNAL FREQUENCY RESPONSE LARGE SIGNAL FREQUENCY RESPONSE
−6
8
G = 1,
VCC = ±5 V
RL = 100 Ω
Figure 14
12
10 M
LARGE SIGNAL FREQUENCY RESPONSE
f − Frequency − Hz
Figure 13
−4
1M
Figure 12
1
f − Frequency − Hz
2
Rf = 550 Ω
G = −1
RL = 100 Ω
VCC = 15 V
VO = 100 mVPP
f − Frequency − Hz
Normalized Amplitude − dB
Small Signal Gain − dB
Small Signal Gain − dB
−1
8
−4
12
2
0
−6
0.1 M
−3
10
Rf = 340 Ω
−2
Rf = 450 Ω
−2
−6
0.1 M
10 G
3
1
−5
−1
Figure 11
3
−4
0
−5
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
−3
1
f − Frequency − Hz
f − Frequency − Hz
2
Rf = 340 Ω
2
Small Signal Gain − dB
Small Signal Gain − dB
Small Signal Gain − dB
15
15
13
13
3
Rf = 340 Ω
15
Rf = 340 Ω
16
16
12
12
SMALL SIGNAL FREQUENCY RESPONSE
16
17
17
VO = 0.5 VPP
−10
VCC = 15 V, G = 2, RL = 100 Ω
−12
100 K
1M
10 M 100 M
1G
f − Frequency − Hz
Figure 17
VO = 2 VPP
VO = 1 VPP
VO = 0.25 VPP
−8
−10
−12
−14
10 G
VO = 4 VPP
10
8
6
4
2
0
−2
−4
−6
G = 2, VCC = ±5, RL = 100 Ω
100 K
1M
10 M
100 M
1G
10 G
f − Frequency − Hz
Figure 18
9
www.ti.com
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
HARMONIC DISTORTION
vs
FREQUENCY
2nd Harmonic
−80
−80
−90
−90
3rd Harmonic
1M
10 M
100 M
G = −1
RL = 500 Ω
VCC = 15 V
Rf = 450 Ω
VO = 2VPP
−70
−70
−90
−90
−100
−100
0.1 M
−60
−60
−70
−70
−90
−90
3rd
Harmonic
3rd Harmonic
1M
10 M
100 M
−100
−100
0.1 M
−90
−90
−60
G=5
RL = 100 Ω
VCC = 15 V
Rf = 500 Ω
VO = 2VPP
−60
−70
−80
2nd Harmonic
−90
3rd Harmonic
1M
10 M
3rd Harmonic
−100
0.1 M
100 M
f − Frequency − Hz
−90
3rd Harmonic
−100
0.1 M
100 M
2nd Harmonic
3rd Harmonic
−90
−70
−50
−55
2nd Harmonic
−80
100 M
HARMONIC DISTORTION
vs
FREQUENCY
G = −1
RL = 500 Ω
VCC = ±5 V
Rf = 450 Ω
VO = 2VPP
−60
10 M
Figure 24
−50
G = −1
RL = 100 Ω
VCC = ±5 V
Rf = 450 Ω
VO = 2VPP
1M
f − Frequency − Hz
HD − Hormonic Distortion − dB
−80
2nd Harmonic
HARMONIC DISTORTION
vs
FREQUENCY
HD − Hormonic Distortion − dB
−70
10 M
−80
Figure 23
HARMONIC DISTORTION
vs
FREQUENCY
−60
1M
G=5
RL = 500 Ω
VCC = 15 V
Rf = 420 Ω
VO = 2VPP
−70
f − Frequency − Hz
Figure 22
−50
100 M
HARMONIC DISTORTION
vs
FREQUENCY
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
2nd Harmonic
10 M
Figure 21
−50
G=2
RL = 500 Ω
VCC = 15 V
Rf = 536 Ω
VO = 2VPP
−100
−100
0.1 M
1M
f − Frequency − Hz
HARMONIC DISTORTION
vs
FREQUENCY
−60
−60
−80
−80
2nd
Harmonic
−80
−80
Figure 20
HARMONIC DISTORTION
vs
FREQUENCY
−70
−70
G=2
RL = 100 Ω
VCC = 15 V
Rf = 500 Ω
VO = 2VPP
f − Frequency − Hz
Figure 19
HD − Hormonic Distortion − dB
2nd Harmonic
−80
−80
f − Frequency − Hz
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
−70
−70
−100
−100
0.1 M
−50
−50
−60
−60
G = −1
RL = 100 Ω
VCC = 15 V
Rf = 450 Ω
VO = 2VPP
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
−50
−50
−60
−60
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
3rd Harmonic
−90
−60
−65
−70
G=2
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
VO = 2VPP
2nd Harmonic
−75
−80
3rd Harmonic
−85
−90
−95
−100
−100
1M
10 M
f − Frequency − Hz
Figure 25
10
100 M
1M
10 M
f − Frequency − Hz
Figure 26
100 M
−100
0.1 M
1M
10 M
f − Frequency − Hz
Figure 27
100 M
www.ti.com
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−50
−60
2nd Harmonic
−70
−80
3rd Harmonic
−90
−100
0.1 M
1M
10 M
−50
G=5
RL = 100 Ω
VCC = ±5 V
Rf = 420 Ω
VO = 2VPP
−60
−70
2nd Harmonic
−80
3rd Harmonic
−90
−100
0.1 M
100 M
1M
10 M
Figure 28
−60
−70
3rd Harmonic
−80
2nd Harmonic
−90
−100
0.1 M
100 M
−70
−80
3rd Harmonic
−50
G=5
RL = 500 Ω
VCC = ±5 V
Rf = 420 Ω
f = 1 MHz
−75
−80
−85
−90
−95
2nd Harmonic
−100
3rd Harmonic
−105
0
2
4
6
8
10
0
12
1
Figure 31
2
3
4
5
2nd Harmonic
−85
−90
3rd Harmonic
0
1
−80
2nd Harmonic
−90
6
8
10
4
5
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
−60
−70
−80
2nd Harmonic
−90
3rd Harmonic
G=5
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 1 MHz
−80
2nd Harmonic
−90
3rd Harmonic
−100
VO − Output Voltage − VPP
3
Figure 33
G=5
RL = 100 Ω
VCC = 15 V
Rf = 500 Ω
f = 1 MHz
3rd Harmonic
−100
2
VO − Output Voltage − VPP
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
−70
Figure 34
−80
−100
6
−50
G=5
RL = 100 Ω
VCC = 15 V
Rf = 500 Ω
f = 1 MHz
4
−75
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−50
2
−70
Figure 32
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
0
−65
VO − Output Voltage − VPP
VO − Output Voltage − VPP
−60
−60
−95
−110
−100
G=5
RL = 500 Ω
VCC = ±5 V
Rf = 420 Ω
f = 10 MHz
−55
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
2nd
Harmonic
100 M
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
G=5
RL = 500 Ω
VCC = 15 V
Rf = 420 Ω
f = 10 MHz
10 M
Figure 30
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−50
−90
1M
f − Frequency − Hz
Figure 29
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−60
G=5
RL = 500 Ω
VCC = ±5 V
Rf = 500 Ω
VO = 2VPP
f − Frequency − Hz
f − Frequency − MHz
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
G=2
RL = 500 Ω
VCC = ±5 V
Rf = 536 Ω
VO = 2VPP
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
−50
HD − Hormonic Distortion − dB
HARMONIC DISTORTION
vs
FREQUENCY
0
2
4
6
8
VO − Output Voltage − V
Figure 35
10
12
−100
0
1
2
3
4
5
VO − Output Voltage − VPP
Figure 36
11
www.ti.com
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−60
−65
2nd Harmonic
−70
−75
−80
−85
−90
3rd Harmonic
−70
−80
2nd
Harmonic
−90
3rd Harmonic
−95
−100
−100
0
1
2
3
4
5
VO − Output Voltage − VPP
2
4
6
8
10
3rd Harmonic
−90
0
12
2
HD − Hormonic Distortion − dB
2nd
Harmonic
−90
−95
4
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−50
G=2
RL = 500 Ω
VCC = ±5 V
Rf = 536 Ω
f = 10 MHz
−60
2nd
Harmonic
−70
−80
3rd Harmonic
−90
−100
2
3
G=2
RL = 100 Ω
VCC = 15 V
Rf = 500 Ω
f = 1 MHz
−60
−70
−80
2nd Harmonic
−90
4
5
−100
0
VO − Output Voltage − VPP
1
4
5
0
−80
−90
−75
2
4
6
8
VO − Output Voltage − VPP
Figure 43
10
10
−80
G=2
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 10 MHz
−55
−85
2nd Harmonic
−90
−95
3rd Harmonic
−60
−65
−70
−75
−80
2nd Harmonic
−85
−90
3rd Harmonic
−95
−100
−100
0
8
−50
G=2
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 1 MHz
3rd Harmonic
−100
6
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
2nd Harmonic
−70
4
Figure 42
−70
G=2
RL = 100 Ω
VCC = 15 V
Rf = 500 Ω
f = 10 MHz
−60
2
VO − Output Voltage − VPP
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−40
HD − Hormonic Distortion − dB
3
Figure 41
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
12
2
VO − Output Voltage − VPP
Figure 40
−50
10
3rd Harmonic
−100
1
8
Figure 39
3rd Harmonic
0
6
VO − Output Voltage − VPP
−50
G=2
RL = 500 Ω
VCC = ±5 V
Rf = 536 Ω
f = 1 MHz
−85
−80
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
2nd
Harmonic
−70
Figure 38
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−80
−60
VO − Output Voltage − VPP
Figure 37
−75
G=2
RL = 500 Ω
VCC = 15 V
Rf = 536 Ω
f = 10 MHz
−100
0
HD − Hormonic Distortion − dB
HD − Hormonic Distortion − dB
−60
−50
G=2
RL = 500 Ω
VCC = 15 V
Rf = 536 Ω
f = 1 MHz
HD − Hormonic Distortion − dB
G=5
RL = 100 Ω
VCC = ±5 V
Rf = 500 Ω
f = 10 MHz
−55
HD − Hormonic Distortion − dB
−50
HD − Hormonic Distortion − dB
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
0
1
2
3
4
VO − Output Voltage − VPP
Figure 44
5
0
1
2
3
4
VO − Output Voltage − VPP
Figure 45
5
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
THS3202
IMD3
vs
FREQUENCY
OIP3
vs
FREQUENCY
−70
RL = 100 Ω, G = 5,
Rf = 536 Ω,
VO = 2VPP_Envelope
∆f = 200 kHz
−60
−65
50
46
−75
−70
−75
VCC = ±6 V
−80
G=2
−80
G=5
−85
VCC = ±5 V
RL = 100 Ω,
Rf = 536 Ω,
∆f = 200 kHz
VO = 2VPP_Envelope
VCC = ±7 V
−85
−90
VCC = ±7.5 V
−90
Test Instrument Measurement Limit
110
160
210
fc − Frequency − MHz
0
260
20
40
60
42
VCC = ±7 V
40
VCC = ±6 V
38
36
34 RL = 100 Ω,
32 G = 5,
Rf = 536 Ω,
30 V = 2V _Envelope
O
PP
28 ∆f = 200 kHz
VCC = ±5 V
26
10
60
110
160
210
−95
−95
60
VCC = ±7.5 V
44
VCC = ±5 V
10
Test Instrument Measurement Limit
48
IMD 3 − dBc
IMD 3 − dBc
THS3202
IMD3
vs
FREQUENCY
OIP 3 − dBm
−55
THS3202
80
fc − Frequency − MHz
Figure 46
Figure 47
Figure 48
THS3202
OIP3
vs
FREQUENCY
S PARAMETER
vs
FREQUENCY
TEST CIRCUIT FOR
IMD3 / OIP3
20
47
OIP 3 − dBm
G=5
43
Spectrum Analyzer
_
G=5
+
41
50 Ω
G=2
50 Ω
39
37
0
20
40
60
−20
−40
−60
S12
S11
+
_
−120
0.1 M
80
1M
Figure 50
S PARAMETER
vs
FREQUENCY
−40
−60
S12
−80
C
+
_
S22
0
−40
−60
S12
S11
−80
C
+
_
−100
−120
−140
0.1 M
−120
1M
10 M
100 M
f − Frequency − Hz
Figure 52
10 G
20
VCC = 15 V
C = 3 pF
RL = 100 Ω
G = 10
S Parameter − dB
−20
S Parameter − dB
S Parameter − dB
0
S22
−100
1G
S PARAMETER
vs
FREQUENCY
20
S11
100 M
Figure 51
S PARAMETER
vs
FREQUENCY
20
−20
10 M
f − Frequency − Hz
Figure 49
0
C
−80
fc − Frequency − MHz
VCC = 15 V
C = 0 pF
RL = 100 Ω
G = 10
S22
−100
This circuit applies to figures 46
through 49
35
VCC = ±5 V
C = 0 pF
RL = 100 Ω
G = 10
0
Output Power
S Parameter − dB
45
VCC = ±5 V
RL = 100 Ω,
Rf = 536 Ω,
∆f = 200 kHz
VO = 2VPP_Envelope
260
fc − Frequency − MHz
1G
10 G
−140
0.1 M
−20
VCC = ±5 V
C = 3 pF
RL = 100 Ω
G = 10
S22
−40
−60
S12
S11
C
−80
+
_
−100
1M
10 M
100 M
f − Frequency − Hz
Figure 53
1G
10 G
−120
0.1 M
1M
10 M
100 M
f − Frequency − Hz
1G
10 G
Figure 54
13
www.ti.com
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
INPUT CURRENT NOISE DENSITY
vs
FREQUENCY
4.5
40
35
30
Inverting
Noise Current
25
20
Noninverting
Current Noise
15
10
100 K
1M
10 M
f − Frequency − Hz
4
3.5
3
2.5
2
1.5
100 K
100 M
1M
10 M
f − Frequency − Hz
Figure 55
13
12
10
10 M
100 M
1G
f − Frequency − Hz
Figure 58
Figure 59
−1.0
−1.5
−2.0
−2.5
VCC = 15 V
−3.5
VOS − Offset Voltage − mV
VCC = ±5 V
TA − Free-Air Temperature − °C
Figure 61
1G
TA = 85°C
19
17
TA = 25°C
15
13
11
TA = −40°C
9
7
10 G
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
±VCC − Supply Voltage − V
Figure 60
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
6
50
4
45
2
TA = −40°C
0
TA = 25°C
−2
−4
−6
−8
−4.0
−45−35−25−15 −5 5 15 25 35 45 55 65 75 85
100 M
21
OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE RANGE
−0.5
−3.0
1M
f − Frequency − Hz
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
10 M
O
I IB
5
100 k
1G
IIB − Input Bias Current − µA
100 M
1M
V
SUPPLY CURRENT/CHANNEL
vs
SUPPLY VOLTAGE
ICC − Supply Current /Channel− mA
ZO − Impedance − Ω
ZO− Output Impedance −Ω
14
11
VCC = 15 V
Gain W +
+
_
23
0.1
10 M
20
_
+
Figure 57
15
VCC = ±5 V
10 Ω
f − Frequency − Hz
VCC = +5 V
1
1M
40
IMPEDANCE OF INVERTING INPUT
10
0.1 M
60
0
0.1 M
100 M
16
G=2
RL = 100 Ω
0.01
80
THS3202
100
VCC = 15 V,
VCC = ±5 V
100
Figure 56
OUTPUT IMPEDANCE
vs
FREQUENCY
VIO − Input Offset Voltage − mV
120
VCC = ±5 V and 15 V
TA = 25°C
Transimpedance Gain −dBΩ
45
Hz
VCC = ±5 V and 15 V
TA = 25°C
Voltage Noise Density − nV/
Input Current Noise Density − pA Hz
50
14
TRANSIMPEDANCE
vs
FREQUENCY
VOLTAGE NOISE DENSITY
vs
FREQUENCY
−10
TA = 85°C
35
VCC = 15 V
30
25
20
RL = 100 Ω
VCC = ±7.5 V
−5 −4 −3 −2 −1
40
0
1
2
3
4
5
VICR − Common-Mode Input Voltage Range − V
Figure 62
VCC = ±5 V
15
−40−30−20−10 0 10 20 30 40 50 60 70 80
TA − Free-Air Temperature − °C
Figure 63
www.ti.com
TA = −40°C to 85°C
VCC = ±5 V
−20
−30
−2
−1
0
1
2
Input Common Mode Range − V
3
TA = −40°C
70
TA = 25°C
65
TA = 85°C
60
55
50
RL = 100 Ω
45
3
3.5
4 4.5 5 5.5
6 6.5
Positive Power Supply − V
Figure 64
VO − Positive Output Voltage Swing − V
VO − Positive Output Voltage Swing − V
13.6
RL = 1 kΩ
13.5
13.4
13.3
RL = 100 Ω
13.2
−10
10
30
50
70
3.65
RL = 1 kΩ
3.60
3.55
3.50
3.45
RL = 100 Ω
3.40
3.35
3.30
−45
90
−25
−5
I O − Output Current Sinking − mA
VO − Negative Output Voltage Swing − V
15
35
55
75
−3.50
RL = 100 Ω
−3.60
−3.65
−3.70
RL = 1 kΩ
50
70
TA − Free-Air Temperature − °C
Figure 70
RL = 100 Ω
45
3
3.5
4 4.5 5 5.5 6 6.5
Negative Power Supply − V
120
TA = 85°C
100
TA = 25°C
90
90
7.5
VCC = 15 V
1.7
RL = 100 Ω
1.6
1.5
1.4
RL = 1 kΩ
1.3
−30
−10
10
30
50
70
90
TA − Free-Air Temperature − °C
OUTPUT CURRENT SOURCING
vs
POWER SUPPLY
160
RL = 10 Ω
110
7
Figure 69
TA = −40°C
80
RL = 10 Ω
140
TA = −40°C
120
TA = 25°C
100
TA = 85°C
80
60
40
70
30
50
1.2
−50
95
130
VCC = ±5 V
10
55
OUTPUT CURRENT SINKING
vs
POWER SUPPLY
−3.45
−10
TA = 85°C
Figure 68
NEGATIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
−30
TA = 25°C
60
TA − Free-Air Temperature − °C
Figure 67
−3.75
65
1.8
VCC = ±5 V
3.70
TA − Free-Air Temperature − °C
−3.55
TA = −40°C
NEGATIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
3.75
VCC = 15 V
−30
70
Figure 66
POSITIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
13.7
−3.80
−50
7.5
NEGATIVE POWER SUPPLY
REJECTION RATIO
vs
NEGATIVE POWER SUPPLY
Figure 65
POSITIVE OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
13.1
−50
7
VO − Negative Output Voltage Swing − V
−3
75
I O − Output Current Sourcing − mA
I IB − Input Bias Current − µ A
−10
POSITIVE POWER SUPPLY
REJECTION RATIO
vs
POSITIVE POWER SUPPLY
−PSSR − Negative Power Supply Rejection Ratio − dB
INPUT BIAS CURRENT
vs
INPUT COMMON MODE RANGE
+PSSR − Positive Power Supply Rejection Ratio − dB
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
3.0
3 3.5 4.0
4 4.5 5.0
5 5.5 6.0
6 6.5 7.0
7 7.5
7.5
3 3.5 4.0
4 4.5 5.0
5 5.5 6.0
6 6.5
6.5 7.0
7 7.5
3.0
±Power Supply − V
±Power Supply − V
Figure 71
Figure 72
15
www.ti.com
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
OVERDRIVE RECOVERY TIME
OVERDRIVE RECOVERY TIME
10
VI
8
6
6
4
4
2
0
−2
VO
SR − Slew Rate − V/ µ s
VI
V − Voltage − V
V − Voltage − V
10 k
10
8
2
0
VO
−2
−4
−4
−6
G = −1
RL = 100 Ω
VCC = 15 V,
VCC = ±5 V
1k
−6
−8
−10
0.0
RL = 100 Ω
VCC = 15 V
0.2
−8
0.4
0.6
0.8
−10
0.0
1.0
1
RL = 100 Ω
VCC = ±5 V
0.2
t − Time − µs
100
0.4
0.6
1
1.0
0.8
0
1
t − Time − µs
Figure 73
2
3.0
VCC = 15 V
RL = 100 Ω
2.5
2.0
VO − Output Voltage − V
SR − Slew Rate − V/ µ s
5
OUTPUT VOLTAGE
TRANSIENT RESPONSE
100 k
VCC = ±5 V
RL = 100 Ω
1k
4
Figure 75
SLEW RATE
vs
OUTPUT VOLTAGE
10 k
3
VO − Output Voltage − V
Figure 74
SLEW RATE
vs
OUTPUT VOLTAGE
SR − Slew Rate − V/ µ s
SLEW RATE
vs
OUTPUT VOLTAGE
10 k
1k
1.5
1.0
G = −1
RL = 500 Ω
VCC = ±5 V
Rf = 250 Ω
VO = 5 VPP
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
100
100
1
2
3
4
5
6
−3.0
0
Figure 76
1.4
1
0.99
0.98
0.97
1.2
1.1
1
0.9
0.8
0.7
0.5
10
30
50
70
90
110
Settling Time − ns
Figure 79
0
130
150
0
10 20 30 40 50 60 70 80 90 100
Settling Time − ns
Figure 80
10
20
30
40
50
60
ts − Settling Time − ns
Figure 78
0.6
0.96
16
12
VCC = 15 V,
VO = 2 VPP,
G = −2,
Rf = 450 Ω
1.3
1.01
0.95
10
SETTLING TIME
VO − Output Voltage − V
VO − Output Voltage − V
1.02
8
1.5
VCC = 15 V,
VO = 2 VPP,
G = −2,
Rf = 450 Ω
1.03
6
Figure 77
SETTLING TIME
1.04
4
VO − Output Voltage − V
VO − Output Voltage − V
1.05
2
DC_CMRR − Common Mode Rejection Ratio High − dB
0
DC COMMON-MODE REJECTION
RATIO HIGH
vs
INPUT COMMON MODE RANGE
70
60
50
RL = 100 Ω
40
30
20
10
0
−7.5 −5.5 −3.5 −1.5 0.5 2.5 4.5 6.5
Input Common Mode Range − V
Figure 81
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
VCC = ±5 V
−25
−30
−35
VCC
−40
−45
VEE
−50
−55
−60
0.1 M
1M
10 M
100 M
0.35
0.035
−10
VCC = 15 V
−15
−20
−25
−30
−35
VCC
−40
−45
VEE
−50
−55
1M
f − Frequency − Hz
100 M
DIFFERENTIAL GAIN ERROR
vs
150-Ω LOADS
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
VCC = 15 V
0.05
0.005
1
2
3
VCC = ±5 V
0.015
0.15
VCC = 15 V
0.005
0.05
3
6
0.035
0.07
NTSC
G=2
0.05
NTSC
G = −2
0.030
0.06
VCC = ±5 V
0.04
0.03
0.02
VCC = 15 V
0.01
VCC = ±5 V
0.025
0.05
0.020
0.04
0.015
0.03
VCC = 15 V
0.010
0.02
0.005
0.01
0.000
0.00
1
4
5
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
0.00
0.000
0.00
4
Figure 84
Differential Phase Error− °
Differential Phase Error − °
0.020
0.20
2
VCC = ±5 V
0.10
0.010
1G
0.06
NTSC
G = −2
2
3
4
5
6
1
2
150-Ω Loads
150-Ω Loads
Figure 85
DIFFERENTIAL GAIN ERROR
vs
150-Ω LOADS
3
4
150-Ω Loads
Figure 86
Figure 87
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
0.004
0.40
0.07
PAL
G=2
0.035
0.35
0.06
Differential Phase Error − °
1
0.15
0.015
150-Ω Loads
Figure 83
Differential Gain Error − %
Differential Gain Error− %
10 M
Figure 82
0.010
0.10
0.20
0.020
f − Frequency − Hz
0.030
0.30
0.025
0.25
0.25
0.025
0.00
0.000
−60
0.1 M
1G
NTSC
G=2
0.30
0.030
Differential Gain Erroe − %
−20
DIFFERENTIAL GAIN ERROR
vs
150-Ω LOADS
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSSR − Power Supply Rejection Ratio − dB
PSSR − Power Supply Rejection Ratio − dB
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
0.030
0.30
0.025
0.25
VCC = ±5 V
0.020
0.20
0.15
0.015
VCC = 15 V
0.010
0.10
VCC = ±5 V
0.05
0.04
0.03
VCC = 15 V
0.02
0.01
0.005
0.05
0.000
0.00
PAL
G=2
0.00
1
2
3
4
150-Ω Loads
Figure 88
5
6
1
2
3
4
5
6
150-Ω Loads
Figure 89
17
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
APPLICATION INFORMATION
INTRODUCTION
The THS3202 is a high-speed, operational amplifier configured in a current-feedback architecture. The device is built
using Texas Instruments BiCOM−ΙΙ process, a 15-V, dielectrically isolated, complementary bipolar process with NPN
and PNP transistors possessing fTs of several GHz. This configuration implements an exceptionally
high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion.
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current-feedback amplifiers, the bandwidth of the THS3202 is an inversely proportional function of the
value of the feedback resistor. The recommended resistors for the optimum frequency response are shown in Table 1.
These should be used as a starting point and once optimum values are found, 1% tolerance resistors should be used
to maintain frequency response characteristics. For most applications, a feedback resistor value of 750 Ω is
recommendeda good compromise between bandwidth and phase margin that yields a very stable amplifier.
Table 1. Recommended Resistor Values for Optimum Frequency Response
THS3202 RF for AC When Rload = 100 Ω
GAIN
1
2
5
10
−1
Vsup
15
Peaking
Optimum
RF Value
619
±5
Optimum
619
15
Optimum
536
±5
Optimum
536
15
Optimum
402
±5
Optimum
402
15
Optimum
200
±5
Optimum
200
15
Optimum
450
±5
Optimum
450
As shown in Table 1, to maintain the highest bandwidth with an increasing gain, the feedback resistor is reduced. The
advantage of dropping the feedback resistor (and the gain resistor) is the noise of the system is also reduced
compared to no reduction of these resistor values, see noise calculations section. Thus, keeping the bandwidth as
high as possible maintains very good distortion performance of the amplifier by keeping the excess loop gain as high
as possible.
Care must be taken to not drop these values too low. The amplifier’s output must drive the feedback resistance (and
gain resistance) and may place a burden on the amplifier. The end result is that distortion may actually increase due
to the low impedance load presented to the amplifier. Careful management of the amplifier bandwidth and the
associated loading effects needs to be examined by the designer for optimum performance.
The THS3202 amplifier exhibit very good distortion performance and bandwidth with the capability of utilizing up to
15 V power supplies. Their excellent current drive capability of up to 115 mA driving into a 20-Ω load allows for many
versatile applications. One application is driving a twisted pair line (i.e., telephone line). Figure 90 shows a simple
circuit for driving a twisted pair differentially.
18
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
+6 V
THS3202(a)
0.1 µF
+
10 µF
RS
+
_
VI+
RLine
2n2
499 Ω
1:n
0.1 µF
Telephone Line
210 Ω
RLine
THS3202(b)
VI−
RS
+
_
RLine
2n2
499 Ω
0.1 µF
10 µF
+
−6 V
Figure 90. Simple Line Driver With THS3202
Due to the large power supply voltages and the large current drive capability, power dissipation of the amplifier must
not be neglected. To have as much power dissipation as possible in a small package, the THS3202 is available only
in a MSOP−8 PowerPAD package (DGN) and SOIC−8 package (D). Again, power dissipation of the amplifier must
be carefully examined or else the amplifiers could become too hot and performance can be severely degraded. See
the Power Dissipation and Thermal Considerations section for more information on thermal management.
NOISE CALCULATIONS
Noise can cause errors on very small signals. This is especially true for amplifying small signals coming over a
transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for voltage
feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify different
current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current parameter. The
noise model is shown in Figure 91. This model includes all of the noise sources as follows:
•
•
•
•
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN− = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx )
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
Rf
eRg
IN−
Rg
Figure 91. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
ni
+
Ǹǒ
ǒ
2
e nǓ ) IN )
R
Ǔ
S
2
ǒ
) IN *
ǒR f ø RgǓǓ
2
ǒ
Ǔ
) 4 kTR s ) 4 kT R ø R g
f
where:
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
Rf || Rg = Parallel resistance of Rf and Rg
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall
amplifier gain (AV).
e no + e
A
ni V
+ e
ni
ǒ
1)
R
Ǔ
f
Rg
(Noninverting Case)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop
gain is increased (by reducing RF and RG), the input noise is reduced considerably because of the parallel resistance
term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the
internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources
smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and
make noise calculations much easier.
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure
is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and
is typically 50 Ω in RF applications.
NF +
e 2ȳ
ȱ
10logȧe ni ȧ
Ȳ Rs2 ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage,
we can approximate noise figure as:
NF +
20
ȱ ȡǒ Ǔ2 ǒ
ȧ en ) IN )
ȧ
Ȣ
ȧ
10logȧ1 )
4 kTR
ȧ
S
ȧ
Ȳ
R
2ȣȳ
Ǔ
S ȧȧ
Ȥȧ
ȧ
ȧ
ȧ
ȴ
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE
Achieving optimum performance with high frequency amplifier-like devices in the THS320x family requires careful
attention to board layout parasitic and external component types.
Recommendations that optimize performance include:
D
Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output
and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
D
Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-µF and 100 pF decoupling
capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal
I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 µF
or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply
pins. These may be placed somewhat farther from the device and may be shared among several devices in the
same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return
paths. For driving differential loads with the THS3202, adding a capacitor between the power supply pins
improves 2nd order harmonic distortion performance. This also minimizes the current loop formed by the
differential drive.
D
Careful selection and placement of external components preserve the high frequency performance of the
THS320x family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use
wirebound type resistors in a high frequency application. Since the output pin and inverting input pins are the most
sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as
possible to the inverting input pins and output pins. Other network components, such as input termination
resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero that can effect circuit
operation. Keep resistor values as low as possible, consistent with load driving considerations.
D
Connections to other wideband devices on the board may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power
planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the
outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an RS since the THS320x family
is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS
are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and
the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched
impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion
as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material
and trace dimensions, a matching series resistor into the trace from the output of the THS320x is used as well as
a terminating shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective impedance should be set to match the trace impedance. If
the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve
signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is
some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
D
Socketing a high speed part like the THS320x family is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the THS320x family parts directly onto the board.
21
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
PowerPAD DESIGN CONSIDERATIONS
The THS320x family is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 92(a) and Figure 92(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 92(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can
be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During
the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a
copper area underneath the package. Through the use of thermal paths within this copper area, heat can be
conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 92. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ ÓÓÓ
68 Mils x 70 Mils
(Via diameter = 10 mils)
Figure 93. DGN PowerPAD PCB Etch and Via Pattern
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
PowerPAD PCB LAYOUT CONSIDERATIONS
1.
Prepare the PCB with a top side etch pattern as shown in Figure 93. There should be etch for the leads as well
as etch for the thermal pad.
2.
Place five holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so
that solder wicking through the holes is not a problem during reflow.
3.
Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS320x family IC. These additional vias may be larger than the 10-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area
to be soldered so that wicking is not a problem.
4.
Connect all holes to the internal ground plane.
5.
When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes
under the THS320x family PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6.
The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes
exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder
from being pulled away from the thermal pad area during the reflow process.
7.
Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8.
With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
POWER DISSIPATION AND THERMAL CONSIDERATIONS
To maintain maximum output capabilities, the THS3202 does not incorporate automatic thermal shutoff protection.
The designer must take care to ensure that the design does not violate the absolute maximum junction temperature
of the device. Failure may result if the absolute maximum junction temperature of 150°C is exceeded. For best
performance, design for a maximum junction temperature of 125°C. Between 125°C and 150°C, damage does not
occur, but the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation
for a given package can be calculated using the following formula.
P Dmax +
Tmax * T A
q JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the case (°C/W).
θCA is the thermal coefficient from the case to ambient air (°C/W).
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
For systems where heat dissipation is more critical, the THS320x family of devices is offered in an 8-pin MSOP with
PowerPAD and the THS3202 is available in the SOIC−8 PowerPAD package offering even better thermal
performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional
SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the
PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of not
soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat
and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.
PD − Maximum Power Dissipation − W
4.0
TJ = 125°C
3.5
3.0
θJA = 58.4°C/W
2.5
θJA = 98°C/W
2.0
1.5
1.0
0.5
0.0
−40
θJA = 158°C/W
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x3”
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJA = 98°C/W for 8-Pin SOIC High Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
Figure 94. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important
to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility
into a possible problem.
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken.
The first is to realize that the THS3202 has been internally compensated to maximize its bandwidth and slew-rate
performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases
the device’s phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 95.
A minimum value of 10 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting
the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance
matching at the source end.
Rg
Rf
Input
_
10 Ω
Output
THS3202
+
CLOAD
Figure 95. Driving a Capacitive Load
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
GENERAL CONFIGURATIONS
A common error for the first-time CFB user is creating a unity gain buffer amplifier by shorting the output directly to
the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS3202, like all
CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the
output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low
impedance. This results in an unstable amplifier and should not be considered when using a current-feedback
amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented on a VFB amplifier,
have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal
of the operational-amplifier (see Figure 96).
Rg
Rf
f
V
−
VO
+
VI
R1
–3dB
O +
V
I
ǒ
+
1)
1
2pR1C1
Ǔǒ
R
f
Rg
Ǔ
1
1 ) sR1C1
C1
Figure 96. Single-Pole Low-Pass Filter
If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because
the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high
slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. An
example is shown in Figure 97.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
Rg
Rf
–3dB
Rg =
+
(
1
2pRC
Rf
1
2−
Q
)
Figure 97. 2-Pole Low-Pass Sallen-Key Filter
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 98, adds a resistor
in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and the feedback
impedance never drops below the resistor value. The second, shown in Figure 99, uses positive feedback to create
the integration. Caution is advised because oscillations can occur due to the positive feedback.
C1
Rf
V
Rg
O +
VI
−
VI
VO
+
THS3202
S) 1 ȣ
ȡ
ǒRgf Ǔȧ SRfC1ȧ
Ȣ
Ȥ
R
Figure 98. Inverting CFB Integrator
Rg
Rf
For Stable Operation:
R2
−
THS320x
VO
+
R1 || RA
VO ≅ VI
R1
R2
(
≥
Rf
Rg
Rf
Rg
sR1C1
1+
)
VI
C1
RA
Figure 99. Noninverting CFB Integrator
The THS3202 may also be employed as a very good video distribution amplifier. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number
of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution
system to minimize reflections and capacitive loading.
Rg
Rf
75-Ω Transmission Line
−
75 Ω
VO1
+
VI
75 Ω
75 Ω
THS3202
N Lines
75 Ω
VON
75 Ω
Figure 100. Video Distribution Amplifier Application
26
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