THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 D Low Power ADSL Line Driver Ideal for D D D D D D D THERMALLY ENHANCED SOIC (DWP) PowerPAD PACKAGE (TOP VIEW) Central Office – 1.35-W Total Power Dissipation for Full-Rate ADSL Into a 25-Ω Load Low-Impedance Shutdown Mode – Allows Reception of Incoming Signal During Standby Two Modes of Operation – Class-G Mode: 4 Power Supplies, 1.35 W Power Dissipation – Class-AB Mode: 2 Power Supplies, 2 W Power Dissipation Low Distortion – THD = –62 dBc at f = 1 MHz, VO(PP) = 20 V, 25-Ω Load – THD = –69 dBc at f = 1 MHz, VO(PP) = 2 V, 25-Ω Load 400-mA Minimum Output Current Into a 25-Ω Load High Speed – 65-MHz Bandwidth (– 3dB) , 25-Ω Load – 100-MHz Bandwidth (– 3dB) , 100-Ω Load – 1200 V/µs Slew Rate Thermal Shutdown and Short Circuit Protection Evaluation Module Available PAD† VCCH– 1OUT VCCL– 1IN– 1IN+ NC SHDN1 SHDN2 PAD† 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PAD† VCCH+ 2OUT VCCL+ 2IN– 2IN+ NC NC DGND PAD† NC – Not Connected (SIDE VIEW) Cross section view showing PowerPAD † This terminal is internally connected to the thermal pad. MicroStar Junior (GQE) PACKAGE (TOP VIEW) description The THS6032 is a low-power line driver ideal for asymmetrical digital subscriber line (ADSL) applications. This device contains two high-current, high-speed current-feedback drivers, which can be configured differentially for driving ADSL signals at the central office. The THS6032 features a unique class-G architecture to lower power consumption to 1.35 W. The THS6032 can also be operated in a traditional class-AB mode to reduce the number of power supplies to two. HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY DEVICE THS6002 THS6012 THS6022 THS6032 THS6062 THS6072 THS7002 DRIVER RECEIVER • • • • • • • • 5V • ±5 V ±15 V • • • • • • • • • • • • • • DESCRIPTION 500-mA differential line driver and receiver 500-mA differential line driver 250-mA differential line driver 500-mA low-power ADSL central-office line driver Low-noise ADSL receiver Low-power ADSL receiver Low-noise programmable-gain ADSL receiver CAUTION: The THS6032 provides ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and MicroStar Junior are trademarks of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 description The class-G architecture supplies current to the load from four supplies. For low output voltages (typically – 2.5 < VO < +2.5), some of the output current is supplied from the +VCC(L) and –VCC(L) supplies (typically ± 5 V). For large output voltages (typically VO < – 2.5 and VO > + 2.5), the output current is supplied from +VCC(H) and –VCC(H) (typically ± 15 V). This current sharing between VCC(L) and VCC(H) minimizes power dissipation within the THS6032 output stages for high crest factor ADSL signals. The THS6032 features a low-impedance shutdown mode, which allows the central office to receive incoming calls even after the device has been shut down. The THS6032 is available packaged in the patented PowerPAD package. This package provides outstanding thermal characteristics in a small-footprint surface-mount package, which is fully compatible with automated surface-mount assembly procedures. It is also available in the new MicoStar Junior BGA package. This package is only 25 mm2 in area, allowing for high density PCB designs. Shutdown (SHDN1 and SHDN2) allows for powering down the internal circuitry for power conservation or for multiplexing. Separate shutdown controls are available for each channel on the THS6032. The control levels are TTL compatible. When turned off, each driver output is placed in a low impedance state which is determined by the voltage at DGND. This virtual ground at the outputs allows proper termination of a transmission line. AVAILABLE OPTIONS PACKAGED DEVICES PACKAGED DEVICES TA PowerPAD PLASTIC SMALL OUTLINE (DWP) MicroStar Junior (BGA) (GQE) 0°C to 70°C THS6032CDWP THS6032CGQE THS6032IDWP THS6032IGQE – 40°C to 85°C † The THS6032 is available taped and reeled. Add an R suffix to the device type (i.e.,THS6032CDWPR) ‡ Uses the THS6032CGQE packaging option. Terminal Functions TERMINAL NAME 2 DWP PACKAGE TERMINAL NO. GQE PACKAGE TERMINAL NO. 1OUT 3 B1 1IN– 5 F1 1IN+ 6 H1 2OUT 18 B9 2IN– 16 F9 2IN+ 15 H9 VCCH– VCCH+ 2 A3 19 A7 VCCL– VCCL+ 4 D1 17 D9 SHDN1 8 J2 SHDN2 9 J4 DGND 12 J7 PAD 1, 10, 11, 20 N/A NC 7, 13, 14 N/A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EVALUATION MODULES THS6032EVM THS6032GQE EVM‡ — THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 pin assignments V CCH– V CCH+ MicroStar Junior (GQE) PACKAGE (TOP VIEW) A 1OUT 2 NC NC NC B C VCCL– 1 NC D E NC F 3 NC NC 4 5 6 7 8 9 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 2OUT NC VCCL+ NC 1IN– 2IN– G NC H NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 2IN+ 1IN+ NC NC NC NC DGND NC SHDN2 NC SHDN1 J NOTE: Shaded terminals are used for thermal connection to the ground plane. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 functional block diagram (SOIC package) 19 1OUT 3 18 17 1IN– 1IN+ 5 6 – – + + 16 15 VCCH+ 2OUT VCCL+ 2IN– 2IN+ VCCH– 2 VCCL– SHDN1 SHDN2 4 8 9 12 DGND NOTE A: Terminals 1, 10, 11, and 20 are internally connected to the thermal pad. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC(L) and VCC(H) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCCH Output current, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 4 V Total power dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating free-air temperature, TA, C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 125°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. VCC(L) must always be less than or equal to VCC(H) 2. The THS6032 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See the Thermal Information section for more information about utilizing the PowerPAD thermally enhanced packages. DISSIPATION RATING TABLE‡ PACKAGE θJA (°C/W) θJC (°C/W) DWP 21.5 0.37 GQE 37.8 4.56 TA = 25°C POWER RATING 5.8 W 3.3 W ‡ This data was taken using 2 oz. trace and copper pad that is soldered directly to a JEDEC standard 4 layer 3 in × 3 in PCB. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 recommended operating conditions Supply Su ly voltage Operating free-air free air temperatures, temperatures TA MIN NOM MAX VCC(L) – Class G mode VCC(L) – Class AB mode ±3 ±5 ± VCCH UNIT V 0 0 0 V VCC(H) C-suffix ±5 ± 15 ± 16 V 0 70 I-suffix – 40 85 °C electrical characteristics, VCC(L) = ±5 V, VCC(H) = ±15 V, RL = 25 Ω, TA = 25 °C (unless otherwise noted) dynamic performance PARAMETER TEST CONDITIONS Gain = 1, 1 RF = 1.3 1 3 kΩ Gain = 2, 2 RF = 1.1 1 1 kΩ ( 3 dB) Small signal bandwidth (–3 BW Bandwidth for 0.1 0 1 dB flatness SR Full power bandwidth† Slew rate‡ MIN TYP RL = 25 Ω 65 RL = 100 Ω 100 RL = 25 Ω 60 RL = 100 Ω 70 MAX UNIT MHz MHz Gain = 1 30 Gain = 2 25 VOPP = 20 V Gain = 5, 19 MHz 1200 V/µs 120 ns ts Settling time to 0.1% Gain = 1, † Full power bandwidth = slew rate/2π VPEAK ‡ Slew rate is defined from the 25% to the 75% output levels. RL = 25 Ω, VO(PP) = 20 V 5 V Step MHz noise/distortion performance PARAMETER TEST CONDITIONS THD Total harmonic distortion VO = 20 V(pp), Gain = 5, VO = 2 V(pp), Gain = 2, Vn Input voltage noise f = 10 kHz In TYP f = 1 MHz – 62 f = 1 MHz – 69 2.4 In+ In– Input current noise f = 10 kHz Differential gain error Gain = 2, 2 NTSC Differential phase error Gain = 2 2, NTSC Crosstalk f = 1 MHz, Gain = 2, POST OFFICE BOX 655303 MIN 11 15 RL = 150 Ω 0.016% RL = 25 Ω 0.020% RL = 150 Ω 0.04° RL = 25 Ω 0.30° RF = 1.1 kΩ • DALLAS, TEXAS 75265 – 62 MAX UNIT dBc nV/√Hz nV/√Hz dB 5 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 electrical characteristics, VCC(L) = ±5 V, VCC(H) = ±15 V, RL = 25 Ω, TA = 25 °C (unless otherwise noted) (continued) dc performance PARAMETER Z(t) VIO TEST CONDITIONS MIN TYP Open loop transimpedance RL = 1 kΩ 1.5 Input offset voltage TA = 25°C TA = full range 0.5 Differential offset voltage TA = 25°C TA = full range TA = 25°C TA = full range 1.5 Negative input bias current 1.5 Positive input bias current TA = 25°C TA = full range MAX 2 MΩ 5 7 Offset voltage drift 10 IIB UNIT mV µV/°C 3 6 mV 9 12 9 µA A 12 input characteristics PARAMETER VICR CMRR ri TEST CONDITIONS Input common-mode voltage range Common-mode rejection ratio TA = full range Inverting terminal Input resistance MIN TYP ± 13.2 ± 13.4 V 64 72 dB 15 Ω 400 kΩ 1.4 pF Non inverting terminal Differential input capacitance MAX UNIT output characteristics PARAMETER VO Output voltage MIN TYP Single-ended RL = 25 Ω TEST CONDITIONS ± 10.5 ± 11 Differential RL = 50 Ω ± 21 ± 22 MAX UNIT V IO Output current† RL = 25 Ω 400 440 mA † ISC Short-circuit current 800 mA † A heat sink is required to keep junction temperature below absolute maximum when an output is heavily loaded or shorted. See “absolute maximum ratings.” power supply PARAMETER VCC TEST CONDITIONS VCCL VCCH Operating range VCCL ICC Quiescent current (per amplifier) VCCL Power supply rejection ratio VCCH 6 0 ±5 TA = 25°C TA = full range POST OFFICE BOX 655303 TA = full range TA = 25°C MAX ± 5 ±VCCH ± 16.5 ± 15 4 80 TA = full range 66 69 V mA 5 5.5 90 UNIT 5.8 6.2 TA = full range TA = 25°C • DALLAS, TEXAS 75265 TYP 4.3 TA = 25°C VCCH PSRR MIN mA 100 dB 80 dB THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 electrical characteristics, VCC(L) = ±5 V, VCC(H) = ±15 V, RL = 25 Ω, TA = 25 °C (unless otherwise noted) (continued) shutdown characteristics PARAMETER TEST CONDITIONS VIL VIH Shutdown voltage for power up Relative to DGND terminal Shutdown voltage for power down Relative to DGND terminal IIH IIL Shutdown input current-high Shutdown input current-low V(SHDN) = 5 V V(SHDN) = 0.5 V Zo ICCL Output impedance (while in shutdown state) V(SHDN) = 2.5 V, f = 1 MHz Supply current (per amplifier) (while in shutdown state) V(SHDN) = 2 2.5 5V V, VO = 0 V ICCH tdis ten Disable time† Enable time† MIN TYP MAX UNIT 0.8 V 200 300 µA 20 40 µA 2 V Ω 0.5 0.05 0.2 2.4 3 mA 1.1 µS 1.5 µS † Disable/enable time begins when the logic signal is applied to the shutdown terminal and ends when the supply current has reached half of its final value. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 2 0.3 –1 RF = 1.5 kΩ –2 –3 –4 –5 –6 –7 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +1 RL = 25 Ω VO = 0.2 VRMS 1M VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +1 RL = 25 Ω VO = 0.2 VRMS 0.2 0.1 RF = 1 kΩ –0.0 –0.1 RF = 1.3 kΩ –0.2 –0.3 10 M 100 M f – Frequency – Hz 1M 5.8 RF = 1.3 kΩ 100 M RF = 1.5 kΩ 11 10 9 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RL= 25 Ω Vo = 0.2 VRMS 1M G = +2 RF =1.1 kΩ VCC(H) = ± 15 V VCC(L) = GND G = +1 RF =1.3 kΩ RL = 25 Ω VI = 0.2 VRMS 1M 10 M f – Frequency – Hz Figure 7 8 100M 500M 17 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +10 RL= 25 Ω Vo = 0.2 VRMS 16 15 100k 1M 10M 100M f – Frequency – Hz SMALL AND LARGE SIGNAL FREQUENCY RESPONSE 18 2 500 M Gain = +1, RF = 1.3 kΩ –2 –4 –6 100 M Gain = +2, RF = 1.1 kΩ 4 0 –8 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V RL = 100 Ω VIN = 0.2 VRMS 1M 10 M 100 M 500 M f – Frequency – Hz Figure 8 POST OFFICE BOX 655303 500M Figure 6 V O – Normalized Output Voltage – dBV 6 Output Amplitude – dB Class-AB Mode Output Amplitude – dB –6 100 k RF = 1 kΩ 18 13 10M 8 0 –4 19 OUTPUT AMPLITUDE vs FREQUENCY 6 500 M RF = 510 Ω Figure 5 8 100 M 20 14 f – Frequency – Hz CLASS-AB MODE OUTPUT AMPLITUDE vs FREQUENCY –2 21 12 7 100k 500 M 10 M OUTPUT AMPLITUDE vs FREQUENCY RF = 820 Ω 13 Figure 4 2 1M Figure 3 14 f – Frequency – Hz 4 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω VO = 0.4 VRMS 22 8 10 M 1 f – Frequency – Hz Output Amplitude – dB Output Amplitude – dB Output Amplitude – dB RF = 1.1 kΩ 1M 2 –1 100 k 500 M RF = 330 Ω 15 6.0 5.6 100 k 100 M 16 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω VO = 0.4 VRMS RF = 820 Ω 5.7 RF = 1.3 kΩ 3 OUTPUT AMPLITUDE vs FREQUENCY 6.4 5.9 4 Figure 2 OUTPUT AMPLITUDE vs FREQUENCY 6.1 5 f – Frequency – Hz Figure 1 6.2 10 M RF = 1.1 kΩ 6 0 RF = 1.5 kΩ –0.4 100 k 500 M RF = 820 Ω 7 Output Amplitude – dB RF = 1.3 kΩ RF = 1 kΩ 0 Output Amplitude – dB Output Amplitude – dB 8 0.4 1 6.3 OUTPUT AMPLITUDE vs FREQUENCY • DALLAS, TEXAS 75265 12 6 0 –6 –12 –18 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V VO(PP) = 4 V VO(PP) = 2 V VO(PP) = 1 V VO(PP) = 0.5 V VO(PP) = 0.25 V Gain = +1 RL = 25 Ω RF = 1.3 k Ω 1M 10 M f – Frequency – Hz Figure 9 100 M 500 M THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS CLASS-G MODE DISTORTION vs FREQUENCY SMALL AND LARGE SIGNAL FREQUENCY RESPONSE VO(PP) = 2 V 6 VO(PP) = 1 V 0 VO(PP) = 0.5 V –6 –12 100 k –30 –40 –50 –60 –70 –80 3rd Harmonic –90 Gain = +2 RL = 25 Ω RF = 1.1 k Ω 1M 10 M 100 M –100 100 k 500 M 1M 3RD Order Distortion – dBc VCC(L) = GND –60 –70 –75 –80 VCC(L) = ± 6 V VCC(L) = ± 6 V VCC(L) = ± 5 V –85 10 15 20 5 CROSSTALK vs FREQUENCY SLEW RATE vs OUTPUT STEP Input = Ch. 2 Output = Ch. 1 Input = Ch. 1 Output = Ch. 2 0 f – Frequency – Hz Figure 16 100 M 500 M 10 15 20 Figure 15 VOLTAGE AND CURRENT NOISE vs FREQUENCY 1000 VCC(H) = ± 15 V VCC(L) = ± 5 V TA = 25°C +SR –SR 800 600 400 0 10 M 5 VO(PP) – Output Voltage – V 200 1M –85 100 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω 1200 –70 –80 100 k VCC(H) = ± 15 V Gain = +5 RF= 1.1 kΩ RL = 25 Ω f = 1 MHz –80 20 1400 –60 VCC(L) = ± 5 V –75 Hz –50 15 Figure 14 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RF = 1.1 kΩ RL = 25 Ω VCC(L) = ± 7.5 V –70 I n – Current Noise – pA/ –40 –65 Hz –30 10 Figure 13 SR – Slew Rate – V/ µs –20 VCC(L) = ± 6 V –60 VO(PP) – Output Voltage – V 0 –10 VCC(L) = GND –55 –90 0 VO(PP) – Output Voltage – V Crosstalk – dB VCC(L) = ± 7.5 V –90 5 10 M 20 M THD vs OUTPUT VOLTAGE –65 VCC(L) = GND 0 1M Figure 12 V n – Voltage Noise – nV/ 2ND Order Distortion – dBc VCC(L) = ± 7.5 V –90 2nd Harmonic –90 f – Frequency – Hz VCC(H) = ± 15 V Gain = +5 RF= 1.1 kΩ RL = 25 Ω f = 1 MHz –55 –75 –85 3rd Harmonic –80 –50 –50 –70 –80 –70 –100 100 k 10 M 20 M THD –60 3RD ORDER DISTORTION vs OUTPUT VOLTAGE VCC(H) = ± 15 V Gain = +5 RF= 1.1 kΩ RL = 25 Ω f = 1 MHz VCC(L) = ± 5 V –65 –50 Figure 11 2ND ORDER DISTORTION vs OUTPUT VOLTAGE –60 –40 f – Frequency – Hz Figure 10 –55 VCC(H) = ± 15 V VCC(L) = GND Gain = +2 RF = 1.1 kΩ RL = 25 Ω VO(PP) = 2 V –30 2nd Harmonic f – Frequency – Hz –50 THD Class-AB Mode Distortion – dBc VO(PP) = 4 V 12 VCC(H) = ± 15 V VCC(L) = ± 5 V to ± 7.5 V Gain = +2 RF = 1.1 kΩ RL = 25 Ω VO(PP) = 2 V Total Harmonic Distortion – dBc VO(PP) = 8 V 18 –20 –20 VCC(H) = ± 15 V VCC(L) = ± 5 V Class-G Mode Distortion – dBc V O – Normalized Output Voltage – dBV 24 CLASS-AB MODE DISTORTION vs FREQUENCY In– 10 In+ VN 1 0 5 10 15 20 VO(pp) – Output Voltage Step – V Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 100 1k 10 k 100 k f – Frequency – Hz Figure 18 9 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS POWER SUPPLY REJECTION RATIO vs FREQUENCY VCC(H) = ± 15 V VCC(L) = ± 5 V RL= 1 kΩ 120 100 80 60 40 20 1k 10 k 100 k 1M 10 M 100 M 1G 120 80 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RF = 1.1 kΩ RL = 25 Ω 60 –VCC(L) 100 +VCC(L) 40 ±VCC(H) 20 0 10 k 0 10 k 100 k 1M 10 M 3.0 0 20 40 60 80 11.8 11.6 +VOUT 11.4 11.2 11.0 –VOUT 10.8 10.6 –40 100 –20 0 20 40 60 80 Figure 22 1.2 –20 Differential Gain – % 1.25 1 0.75 lib– 0.5 TA – Free-Air Temperature – °C 80 100 Gain = 2 RF = 1.1 kΩ 40 IRE Modulation Worst Case ± 100 IRE Ramp 0.4 PAL 0.02 NTSC 0.3 PAL 0.2 NTSC 0.1 VCC(H) = ± 15 V VCC(L) = ± 5 V VCC(H) = ± 15 V VCC(L) = ± 5 V 0.0 0 100 60 DIFFERENTIAL PHASE vs LOADING 0.03 0.25 80 40 0.5 0.01 60 20 Figure 24 Gain = 2 RF = 1.1 kΩ 40 IRE Modulation Worst Case ± 100 IRE Ramp 0.04 lib+ 1.5 0 TA – Free-Air Temperature – °C DIFFERENTIAL GAIN vs LOADING 1.75 Figure 25 1.4 1.0 –40 100 0.05 40 1.6 Figure 23 INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 20 VCC(H)= ± 15 VCC(L)=± 5 V 1.8 TA – Free-Air Temperature – °C 2 100 M 2.0 VCC(H)= ± 15 V VCC(L)=± 5 V TA – Free-Air Temperature – °C I IB – Input Bias Current – µ A 10 INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE V IO – Input Offset Voltage – mV VOUT – Maximum Output Voltage – V I CC – Supply Current – mA ICC(H) 3.5 2.5 10 20 MAXIMUM OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE ICC(L) 0 30 Figure 21 12.0 –20 40 Figure 20 VCC(H) = ± 15 V VCC(L) = ± 5 V Per Amplifier –20 50 Figure 19 4.0 0 –40 100 M 60 f – Frequency – Hz 4.5 2.0 –40 10 M VCC(H) = ± 15 V VCC(L) = ± 5 V RF = 1 kΩ RL = 25 Ω 70 f – Frequency – Hz 6.0 5.0 1M 80 f – Frequency – Hz SUPPLY CURRENT vs FREE-AIR TEMPERATURE 5.5 100 k Differential Phase – % Transimpedance – dBΩ PSRR – Power Supply Rejection Ratio – dB 140 COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR – Common-Mode Rejection Ratio – dB TRANSIMPEDANCE vs FREQUENCY 1 2 3 4 5 6 7 8 Number of 150 Ω Loads Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2 3 4 5 6 Number of 150 Ω Loads Figure 27 7 8 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS STANDBY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 100 10 Shut-down Mode 1 Not Shut-down 0.1 0.01 100 k 56 3.00 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RF = 1 kΩ 1M 10 M 100 M f – Frequency – Hz 2.75 52 2.25 50 48 2.00 ICC(L) 46 1.75 44 –40 –20 0 –10 –50 –60 Reverse Isolation –70 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = –1 RL = 25 Ω RF = 1.1 kΩ VI = 0.2 VRMS –20 Shutdown Isolation – dB –30 –40 –50 Forward Isolation –60 –70 –80 –80 –90 100 k –90 100 k 1M 10 M 100 M 500 M 100 M Figure 30 Figure 31 500 M –0.2 –0.4 –0.6 100 Figure 33 150 SHUTDOWN RESPONSE Gain = +2 RF = 1.1 kΩ RL = 25 Ω 5 0 800 600 400 200 0 –200 0 200 2 4 6 8 10 12 14 16 18 20 t – Time – µs 10 V PULSE RESPONSE VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RL = 25 Ω RF = 1.1 kΩ 1 6 0 –1 –2 t – Time – ns 100 8 2 –0.0 50 80 10 5 VOLT STEP RESPONSE VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω RF = 1.1 kΩ 0 60 Figure 32 3 V O – Output Voltage – V V O – Output Voltage – V 10 M f – Frequency – Hz 1 VOLT STEP RESPONSE 0.2 1M f – Frequency – Hz 0.6 0.4 Reverse Isolation V O – Output Voltage – V Shutdown Isolation – dB –40 Forward Isolation V O – Output Voltage – mV V SD – Shutdown Voltage – V SHUTDOWN ISOLATION vs FREQUENCY –10 –30 40 Figure 29 SHUTDOWN ISOLATION vs FREQUENCY VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +2 RL = 25 Ω RF = 1.1 kΩ VI = 0.2 VRMS 20 TA – Free-Air Temperature – °C Figure 28 –20 54 ICC(H) 2.50 1.50 500 M VCC(H) = ± 15 V VCC(L) = ± 5 V VSD = 2.5 V Per Amplifier I CC(L) – Stanby Supply Current – µA 1000 I CC(H) – Stanby Supply Current – mA Z o – Closed Loop Output Impedance – Ω CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY 4 2 0 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω TR/TF = 6 ns –2 –4 –6 –3 –8 0 50 100 150 200 t – Time – ns Figure 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 25 50 75 100 125 150 175 200 225 250 t – Time – ns Figure 35 11 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION ADSL The THS6032 was primarily designed as a low-power line driver for ADSL (asymmetrical digital subscriber line). The driver output stage has been sized to provide full ADSL power levels of 20 dBm onto the telephone lines. Although actual driver output peak voltages and currents vary with each particular ADSL application, the THS6032 is specified for a minimum full output current of 400 mA at its full output voltage of approximately 11 V. This performance meets the demanding needs of ADSL at the central office end of the telephone line. A typical ADSL schematic is shown in Figure 36. VCC(H)15 V 0.1 µF 0.1 µF THS6032 Driver 1 VI+ + 6.8 µF 12.5 Ω + _ 1:2 680 Ω 0.1 µF 6.8 µF + –VCC(H) –15 V 0.1 µF 1 kΩ VCC(L) 6 V 200 Ω VI– 15 V 0.1 µF THS6032 Driver 2 100 Ω Telephone Line + 2 kΩ 6.8 µF 0.1 µF 12.5 Ω + _ 1 kΩ – + THS6072 VO+ 680 Ω 0.1 µF 6.8 µF + 1 kΩ –VCC(L) –6 V 2 kΩ Driver 1 kΩ – + VO– THS6072 0.1 µF –15 V Receiver Figure 36. THS6032 ADSL Application 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION ADSL (continued) The ADSL transmit band consists of 255 separate carrier frequencies, each with its own modulation and amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies. The THS6032 has been specifically designed for ultralow distortion by careful circuit implementation and by taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended distortion measurements are shown in Figures 11 – 15. It is commonly known that in the differential driver configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion (THD) will be primarily due to the third order harmonics. Additionally, distortion should be reduced as the feedback resistance drops. This is because the bandwidth of the amplifier increases, which allows the amplifier to react faster to any nonlinearities in the closed-loop system. Another significant point is the fact that distortion decreases as the impedance load increases. This is because the output resistance of the amplifier becomes less significant as compared to the output load resistance. One problem that has been receiving a lot of attention in the ADSL area is power dissipation. One way to substantially reduce power dissipation is to lower the power supply voltages. This is because the RMS voltage of an ADSL central office signal is 1.65-V RMS at each driver’s output with a 1:2 transformer. But, to meet ADSL requirements, the drivers must have a voltage peak-to-RMS crest factor of 5.6 in order to keep the bit-error probability rate below 10– 7. Hence, the power supply voltages must be high enough to accomplish the driver’s peak output voltage of 1.65 V × 5.6 = 9.25 V(PEAK ). This high peak output voltage requirement, coupled with a low RMS voltage requirement, does not lend itself to conventional high efficiency designs. One way to save power is to decrease the bias currents internal to the amplifier. The drawback of doing this is an increase in distortion and a lower frequency response bandwidth. This is where the THS6032 class-G architecture is useful. The class-G output stage utilizes both a high supply voltage [VCC(H) typically ± 15 V] and a low supply voltage [(VCC(L) typically ± 6 V]. As long as the output voltage is less than [VCC(L) – 2.5 V], then part of the output current will be drawn from the VCC(L) supplies. If the output signal goes above this cutoff point [for example, VO > VCC(L) – 2.5 V], then all of the output current will be supplied by VCC(H). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION ADSL (continued) To ensure that the cutoff point does not introduce distortion into the system, the entire output stage is always biased on. This constant biasing scheme will cause a decrease in the efficiency over hard switching class-G circuits, but the very low distortion results tend to outweigh the efficiency loss. The biasing scheme used in the THS6032 can be shown by the currents being supplied by the VCC(L) power supplies in Figure 37. This graph shows there is no discrete current transfer point between the VCC(L) supplies and the VCC(H) supplies. This was done to ensure low distortion throughout the entire output range. By changing the VCC(L) supply voltage, the system efficiency can be tailored to suit almost any system with high crest factor requirements. OUTPUT CURRENT DISTRIBUTION vs OUTPUT VOLTAGE 100 Output Current Distribution – % VCC(H) = 15 V VI = 1 MHz RL = 25 Ω ICC(L) Current Draw 90 80 70 60 VCC(L) = ±5 V 50 40 VCC(L) = ±7.5 V 30 20 10 0 0 1 2 3 4 5 6 7 RMS – Output Voltage – V Figure 37 class-AB mode operation The class-G architecture produces sizable power dissipation savings over traditional class-AB designs while maintaining low distortion requirements. The only drawback to the class-G design is the requirement of 4 power supply voltages, 2 more than a typical line driver requires. In certain instances, the addition of two separate power supplies may be cost prohibitive or PCB space prohibitive. There are two options in this case, use a traditional amplifier, such as a THS6012, or use the THS6032 in class-AB mode. Using the THS6032 in class-AB mode will give several functional benefits over the THS6012. This includes shutdown capability, low-impedance output while in shutdown state, and a slight reduction in quiescent current. One important thing to remember is that the THS6032 running in class-AB mode, will be only about as efficient as the THS6012. This means that the power dissipation of the THS6032 will increase dramatically and must be accounted for. Failure to do so will result in a part which continuously overheats and may lead to failure. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION class-AB mode operation (continued) To use the THS6032 in class-AB mode, the user should always connect the VCC(L) power supply pins to GND. The internal VCC(L) paths were not designed for continuous full output current and could possibly fail. The VCC(H) paths were designed for the full output currents and thus, should be used for class-AB mode operation. The performance of the THS6032 while in class-AB mode is very similar to the class-G mode. Figure 7 and Figures 12 to15 show the THS6032 while in class-AB mode. device protection features The THS6032 has two built-in features that protect the device against improper operation. The first protection mechanism is output current limiting. Should the output become shorted to ground the output current is automatically limited to the value given in the data sheet. While this protects the output against excessive current, the device internal power dissipation increases due to the high current and large voltage drop across the output transistors. Continuous output shorts are not recommended and could damage the device. Additionally, connection of the amplifier output to one of the high supply rails [± VCC(H) ] can cause failure of the device and is not recommended. The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above approximately 180°C, the device automatically shuts down. Such a condition could exist with improper heat sinking or if the output is shorted to ground. When the junction temperature drops below 150°C, the internal thermal shutdown circuit automatically turns the device back on. thermal information The THS6032 is available in a thermally-enhanced DWP package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 38(a) and Figure 38(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 38(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. DIE Thermal Pad Side View (a) DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 38. Views of Thermally Enhanced DWP Package POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION thermal information (continued) The THS6032 is also available in the MicroStar Junior GQE package. Just like the DWP package, the GQE package utilizes the PowerPAD functionality to improve thermal performance. The GQE package is part of the new ball-grid array (BGA) family developed by Texas Instruments (TI). This package allows for even higher density layouts with virtually no loss in thermal performance. Its construction is similar to the DWP construction (see Figure 39 (a) and (b)), but utilizes the BGA’s to transfer the heat away from the die. (TOP VIEW) (Side VIEW) Die (b) (a) NOTE: Shaded areas are part of the thermally conductive path. Figure 39. Views of Thermally Enhanced GQE Package The PowerPAD packages allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads or balls are being soldered), the thermal areas can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. This is discussed in more detail in the PCB design considerations section of this document. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. Because of its power dissipation, proper thermal management of the THS6032 is required. There are several ways to properly heatsink both the DWP and GQE packages. There are several TI application notes on how to best accomplish the thermal mounting scheme required for each package. For the DWP package, refer to the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package, literature number SLMA002. There is also a more compact technical paper entitled PowerPad Made Easy, literature number SLMA004. For the GQE – MicroStar Junior package, refer to the MicroStar BGA Packaging Reference Guide, literature number SSYZ015A and the compact version entitled MicroStar Junior Made Easy, literature number SSYA009. This literature is available on TI’s web site at http://www.ti.com. TI is a trademark of Texas Instruments Incorporated. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION thermal information (continued) The actual thermal performance achieved with the THS6032 in its PowerPAD package depends on the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches, then the expected thermal coefficient, θJA, is about 21.5°C/W for the DWP package and 37.8°C/W for the GQE package. For a given θJA, the maximum power dissipation is shown in Figure 40 and is calculated by the following formula: P D + ǒ T Ǔ –T MAX A q JA Where: PD = Maximum power dissipation of THS6032 (watts) TMAX = Absolute maximum junction temperature (150°C) = Free-ambient air temperature (°C) TA θJA = θJC + θCA θJC = Thermal coefficient from junction to case (DWP =0.37°C/W; GQE = 4.56°C/W) θCA = Thermal coefficient from case to ambient MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 9 TJ = 150°C PCB Size = 3” x 3” No Air Flow Maximum Power Dissipation – W 8 7 DWP θJA = 21.5°C/W 2 oz Trace and Copper Pad with Solder 6 5 GQE 4 3 2 1 0 –40 DWP θJA = 43.9°C/W 2 oz Trace and Copper Pad without Solder –20 0 20 40 60 80 100 TA – Free-Air Temperature – °C Figure 40. Maximum Power Dissipation vs Free-Air Temperature POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION PCB design considerations Proper PCB design techniques in two areas are important to assure proper operation of the THS6032. These areas are high-speed layout techniques and thermal-management techniques. Because the THS6032 is a high-speed part, the following guidelines are recommended. D Ground plane – It is essential that a ground plane be used on the board to provide all components with a low inductive ground connection. Although a ground connection directly to a terminal of the THS6032 is not necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and it provides the path for heat removal. D Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input must be as short as possible, the ground plane must be removed under any etch runs connected to the inverting input, and external components should be placed as close as possible to the inverting input. This is especially true in the noninverting configuration. An example of this can be seen in Figure 41, which shows what happens when a 2.2 pF capacitor is added to the inverting input terminal in the noninverting configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in the noninverting configuration. This can be seen in Figure 42, where a 27-pF capacitor adds only 2.5 dB of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor decreases. While this can initially appear to be a faster and better system, overshoot and ringing are more likely to occur under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input node should always be performed for stable operation. OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 4 2 1 4 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +1 RL = 25 Ω VO = 0.2 VRMS Ci = 2.2 pF 0 –1 –2 –3 VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = –1 RL = 25 Ω VO = 0.2 VRMS 3 Output Amplitude – dB Output Amplitude – dB 3 Ci = 0 pF –4 2 1 Ci = 27 pF 0 –1 Ci = 0 pF –2 –3 –4 –5 100 k 1M 10 M 100 M 500 M –5 100 k f – Frequency – Hz Ci 1M 10 M 100 M 500 M f – Frequency – Hz 1.3 kΩ 1.1 kΩ 1.1 kΩ VI – + 50 Ω VO VI 50 Ω 25 Ω Ci Figure 41 18 – + Figure 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VO RL = 25 Ω THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION PCB design considerations (continued) D Proper power supply decoupling – Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminal and the ceramic capacitors. D Differential power supply decoupling – The THS6032 was designed for driving low-impedance differential signals. The 25 Ω load which each amplifier drives causes large amounts of currents to flow from amplifier to amplifier. Power supply decoupling for differential current signals must be accounted for to ensure low distortion of the THS6032. By simply connecting a 0.1-µF ceramic capacitor from the +VCC(H) pin to the –VCC(H) pin, along with another 0.1-µF ceramic capacitor from the +VCC(L) pin to the –VCC(L) pin, differential current loops will be minimized (see Figure 36). This will help keep the THS6032 operating at peak performance. recommended feedback and gain resistor values As with all current feedback amplifiers, the bandwidth of the THS6032 is an inversely proportional function of the value of the feedback resistor. This can be seen from Figures 1 to 6. The recommended resistors for the optimum frequency response with a 25-Ω load system can be seen in Table 1. These should be used as a starting point and once optimum values are found, 1% tolerance resistors should be used to maintain frequency response characteristics. For most applications, a feedback resistor value of 1.3 kΩ is recommended, which is a good compromise between bandwidth and phase margin that yields a very stable amplifier. Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback resistor value and the internal dominant-pole capacitor. The ability to control the amplifier gain independently of the bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value of the gain resistor to increase or decrease the overall amplifier gain. Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance decreases the loop gain and increases the distortion. It is also important to know that decreasing load impedance increases total harmonic distortion (THD). Typically, the third order harmonic distortion increases more than the second order harmonic distortion. Table 1. Recommended Feedback Resistor Values for 25 Ω Loads GAIN 1 Rf 1.3 kΩ 2, – 1 1.1 kΩ 5 820 Ω 7.8 680 Ω 10 510 Ω POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION shutdown control There are two shutdown pins which control the shutdown for each amplifier of the THS6032. When the shutdown pin signals are low, the THS6032 is active. But, when a shutdown pin is high (≥ 2 V), the corresponding amplifier is turned off. The shutdown logic is not latched and should always have a signal applied to it. To help ensure a fixed logic state, an internal 50 kΩ resistor to DGND is utilized. An external resistor, such as a 3.3 kΩ, to DGND may be added to help improve noise immunity within harsh environments. If no external resistor is utilized and SHDNX pins are left unconnected, the THS6032 will default to a power-on state. A simplified circuit can be seen in Figure 43. +VCC(H) To Internal Bias Circuitry Control SHDNX 50 kΩ DGND –VCC(H) DGND Figure 43. Simplified THS6032 Shutdown Control Circuit shutdown function The THS6032 incorporates a shutdown circuit to conserve power. Traditionally when an amplifier is placed into shutdown mode, the input and output circuitry are turned off. This conserves a large amount of power, but the output impedance will be a very high, typically greater than several kΩ. This situation does not allow for proper line termination resulting in a severe reduction of the receive signal coming through the transmission line (see Figure 36). The THS6032 eliminates this problem. When the SHDNX pin voltage is greater than 2 V, the THS6032 enters shutdown mode to conserve power. Unlike the traditional amplifier, the THS6032’s output impedance is typically 0.5 Ω at 1 MHz (see Figure 28). The shutdown mode function results in the proper termination of the line without degradation in performance of the receive signal coming through the transmission line. There are a few design considerations in order to fully achieve this type of functionality. To better understand these design considerations, it is helpful to examine what is happening inside the THS6032. Figure 44 shows the simplified shutdown components. Notice that there are two similar input stages; the normal input stage consisting of transistors Q1 through Q4 and the shutdown input stage consisting of transistors QS1 through QS4. When in shutdown mode, the I(BIAS – 1) and I(BIAS – 2) current sources are turned off. This turns off the normal input stage of the amplifier. The I(BIAS – S1) and I(BIAS – S2) current sources are then turned on. The shutdown input stage signals are then fed through the same internal circuitry which the normal input stage drove. This allows for sinking and sourcing large amounts of current at the output of the THS6032 during shutdown operation. The QS1 through QS4 transistors are not designed for the performance like the Q1 through Q4 transistors because their only function is to amplify the DC ground reference, DGND. A 1-kΩ resistor connects internally to the output node of the amplifier, which provides a feedback loop in shutdown mode. This forces the output impedance to become very small, making for proper transmission line termination. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION shutdown function (continued) +VCC(H) IBIAS–S1 QS1 Active Load IBIAS–1 Q1 QS3 Q3 Q5 1 kΩ +IN Pin DGND –IN Pin Q6 QS2 To Internal Output Node QS4 IBIAS–S2 Q2 To Output Drive Circuitry Q4 Active Load IBIAS–2 –V CC(H) Shut–Down Circuitry Figure 44. Simplified THS6032 Input Stages Because the DGND pin voltage is effectively at a noninverting terminal, any signal or voltage fluctuation at this node is amplified by the THS6032. This could possibly cause a noisy output to appear during shutdown operation. Figure 45 shows the frequency response of the THS6032 due to an input signal at the DGND terminal. The maximum DGND voltage signal which the THS6032 will follow linearly during shutdown operation is less than ± 4 V. With this dynamic range capability, it is recommended that the DGND pin be as noise-free as possible to ensure proper transmission line termination. DGND OUTPUT AMPLITUDE vs FREQUENCY 3 DGND Output Amplitude – dB 2 1 VO(PP) = 0.2 V 0 –1 VO(PP) = 2 V –2 –3 –4 –5 –6 100 k VCC(H) = ± 15 V VCC(L) = ± 5 V RL = 25 Ω VSD = +10 V VI = DGND Pin 1M 10 M 100 M f – Frequency – Hz Figure 45 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION shutdown function (continued) The second design consideration is due to transistors Q5 and Q6. These transistors ensure the +IN to – IN voltage separation is less than a VBE drop (about 0.7 V). This protects the other transistors, Q1 to Q4, from saturating during fast transients. Transistors Q5 and Q6 also enhance the slew rate capabilities of the THS6032. When a fast transient is applied to the input, these transistors will quickly apply the currents to the active load stages. A design issue with this setup is that while in shutdown mode, a large enough signal being applied to the input pins may turn on these transistors. Once the input voltage differential between the +IN and – IN pins reaches ± 0.7-V, transistors Q5 and Q6 turn on applying the difference signal to the rest of the amplifier circuitry. Because these two transistors are designed for much higher performance levels than the shutdown circuitry transistors (QS3 and QS4), they will become dominant and the difference input signal will be utilized instead of the DGND signal. Because the external negative feedback resistor path is still connected around the amplifier, this difference input signal will be amplified just like a normal amplifier is designed to do (see Figure 46). As long as the +IN and – IN input signals are kept below ± 0.7 V, the isolation from input-to-output is very high as shown in the Shutdown Isolation vs Frequency graphs (see Figures 30 and 31). To ensure proper shutdown functionality of the THS6032, it is important to keep the DGND voltage noise-free. Additionally, the +IN and – IN signals should be limited to less than ± 0.7 V during shutdown mode. This will ensure proper line termination functionality while conserving power. SHUTDOWN FEEDTHROUGH 7 VOUT – Output Voltage – V 6 G=5 G=2 G = +1; G = –1 5 4 3 2 VCC(H)= ± 15 V VCC(L)=± 5 V RL = 25 Ω VSD = 5 V 1 0 0 2 4 6 8 10 VIN – Input Voltage – V Figure 46 slew rate The slew rate performance of a current feedback amplifier, like the THS6032, is affected by many different factors. Some of these factors are external to the device, such as amplifier configuration and PCB parasitics, and others are internal to the device, such as available currents and node capacitance. Understanding some of these factors should help the PCB designer arrive at a more optimum circuit with fewer problems. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION slew rate (continued) Whether the THS6032 is used in an inverting amplifier configuration or a noninverting configuration can impact the output slew rate. Slew rate performance in the inverting configuration is generally faster than the noninverting configuration. This is because in the inverting configuration the input terminals of the amplifier are at a virtual ground and do not significantly change voltage as the input changes. Consequently, the time to charge any capacitance on these input nodes is less than for the noninverting configuration, where the input nodes actually do change in voltage an amount equal to the size of the input step. In addition, any PCB parasitic capacitance on the input nodes degrades the slew rate further simply because there is more capacitance to charge. If the main supply voltage VCC(H) to the amplifier is reduced, slew rate decreases because there is less current available within the amplifier to charge the capacitance on the input nodes as well as other internal nodes. Also, as the load resistance decreases, the slew rate typically decreases due to the increasing internal currents, which slow down the transitions. Internally, the THS6032 has other factors that impact the slew rate. The amplifier’s behavior during the slew rate transition varies slightly depending upon the rise time of the input. This is because of the way the input stage handles faster and faster input edges. Slew rates (as measured at the amplifier output) of less than about 1200 V/µs are processed by the input stage in a very linear fashion. Consequently, the output waveform smoothly transitions between initial and final voltage levels. For slew rates greater than 1200 V/µs, additional slew-enhancing transistors present in the input stage (transistors Q5 and Q6 in Figure 44) begin to turn on to support these faster signals. The result is an amplifier with extremely fast slew rate capabilities. The additional aberrations present in the output waveform with these faster slewing input signals are due to the brief saturation of the internal current mirrors. This phenomenon, which typically lasts less than 20 ns, is considered normal operation and is not detrimental to the device in any way. If for any reason this type of response is not desired, then increasing the feedback resistor or slowing down the input signal slew rate reduces the effect. SLEWING 20 V PULSE 16 6 12 4 8 V O – Output Voltage – V V O – Output Voltage – V SLEWING 10 V PULSE 8 2 SR = 1400 V/µs VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω TR/TF = 1 ns 0 –2 –4 –6 4 SR = 4000 V/µs VCC(H) = ± 15 V VCC(L) = ± 5 V Gain = +5 RF = 1.1 kΩ RL = 25 Ω TR/TF = 1 ns 0 –4 –8 –12 –16 –8 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 t – Time – ns t – Time – ns Figure 47 Figure 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION noise calculations and noise figure Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only difference between the two is that the CFB amplifiers generally specify different current noise parameters for each input, while VFB amplifiers usually only specify one noise current parameter. The noise model is shown in Figure 49. This model includes all of the noise sources as follows: • • • • en = Amplifier internal voltage noise (nV/√Hz) IN+ = Noninverting current noise (pA/√Hz) IN– = Inverting current noise (pA/√Hz) eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx ) eRs RS en Noiseless + _ eni IN+ eno eRf RF eRg IN– RG Figure 49. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e Where: ni + Ǹǒ ǒ 2 e nǓ ) IN ) R Ǔ S 2 ǒ ) IN– ǒRF ø RGǓǓ 2 ǒ Ǔ ) 4 kTR s ) 4 kT R ø R F G k = Boltzmann’s constant = 1.380658 × 10–23 T = Temperature in degrees Kelvin (273 +°C) RF || RG = Parallel resistance of RF and RG To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni ) by the overall amplifier gain (AV). e no + e 24 ǒ Ǔ R A + e ni 1 ) F (Noninverting Case) ni V RG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing RG ), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS ) and the internal amplifier noise voltage (en ). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. For more information on noise analysis, please refer to Noise Analysis in Operational Amplifier Circuits, literature number SLVA043A This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 Ω in RF applications. ȱ eni 2 ȳ ȧ 2ȧ ȲǒeRsǓ ȴ NF + 10log Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: NF + ȱ ȡǒe Ǔ2 ) ǒIN ) n ȧ ȧ Ȣ 10logȧ1 ) 4 kTR S ȧ ȧ Ȳ R ȳ Ǔ2ȣ ȧ S POST OFFICE BOX 655303 Ȥȧ ȧ ȧ ȧ ȴ • DALLAS, TEXAS 75265 25 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION noise calculations and noise figure (continued) Figure 50 shows the noise figure graph for the THS6032. NOISE FIGURE vs SOURCE RESISTANCE 20 18 16 14 Noise Figure – dB 12 10 8 6 4 f = 10 kHz TA = 25 Deg. C 2 0 10 100 1000 10000 Source Resistance – RS (Ω ) Figure 50. Noise Figure vs Source Resistance offset voltage The output offset voltage, (VOO ) is the sum of the input offset voltage (VIO ) and both input bias currents (IIB ) times the corresponding gains. Figure 51 can be used to calculate the output offset voltage. RF IIB– RG + – VI IIB+ V OO +V IO ǒ ǒ ǓǓ 1) R R F G VO + RS "I IB) R S ǒ ǒ ǓǓ 1) R R F G "I IB– Figure 51. Output Offset Voltage Model 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 R F THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION general configurations A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6032, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when using a current-feedback amplifier. Because of this, simple low-pass filters, which are easily implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 52). RG RF O + V I ǒ –3dB + V – VI VO + R1 f C1 1) R R F G Ǔǒ Ǔ 1 1 ) sR1C1 1 2pR1C1 Figure 52. Single-Pole Low-Pass Filter If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. One implementation of the Sallen-Key filter is shown in Figure 53. For more information on Sallen-Key filters, refer to the Analysis of the Sallen-Key Architecture, literature number SLOA024A. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG RF –3dB RG = + ( 1 2pRC RF 1 2– Q ) Figure 53. 2-Pole Low-Pass Sallen-Key Filter Another good use for the THS6032 amplifiers is as video distribution amplifiers. One characteristic of distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution system to minimize reflections and capacitive loading. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 APPLICATION INFORMATION general configurations (continued) 1.1 kΩ 1.1 kΩ 1/2 THS6032 75 Ω Transmission Line 75 Ω – VO1 + VI 75 Ω 75 Ω N Lines 75 Ω VON 75 Ω Figure 54. Video Distribution Amplifier Application driving a capacitive load Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS6032 has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 55. A minimum value of 10 Ω should work well for most applications. For example, in ADSL systems, setting the series resistor value to 12.5 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 1.1 kΩ 1.1 kΩ Input _ 10 Ω Output THS6032 + CLOAD Figure 55. Driving a Capacitive Load evaluation board Evaluation boards are available for the THS6032. Each board has been configured for proper thermal management of the THS6032 depending on package selection. The circuitry has been designed for a typical ADSL application as shown previously in this document. To order the evaluation board, contact your local TI sales office or distributor. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 MECHANICAL DATA DWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 20-PIN SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 20 0.010 (0,25) M 11 Thermal Pad (See Note D) 0.419 (10,65) 0.400 (10,16) 0.299 (7,59) 0.010 (0,25) NOM 0.293 (7,45) Gage Plane 1 10 0.010 (0,25) A 0°–ā8° 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.006 (0,15) 0.004 (0,10) 0.002 (0,05) PINS ** 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4147575/A 04/98 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. PowerPAD is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 THS6032 LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER SLOS233C – APRIL1999 – REVISED MARCH 2000 MECHANICAL DATA GQE (S-PLGA-N80) PLASTIC LAND GRID ARRAY 5,20 SQ 4,80 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,93 0,87 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,33 0,23 ∅ 0,05 M 0,08 0,08 MAX 4200461/A 10/99 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar Junior LGA configuration MicroStar Junior LGA is a trademark of Texas Instruments Incorporated. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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