TI TI380C60

SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
D Facilitates Connection of the TI380C25,
D
D
D
EQ −
TMS
EQ +
TCLK
TRST
TDO
TDI
RATER
VDDD
OSC32
RCVR
VSSD
RCLK
3
37
VSSD
DRVR+
4
36
5
35
IREF
DRVR−
6
34
VSSA2
ATEST
WFLT
7
33
NSRT
8
32
VSSL
FRAQ
9
31
10
30
VDDL
REDY
11
29
12
28
NABL
13
27
VSSA1
RCV+
VDDA1
RCV−
VDDA2
XT1
VSSO
XT2
VDDO
VDDL
VSSL
VDDP
RES
14 15 16 17 18 19 20 21 22 23 24 25 26
VSSP
PHOUTA
D
38
XMT−
D
2
VDDX
PHOUTB
D
39
VDDD
WRAP
XMT+
D
1
PWRDN
VSSX
D
52 51 50 49 48 47 46 45 44 43 42 41 40
PXTAL
S4 / 16
D
TI380C26, or TI380C27 to Token Ring
Internal Crystal Oscillator for
Reference-Clock Generation
Loop Back (Wrap Mode) for Self-Test
Diagnostics
Compatible With Electrical Interface of
ISO/IEC 8802.5: 1995 (ANSI/IEEE Std. 802.5)
Token-Ring Access Method and Physical
Layer Specifications
Glueless Interface to TI380C2x
COMMprocessor for Token Ring
16- and 4-Mbps Token-Ring Data Rates
With no External Switching Circuits
Repeater Application Requires no
Additional Active Components
Digital Phase-Locked Loop
− Precise Control of Bandwidths
− Improved Jitter Tolerance
− Minimizes Accumulated Phase Slope
Phantom Drive for Physical Insertion Onto
Ring
Differential Line Receiver With
Level-Dependent Frequency Equalization
Low-Impedance Differential Line Driver to
Ease Transmit-Filter Design
REPT
D
PAH PACKAGE
( TOP VIEW )
D On-Chip Watchdog Timer
D Low-Power Enhanced Performance
Implanted CMOS (EPIC) 0.8-µm Process
D PCMCIA-Compatible 52-Lead 1,0-mm
Plastic Quad Flatpack
description
The TI380C60 token-ring interface device is a full-duplex electrical interface compatible with ISO / IEC
8802.5:1995 (ANSI / IEEE Std. 802.5) token-ring access method and physical layer specifications. The
TI380C60 operates at the IEEE standard 4- and 16-Mbps data rates. The Manchester-encoded data stream
is received and phase-aligned using an on-chip phase-locked loop ( PLL). Both the recovered clock and data
are passed to the protocol-handling circuits of one of the TI380C2x single-chip token-ring COMMprocessors
for serial-to-parallel conversion and data processing. On transmit, the TI380C60 buffers the output of the
TI380C2x and drives the media by way of suitable isolation and waveform-shaping components.
All necessary functions required to interface with an IEEE-802.5 token ring are provided. These include the PLL,
the phantom drive to control the relays within a trunk-coupling unit, and wire-fault detection circuits. An internal
wrap function is provided for self test, and a watchdog timer is included to provide fail-safe deinsertion from the
ring in the event of a station microcode or COMMprocessor failure.
The TI380C60, when coupled with one of the TI380C2x token-ring COMMprocessors, forms a highly integrated
token-ring LAN adapter compatible with the ISO / IEEE Standard 802.5. The TI380C60 synthesizes the
necessary token-ring reference clock for its own use and for the TI380C2x. This removes the need for external
components to provide this function.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
1
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
description (continued)
The TI380C60 can function as a stand-alone device because the digital PLL is self-contained and requires no
additional circuits for frequency management. Using the device in this manner in the repeat mode provides a
highly integrated token-ring repeater with no additional active components suitable for wiring center
applications.
The TI380C60 is available in a 52-lead 1,0-mm plastic quad flatpack and is characterized for operation from
0°C to 95°C with a typical power dissipation of 600 mW.
Pin Functions
PIN
NAME
NO.
I / O / E†
TYPE‡
DESCRIPTION
ATEST
33
E
N
Analog test. ATEST should be left unconnected.
DRVR+
DRVR−
5
6
I
I
D
D
Differential driver data inputs. DRVR+ and DRVR− receive the ’380C2x transmit data.
EQ +
EQ −
41
40
E
E
N
N
Equalization / gain points. EQ+ and EQ- provide connections to allow frequency tuning of
equalization circuit.
FRAQ
10
I
TTL
Frequency acquisition control. FRAQ is driven by the ’380C2x or can be tied low for repeater
applications.
H = Clock recovery PLL is initialized
L = Normal operation
IREF
35
E
N
Internal reference. IREF allows the internal bias current of analog circuitry to be set by way
of an external resistor.
TTL
Output-enable control. NABL can be used in token-ring / Ethernet applications to disable
the token-ring function. (See Note 1)
H = TI380C60 operates normally
L = All outputs are driven to the high-impedance state, except XMT+ / XMT− which
are driven low. Internal logic continues to operate unless PWRDN is asserted low.
NABL
13
I
NSRT
8
I
TTL
Insert control. NSRT enables the phantom-driver outputs (PHOUTA and PHOUTB) through
the watchdog timer for insertion onto the token ring.
Static high = Inactive, phantom current removed (due to watchdog timer)
Static low
= Inactive, phantom current removed (due to watchdog timer)
Falling edge = Active, current output on PHOUTA and PHOUTB
PHOUTA
PHOUTB
23
21
O
O
N
N
Phantom-driver outputs A and B. PHOUTA and PHOUTB are the outputs that cause
insertion onto the token ring. PHOUTA and PHOUTB should be connected to the center tap
of the transmit transformer secondary winding for phantom-drive generation.
PWRDN
16
I
TTL
Power-down control
H = Normal operation. PWRDN is required to be tied to VCC with an external pullup
resistor of 4.7 kΩ.
L = TI380C60 is placed into a power-down state. All TTL outputs are driven to the
high-impedance state.
PXTAL
1
O
TTL
Token-ring reference-clock output. For 16-Mbps operations, PXTAL is a 32-MHz clock; and
for 4-Mbps operations, PXTAL is an 8-MHz clock.
OSC32
48
O
TTL
Oscillator output. OSC32 provides a 32-MHz clock output and can be used to drive OSCIN
of a TI380C2x.
TTL
Repeat-mode enable
L = Repeat mode selected. The received and sampled data present on RCVR is also
driven out on the XMT+ / XMT− pair. This function is overridden if WRAP is
asserted low.
H = TI380C60 operates normally. (See Note 1)
REPT
15
I
† I = input, O = output, E = provides external-component connection to the internal circuitry for tuning
‡ TTL = TTL signal, N = non-TTL signal, D = differential drive or data
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
Ethernet is a trademark of Xerox Corporation.
2
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
Pin Functions (Continued)
PIN
NAME
NO.
I / O / E†
TYPE‡
DESCRIPTION
RATER
47
O
TTL
Rate error. RATER indicates that there are transitions on RCV+ / RCV− input pair
(DRVR+ / DRVR− if WRAP is asserted low) but that the transition rate is not consistent with
the ring speed selected by S4 / 16.
RCLK
51
O
TTL
Recovered clock. RCLK is the clock recovered from the token-ring received data. For
16-Mbps operations, it is a 32-MHz clock. For 4-Mbps operations, it is an 8-MHz clock.
RCV+
RCV−
38
36
I
I
D
D
Receiver inputs. RCV+ and RCV− receive the token-ring data by way of isolation
transformers.
RCVR
50
O
TTL
Recovered data. RCVR contains the data recovered from the token ring and should be
sampled at the rising edge of RCLK.
PLL ready. REDY is normally asserted (active) low. REDY is cleared following the assertion
of FRAQ and reasserted after the data recovery PLL has been reinitialized.
H = Received data not valid
L = Received data valid
REDY
12
O
TTL
RES
25
—
—
S4 / 16
14
I
TTL
Speed switch. S4 / 16 specifies the token-ring data rate.
H = 4-Mbps data rate
L = 16-Mbps data rate
TCLK
TMS
TDI
TDO
43
42
45
46
I
I
I
O
TTL
Test ports used during the production test of the device. TCLK, TMS, TDI, and TDO should
be left unconnected.
TRST
44
I
TTL
Test-port reset. TRST should be tied to ground for normal operation of the TI380C60.
H = Reserved
L = Test ports forced to an idle state
TTL
Phantom-wire fault. WFLT provides an indication of the presence of a short or open circuit
on PHOUTA or PHOUTB.
H = No fault
L = Open or short. The dc fault condition is present in the phantom-drive lines.
WFLT
7
O
Reserved. RES should be left unconnected.
WRAP
3
I
TTL
Internal wrap-mode control. WRAP allows the TI380C60 to be placed in the loopback-wrap
mode for adapter self test.
H = Normal ring operation
L = Transmit data drives the receive data. RCV+ and RCV− are ignored by the
TI380C60, and XMT+ and XMT− are both forced low.
XMT+
XMT−
18
19
E
D
Transmit differential outputs. XMT+ and XMT− provide a low-impedance differential source
for line drive by way of filtering and transformer isolation.
XT1
XT2
31
29
E
N / TTL
N
XTAL connection. An 8-MHz crystal network can be connected here to provide a reference
clock for the TI380C60. Alternatively, an 8-MHz TTL clock source can be connected to XT1.
VDDA1
VDDD
37
—
—
Positive supply voltage for receiver circuits
2, 49
—
—
Positive supply voltage for output buffers
VDDL
VDDA2
11, 27
—
—
Positive supply voltage for internal logic
32
—
—
Positive supply voltage for data recovery PLL
VDDO
VDDP
28
—
—
Positive supply voltage for XTAL oscillator
24
—
—
Positive supply voltage for phantom drive
VDDX
20
—
—
Positive supply voltage for transmit output
† I = input, O = output, E = provides external-component connection to the internal circuitry for tuning
‡ TTL = TTL signal, N = non-TTL signal, D = differential drive or data
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
Pin Functions (Continued)
PIN
NAME
NO.
I / O / E†
TYPE‡
DESCRIPTION
VSSA1
VSSA2
39
—
—
Ground reference for receiver circuits
34
—
—
Ground reference for data recovery PLL
VSSD
VSSL
4, 52
—
—
Ground reference for output buffers
9, 26
—
—
Ground reference for internal logic
VSSX
VSSO
17
—
—
Ground reference for transmit output
30
—
—
Ground reference for XTAL oscillator
VSSP
22
—
—
Ground reference for phantom drive
† I = input, O = output, E = provides external-component connection to the internal circuitry for tuning
‡ TTL = TTL signal, N = non-TTL signal, D = differential drive or data
architecture
The major blocks of the TI380C60 include the receiver / equalizer, clock recovery PLL, wrap function, phantom
drive with wire-fault detector, and watchdog timer. Figure 1 is the block diagram illustrating these major blocks,
and the functionality of each block is described in the following sections.
External
Equalizer
WRAP
EQ +
XTAL
8 MHz
REPT
EQ −
XT1
S4 / 16
ATEST
FRAQ
XT2
OSC
CKT
RCV+
RCV−
PXTAL
RCVR
RCV
Data
Receiver
NABL
Receiver
Clock
Recovery
RCLK
OSC32
FRAQ
REDY
DRVR+
DRVR−
XMT+
Transmit
XMT−
WFLT
PHOUTA
Phantom
Drive
PHOUTB
PWRDN
Rate Error
RATER
Watchdog
Timer (22 ms)
NSRT
Test Port
Bias Gen
IREF
TDI
TDO
TCLK
Figure 1. Functional Block Diagram
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
TMS
TRST
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
receiver
Figure 2 shows the arrangement of the line-receiver / equalizer circuit. The differential-input pair, RCV+ and
RCV−, are designed to be connected to a floating winding of an isolation transformer. Each is equipped with
a bias circuit to center the operating point of the differential input at approximately VDD / 2.
The differential-input pair consists of a pair of metal oxide semiconductor field effect transistors (MOSFETs),
each with an identical current source in its source pin that is set to supply a nominal current of 1.5 mA. At low
signal levels, the gain of this pair is inversely proportional to the impedance connected between their sources
on EQ − and EQ +. A frequency-equalization network can be connected between EQ + and EQ − to provide
equalization for media signal distortion.
The internal wrap mode is provided for self-test of the device. When selected by taking WRAP low, the normal
input path is disabled by a multiplexer and a path is enabled from the DRVR+ / DRVR− pair. Receiver gain,
thresholds, and equalization are unchanged in the internal wrap mode.
VDD
LOAD
36
Bias Network
RCV−
38
WRAP MUX
RCV+
LOAD
DATA
External Equalizer
EQ −
R1
R2
DATA
EQ +
40
WRAP
41
IEQB
C1
IEQB
From DRVR+ / DRVR−
VSS
Figure 2. Line Receiver / Equalizer
receiver-clock recovery
The clock and data recovery in TI380C60 is performed by an advanced, digitally controlled phase-locked loop.
In contrast to the TMS38054, the PLL of the TI380C60 is digitally controlled and the loop parameters are set
by internally programmed digital constants. This results in precise control of loop parameters and requires no
external loop-filter components.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
5
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
receiver-clock recovery (continued)
The TI380C60 implements an intelligent algorithm to determine the optimum phase position for data sampling
and extracted clock synthesis. The resulting action of the TI380C60 can be modeled as two cascaded PLLs as
shown in Figure 3.
PLL1
PLL2
RCLK
RCV Data
RCVR
f3dB ≅ 680 kHz
(see Note A)
f3dB ≅ 162 kHz
(see Note A)
NOTE A: f3dB = − 3dB bandwidth of PLL
Figure 3. Dual PLL Arrangement
PLL1 represents the algorithm to recover data from the incoming stream detected by the receiver. It has a
relatively high bandwidth to provide good jitter tolerance. Data and embedded clock phase information are fed
as digital values to PLL2, which generates the extracted clock (RCLK) for the TI380C2x COMMprocessor. The
recovered data is sent to the TI380C2x as the RCVR signal synchronous with RCLK. In addition to sampling
the RCVR signal, the TI380C2x uses RCLK to re-transmit data in most cases. The lower bandwidth of PLL2
greatly reduces the rate of accumulation of data-correlated phase jitter in a token-ring network and provides very
good accumulated-phase-slope (APS) characteristics. In addition to RCLK, the token-ring reference clock
(PXTAL) and a fixed-frequency 32-MHz clock (OSC32) are also synthesized from the 8-MHz crystal reference.
line driver, wrap function, and repeat mode
The line-drive function of the TI380C60 is performed by XMT+ and XMT−. Unlike the TMS38054, these pins
are low-impedance outputs and require external series resistance to provide line termination. These pins
provide buffering of the differential signal from the TI380C2x on DRVR+/ DRVR− with action to control skew and
asymmetry and with no re-timing in the transmit path.
The wrap function is designed to provide a signal path for system self-test diagnostics. When WRAP is taken
low, the receiver inputs are ignored and the transmit signal is fed to the receiver input circuitry by way of a
multiplexer. In the internal wrap mode, WRAP can be checked by observing the signal amplitude at the
equalization pins, EQ+ and EQ−. Equalization is active at this signal level, although the signal does not exhibit
the high-frequency attenuation effects for which equalization is intended to compensate. During internal wrap
mode, both XMT+ and XMT− are driven to a low state to prevent any dc in the isolation transformer.
When the repeat function is selected, the sampled and re-timed ring data present on RCVR is also driven out
on XMT+ and XMT−. This allows the TI380C60 to operate as a stand-alone repeater. Both RCVR and RCLK
continue to provide valid sampled ring data and extracted clock as normal. The DRVR+/ DRVR− inputs are
ignored. The repeat function is enabled by taking REPT low while holding WRAP high.
phantom driver and wire-fault detection
The phantom-drive circuit under control of NSRT generates a dc voltage on both of the phantom-drive outputs,
PHOUTA and PHOUTB. In order to maintain the phantom drive, NSRT is toggled by the TI380C2x at least once
every 20 ms. An internal watchdog timer is included in the TI380C60 to remove the phantom drive if NSRT fails
to have the required transitions.
6
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
phantom driver and wire-fault detection (continued)
The watchdog timer is normally not allowed to expire because it is being reinitialized at least every 20 ms. If there
is a problem in the TI380C2x or its microcode, resulting in failure to toggle NSRT, the timer expires in a maximum
of 22 ms. If this happens, the phantom drive is deasserted and remains so until the next falling edge of NSRT.
The watchdog timer requires no external timing components. When the phantom drive is deasserted, the
phantom-drive lines are actively pulled low, reaching a level of 1 V or less within 50 ms.
The dc voltage from PHOUTA and PHOUTB is superimposed on the transmit-signal pair to the trunk-coupling
unit (TCU) to request that the station be inserted into the ring. This is achieved by connecting them to the center
of the secondary winding of the transmit-isolation transformer. Since PHOUTA and PHOUTB are connected to
the media side of the isolation transformer, they require extensive protection against line surges. A capacitor
is connected between the two phantom lines to provide an ac path for the transmit signal. PHOUTA and
PHOUTB independently drive the dc voltage on each of the transmit lines, allowing for independent wire-fault
detection on each.
The phantom voltage is detected by the TCU, causing the external wrap path from the transmitter outputs back
to the receiver inputs to be broken, and the ring to be broken. A signal connection is then established from the
ring to the receiver inputs and from the transmitter outputs to the ring. The return current from the dc-phantom
voltage on the transmit pair is returned to the station by way of the receive pair. This provides some measure
of wire-fault detection on the receive lines. The phantom-drive outputs are current limited to prevent damage
if short-circuited. They detect either an abnormally high or an abnormally low load current at either output,
corresponding to a short or an open circuit in the ring or TCU wiring. Either fault causes the wire-fault indicator
output, WFLT, to be driven low. The logic state of WFLT is high when the phantom drive is not active.
frequency acquisition and REDY
Unlike its predecessors, the TMS3805x family, the data-recovery PLL of the TI380C60 does not require
constant frequency monitoring; neither is it necessary to recenter its frequency by way of the FRAQ control line.
However, it is necessary to provide the interaction with the TI380C2x or other COMMprocessors that expect
to perform this frequency-management task.
When the TI380C2x asserts FRAQ, it initiates a reset of the clock-recovery PLL. The REDY signal is deasserted
for the duration of this action and reasserted low when it is complete (a maximum of 3 µs later). This low-going
transition of REDY is required by the TI380C2x following the setting of FRAQ high to indicate to the
COMMprocessor that any frequency error that it detected has been corrected. In fact, the TI380C60 will never
require FRAQ to be asserted after the PLL has been initialized. This interaction is provided purely for the benefit
of the TI380C2x.
rate error (RATER) function
RATER provides an indication that incoming data transitions are present on the RCV+/ RCV− pair but that the
rate of transitions is outside the range that would be expected for the ring speed selected by S4 / 16. RATER
is not asserted low if no incoming transitions are present. In wrap mode, the rate-error function monitors the
transitions on the DRVR+/ DRVR− pair. REDY will also be de-asserted if no incoming transitions are detected
by the Rate Error function.
The rate-error function interprets 16 or more transitions in a 1.5-µs period as valid 16-Mbps data. It interprets
15 or less transitions in a 1.5-µs period as 4-Mbps data. One transition or less in a 1.5-µs period is interpreted
as no incoming transitions, in which case, RATER and REDY will not be asserted.
disable and power-down mode
The TI380C60 can be disabled by either NABL or PWRDN. If NABL is taken low, the output buffers of the
COMMproccessor interface are placed in the high-impedance state; however, internal logic continues to
operate. Phantom drive is disabled, but XMT+ and XMT− are driven to a low value to sustain line termination
in token-ring / Ethernet 10-base-T applications that share magnetics.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
7
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
disable and power-down mode (continued)
If PWRDN is taken low, all outputs are in the high-impedance state and all internal logic is powered down,
bringing power consumption to a very low level. Upon removing PWRDN, the device resets and initializes itself.
This process can take up to 2 ms and care should be taken to ensure that the system does not require stable
clocks during this period. In particular, slow-clock errors can be seen by a TI380C2x COMMprocessor in a
dual-physical-layer application if the TI380C60 is powered down when not in use.
test facilities
A 5-pin test port is included for production-device testing. While the signals are similar to ports defined by
IEEE-1149.1, this port is not compliant with the standard and the port is not suitable for in-circuit test.
ATEST gives access to the filter of the internal PLL. This pin is also for production test purposes, and no
connection should be made to it in an application.
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Input voltage range (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Power dissipation (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 W
ESD protection, VESD (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Junction-to-ambient package thermal impedance @ 0 LFPM air flow, Qja(0) . . . . . . . . . . . . . . . . . . 80.5°C/W
Junction-to-ambient package thermal impedance @ 100 LFPM air flow, Qja(100) . . . . . . . . . . . . . 64.9°C/W
Junction-to-case package thermal impedance, Qjc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9°C/W
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 95°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. All voltage values are with respect to VSS unless otherwise noted.
3. Inputs can be taken to more negative voltages if the current is limited to 20 mA.
4. Maximum power dissipation per package
5. The device is classified as ESDS class 1 (A:1500). ESD protection measured per MIL-STD-883C, Method 3015.
recommended operating conditions‡
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VDD + 0.3
0.8
V
VSB + 1
− 0.2
V
VDD
VIH
Supply voltage
All VDD
High-level input voltage (see Note 6)
TTL inputs
VIL
VIB
Low-level input voltage (see Notes 6 and 7)
TTL inputs
− 0.3
Receiver input bias voltage
See Note 8
VSB − 1
IOH
IOL
High-level output current (see Note 6)
TTL outputs
Low-level output current (see Note 6)
TTL outputs
2
2
V
mA
mA
TC
Operating case temperature range
0
95
°C
‡ Recommended operating conditions indicate the conditions that must be met to ensure that the device functions as intended and meets the
detailed electrical specifications. Unless otherwise noted, all electrical specifications apply for all recommended operating conditions. Voltages
are measured with respect to the device VSS pins. Currents into the device are considered to be positive.
NOTES: 6. The TTL input and TTL output pins are identified in the pin functions table.
7. Inputs can be taken to more negative voltages if the IDD current is limited to 20 mA.
8. VSB is the self-bias voltage of the input pair RCV+ and RCV−. It is defined as VSB = (VSB+ +VSB −) / 2 (where VSB+ is the self-bias
voltage of RCV+; VSB − is the self-bias voltage of RCV−). The self-bias voltage of both pins is approximately VDD / 2.
8
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
TTL input and output pins (see Note 6)
TEST
CONDITIONS †
PARAMETER
IIH
IIL
High-level input current
VOH
VOL
High-level output voltage
IOZH
IOZL
Off-state output current with high-level voltage applied
IDD
VI = VDD
VI = OV (PWRDN = High)
Low-level input current
VO = 2.7 V
VO = 0.4 V
Off-state output current with low-level voltage applied
Normal mode
MAX
UNIT
20
µA
− 100
−20
µA
2.6
V
− 20
− 20
VDD = MAX
Power-down mode
TYP
− 20
IOH = − 0.2 mA
IOL = 2 mA
Low-level output voltage
Supply current
MIN
0.45
V
20
µA
20
µA
120
mA
10
mA
† For conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions.
NOTE 6: The TTL input and TTL output pins are identified in the pin functions table.
receiver input (RCV+ and RCV−)
PARAMETER
TEST CONDITIONS
MAX
UNIT
VT+
Rising input threshold voltage
VT−
Falling input threshold voltage
VICM = VSB,
See Notes 8 and 9,
and Figure 6
− 50
VAT
Asymmetry threshold voltage, (VT+ + VT −) B 2
VICM = VSB,
See Notes 8 and 9,
and Figure 6
− 15
15
mV
VCM+
Rising input common-mode rejection
[VT+ (@VSB + 0.5 V) − VT+ (@VSB − 0.5 V)]
See Notes 8 and 9, and Figure 6
− 30
30
mV
VCM−
Falling input common-mode rejection
[VT− (@VSB + 0.5 V) − VT− (@VSB − 0.5 V)]
See Notes 8 and 9, and Figure 6
− 30
30
mV
Both inputs at VSB,
See Note 8 and Figure 6
− 10
10
Input under test at VSB + 1 V,
Other input at VSB − 1 V,
See Note 8 and Figure 6
10
60
Input under test at VSB − 1 V,
Other input at VSB + 1 V,
See Note 8 and Figure 6
−10
−60
1
2.2
II(RCV)
IEQB
Receiver input current
RCV+ at 4 V,
RCV+ at 1 V,
See Figure 4d
Equalizer bias current
See Notes 8 and 9,
and Figure 6
MIN
VICM = VSB,
RCV− at 1 V or
RCV− at 4 V
50
mV
mV
µA
mA
VEQW
Equalizer wrap voltage
WRAP = low,
See Figure 4d
300
700
mV
NOTES: 8. VSB is the self-bias voltage of the input pair RCV+ and RCV−. It is defined as VSB = (VSB+ +VSB −) / 2 (where VSB+ is the self-bias
voltage of RCV+; VSB − is the self-bias voltage of RCV−). The self-bias voltage of both pins is approximately VDD / 2.
9. VICM is the common-mode voltage applied to RCV+ and RCV−.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
9
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
IOL
Test
Point
1.5 V
50 pF
Test
Point
TTL
Output
Under
Test
XMT+
50 pF
330 Ω
Test
Point
XMT−
50 pF
IOH
(a) TTL-OUTPUT TEST LOAD
(b) XMT+ and XMT− TEST LOAD
IEQB
RCV+
Iref
VEQW
330 Ω
200 Ω
RCV−
(c) Iref TEST CIRCUIT
(d) EQUALIZER TEST CIRCUIT
Figure 4. Test and Load Circuits
phantom driver (PHOUTA and PHOUTB)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOS
IOL
Short-circuit output current
IOZH
IOZL
Off-state output current with high-level voltage applied
Low-level output current
Off-state output current with low-level voltage applied
MIN
IOH = − 1 mA
IOH = − 2 mA
4.1
VO = 0 V
VO = VDD
−4
VO = VDD
VO = 0 V
MAX
UNIT
V
3.8
V
− 20
mA
1
10
mA
− 100
100
µA
− 100
100
µA
MIN
MAX
UNIT
0.15
kΩ
wire fault ( WFLT ) (see Notes 10 and 11)
PARAMETER
RL(S)
Phantom-drive load resistance detected as short circuit
RL(O)
Phantom-drive load resistance detected as open circuit
50
kΩ
RL(N) Phantom-drive load resistance detected as normal
2.9
5.5
kΩ
NOTES: 10. The wire-fault circuit recognizes a fault condition for any phantom-drive load resistance to ground greater than RL(O) or any load
resistance less than RL(S). Any resistance in the range specified for RL(N) is not recognized as a wire fault. A fault condition on either
PHOUTA or PHOUTB results in WFLT being asserted (low).
11. Resistor [RL(S), RL(O), RL(N)] connected from output under test to ground, other output loaded with 4.1 Ω to ground.
10
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PLL characteristics
PARAMETER
Reference PLL operating filter voltage
TEST CONDITIONS
MIN
MAX
UNIT
tc(XT1) = 125 ns
1.8
4
TEST CONDITIONS
MIN
MAX
1.8
4
− 2.5
− 6.5
mA
0.4
1.3
mA
V
crystal-oscillator characteristics
PARAMETER
VIB(XT1)
Input self-bias voltage
IOH(XT2)
High-level output current
V(XT2) = VSB(XT1)
V(XT1) = VSB(XT1) + 0.5 V
IOL(XT2)
Low-level output current
V(XT2) = VSB(XT1)
V(XT1) = VSB(XT1) − 0.5 V
UNIT
V
switching characteristics over recommended range of supply voltage (unless otherwise noted)
transmitter-drive characteristics
PARAMETER
VPP(XMT)
XMT+ / XMT− peak-to-peak voltage (see Note 12)
TEST CONDITIONS
MIN
VDD = 4.75 V,
See Figures 4 and 5
8.2
MAX
UNIT
V
VDD = 5.25 V,
See Figures 4 and 5
10.3
NOTE 12: VPP(XMT) is determined by:
VOH(XMT+) + VOH(XMT−) − VOL(XMT+) − VOL(XMT−)
transmitter switching characteristics (see Figures 4 and 5)
PARAMETER
TEST CONDITIONS
MIN
MAX
−3
+3
ns
XMT+/XMT− skew (see Note 13)
tsk(DRV) = − 1 ns
tsk(DRV) = + 1 ns
UNIT
−3
+3
ns
XMT+/XMT− asymmetry (see Note 14)
tsk(DRV) = − 1 ns
tsk(DRV) = + 1 ns
−2
+2
ns
−2
+2
ns
NOTES: 13. XMT+/XMT− skew is determined by: td(XMT+ H) − td(XMT− L) or td(XMT+ L) − td(XMT− H)
14. XMT+/XMT− asymmetry is determined by:
t
)t
t
)t
d(XMT)L)
d(XMT)H)
d(XMT– H)
d(XMT– L)
–
2
2
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
11
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
switching characteristics over recommended range of supply voltage (unless otherwise noted)
(continued)
DRVR+
2V
1.5 V
0.45 V
DRVR−
2.4 V
1.5 V
0.45 V
tsk(DRV)
tsk(DRV)
VOH(XMT+)
V50(XMT+)
VOL(XMT+)
XMT+
td(XMT+L)
VOH(XMT−)
V50(XMT−)
VOL(XMT−)
XMT−
td(XMT− H)
Figure 5. Transmitter Timing
12
td(XMT+H)
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
td(XMT− L)
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
clock and data switching characteristics over recommended range of supply voltage,
tc(XT1) = 125 ns (see Figure 6)
TEST CONDITIONS
tc(XT1)
tw(OSC32H)
Cycle time of clock applied to XT1
tw(OSC32L)
Pulse duration, OSC32 low
tw(PXTALL)
Pulse duration, PXTAL low
Pulse duration, PXTAL high
tw(RCLKL)
Pulse duration, RCLK low
TYP
125
Pulse duration, OSC32 high
tw(PXTALH)
MIN
MAX
UNIT
ns
10
ns
12
ns
16-Mbps mode
12
ns
4-Mbps mode
46
ns
16-Mbps mode
10
ns
4-Mbps mode
46
ns
16-Mbps mode
12
ns
4-Mbps mode
46
ns
16-Mbps mode
10
ns
tw(RCLKH)
Pulse duration, RCLK high
4-Mbps mode
46
ns
tsu(RCVR)
th(RCVR)
Setup time, RCVR valid to RCLK rising edge
16-Mbps mode
18
ns
Hold time, RCVR valid after RCLK rising edge
16-Mbps mode
2.5
ns
tw(PXTALH)
tw(PXTALL)
2V
PXTAL
0.8 V
tw(OSC32H)
tw(OSC32L)
2V
OSC32
0.8 V
tw(RCLKH)
tw(RCLKL)
2V
RCLK
0.8 V
tsu(RCVR)
th(RCVR)
2V
RCVR
0.8 V
Figure 6. PXTAL, OSC32, RCLK, and RCVR Timing
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
13
SPWS015B − APRIL 1995 − REVISED OCTOBER 1996
MECHANICAL DATA
PAH (S-PQFP-G52)
PLASTIC QUAD FLATPACK
0,38
0,22
0,65
39
0,13 M
27
40
26
52
14
0,13 NOM
1
13
7,80 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°−ā 7°
0,75
0,45
Seating Plane
0,10
1,20 MAX
4040281 / B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
14
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated