INFINEON TLE4253GS

Data Sheet, Rev. 1.2, November 2009
TLE4253
Low Dropout Voltage Tracking Regulator
Automotive Power
Low Dropout Voltage Tracking Regulator
TLE4253
1
TLE4253GS
Overview
Features
•
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Tight output tracking tolerance to reference
Output voltage adjust down to 2.0 V
Stable with ceramic output capacitor
Flexibility of output voltage adjust higher or lower than reference,
proportional to the reference voltage
250 mA output current capability
Low dropout voltage
Combined tracking / enable input
Very low current consumption in OFF mode
PG-DSO-8 packages with lowest thermal resistance
Wide input voltage range -42 V ≤ VI ≤ 45 V
Wide temperature range: -40 °C ≤ Tj ≤ 150 °C
Output protected against short circuit to GND and battery
Overtemperature protection
Reverse polarity proof
Suitable for use in automotive electronics
Green Product (RoHS compliant)
AEC Qualified
PG-DSO-8
PG-DSO-8 exposed pad
Functional Description
The TLE4253 is a monolithic integrated low-dropout voltage tracking regulator in small PG-DSO-8 packages. The
exposed pad (EP) package variant PG-DSO-8 exposed pad offers extremely low thermal resistance. The IC is
designed to supply off-board systems, e. g. sensors in engine management systems under the severe conditions
of automotive applications. Therefore, the IC is equipped with additional protection functions against reverse
polarity and short circuit to GND and battery.
With supply voltages up to 40 V, the output voltage follows a reference voltage applied at the adjust input with high
accuracy. The reference voltage applied directly to the adjust input or by an e. g. external resistor divider can be
2.0 V at minimum.
The output is able to drive loads up to 250 mA at minimum while the device follows the e. g. 5 V output of a main
voltage regulator acting as reference with high accuracy.
The TLE4253 tracker can be set into shutdown mode in order to reduce the quiescent current to an extremly low
value. This makes the IC suitable to low power battery applications.
Type
Package
Marking
TLE4253GS
PG-DSO-8
4253
TLE4253E
PG-DSO-8 exposed pad
4253E
Data Sheet
2
Rev. 1.2, 2009-11-09
TLE4253
Block Diagram
2
Block Diagram
Saturation
Control and
Protection
circuits
Temperature
control
I
Q
-
TLE
4253
FB
+
EN/
ADJ
+
typ.
1.4V
=
GND
Figure 1
Data Sheet
Block Diagram
3
Rev. 1.2, 2009-11-09
TLE4253
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
Q
1
8
I
GND
2
7
GND
3
FB
4
TLE4253GS
Q
1
8
I
GND
n. c.
2
7
n. c.
6
GND
n. c.
3
6
GND
5
EN/ADJ
FB
4
5
EN/ADJ
Figure 2
Pin Configuration and Block Diagram
3.2
Pin Definitions and Functions
TLE4253E
Pin
Symbol
Function
1
Q
Tracker Output.
Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR
requirements given in the table “Functional Range”.
2, 3, 6, 7
GND
Ground reference (version TLE4253GS only).
Interconnect the pins on PCB. Connect to heatsink area.
6
GND
Ground (version TLE4253E only).
Connect to exposed pad.
2, 3, 7
n. c.
Not connected (version TLE4253E only).
Connect to GND externally.
4
FB
Feedback input for tracker.
Non inverting input of the internal error amplifier to control the output voltage.
Connect this pin directly to the output pin in order to obtain lower or equal output voltages
with respect to the reference voltage and connect a voltage divider for higher output
voltages than the reference (see application information).
5
EN/ADJ
Adjust / Enable.
Connect the reference to this pin. The active high signal of the reference turns on the
device, with active low the tracker is disabled. The reference voltage can be connected
directly or by a voltage divider for lower output voltages (see application information).
8
I
Input.
IC supply. For compensating line influences, a capacitor close to the IC terminals is
recommended.
–
EP
Exposed pad (version TLE4253E only).
Attach the exposed pad on package bottom to the heatsink area on circuit board.
Connect to GND.
Data Sheet
4
Rev. 1.2, 2009-11-09
TLE4253
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground (unless otherwise specified).
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
VI
VQ
VADJ/EN
VFB
-42
45
V
–
-2
45
V
–
-42
45
V
–
-42
45
V
–
Tj
Tstg
-40
150
°C
–
-50
150
°C
–
VESD,HBM
VESD,CDM
-4
4
kV
HBM2)
-1
1
kV
CDM3)
Voltages
4.1.1
Input voltage
4.1.2
Output voltage
4.1.3
Adjust / Enable Input
4.1.4
Feedback Input
Temperature
4.1.5
Junction Temperature
4.1.6
Storage Temperature
ESD Rating
4.1.7
ESD Susceptibility
4.1.8
1) Not subject to production test, specified by design.
2) ESD susceptibility Human Body Model “HBM” according to EIA/JESD 22-A 114B.
3) ESD susceptibility Charged Device Model “CDM” according to EIA/JESD22-C101 or ESDA STM5.3.1.
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
5
Rev. 1.2, 2009-11-09
TLE4253
General Product Characteristics
4.2
Pos.
Functional Range
Parameter
Symbol
4.2.1
Input Voltage
4.2.1
Adjust / Enable Input Voltage
(Voltage Tracking Range)
4.2.2
Junction Temperature
4.2.3
Output Capacitor Requirements
4.2.4
Limit Values
Unit
Conditions
Min.
Max.
VI
VADJ/EN
3.5
40
V
VI ≥ VQ + Vdr
2.0
–
V
–
Tj
CQ
ESRCQ
-40
150
°C
–
µF
–1)
Ω
–2)
10
–
5
1) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
2) relevant ESR value at f = 10 kHz.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
Thermal Resistance
Parameter
Symbol
Limit Value
Min.
Typ.
Max.
Unit
Conditions
PG-DSO-8:
4.3.1
Junction to Soldering Point
RthJSP
–
39
–
K/W
Pins 2 - 3 and 6 - 7
fixed to TA
4.3.2
Junction to Ambient
RthJA
–
150
–
K/W
Footprint only 1)
4.3.3
–
91
–
K/W
300 mm2 PCB heatsink
area 1)
4.3.4
–
81
–
K/W
600 mm2 PCB heatsink
area 1)
4.3.5
–
65
–
K/W
2s2p board2)
PG-DSO-8 exposed pad:
4.3.6
Junction to Case Bottom
RthJC
–
9
–
K/W
Measured to exposed
bottom pad
4.3.7
Junction to Ambient
RthJA
–
169
–
K/W
Footprint only 1)
4.3.8
–
64
–
K/W
300 mm2 PCB heatsink
area 1)
4.3.9
–
55
–
K/W
600 mm2 PCB heatsink
area 1)
4.3.10
–
49
–
K/W
2s2p board2)
1) Package mounted on PCB FR4; 80 x 80 x 1.5 mm; 35 µm Cu, 5 µm Sn; horizontal position; zero airflow.
Not subject to production test; specified by design.
2) Specified RthJA value is according to JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package)
was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the package contacted the first inner copper layer.
Data Sheet
6
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
5
Electrical Characteristics
5.1
Tracking Regulator
The output voltage VQ is controlled by comparing it to the voltage applied at pin ADJ/EN and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional Range”
have to be maintained. For details see also the typical performance graph “Output Capacitor Series Resistor
ESRCQ vs. Output Current IQ”. Also, the output capacitor shall be sized to buffer load transients.
An input capacitor CI is strongly recommended to buffer line influences. Connect the capacitors close to the IC
terminals.
Protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events. These
safeguards contain output current limitation, reverse polarity protection as well as thermal shutdown in case of
overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the package,
the maximum output current is decreased at high input voltages.
An overtemperature protection circuit prevents the IC from immediate destruction under fault conditions (e. g.
output continuously short-circuited to GND) by reducing the output current. A thermal balance below 200 °C
junction temperature is established. Please note that a junction temperature above 150 °C is outside the maximum
ratings and reduces the IC lifetime.
The TLE4253 allows a negative supply voltage. However, several small currents are flowing into the IC. For details
see electrical characteristics table and typical performance graph. The thermal protection circuit is not operating
during reverse polarity condition.
Table 1
Electrical Characteristics Tracking Regulator
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ; -40 °C ≤ Tj ≤ 150 °C;
all voltages with respect to ground (unless otherwise specified).
Pos.
5.1.1
5.1.2
Parameter
Output Voltage Tracking
Accuracy
∆VQ = VEN/ADJ - VQ
Symbol
∆ VQ
5.1.3
Limit Values
Unit
Test Condition
IQ = 30 mA;
VADJ/EN = 5 V
0.1 mA ≤ IQ ≤ 200 mA;
3.5 V ≤ VI ≤ 32 V
VADJ/EN = 2 V
0.1 mA ≤ IQ ≤ 250 mA;
9 V ≤ VI ≤ 32 V
VADJ/EN = 5 V
IQ = 0.1 mA to 200 mA;
VADJ/EN = 5 V
VI = 6 V to 32 V;
IQ = 10 mA
VADJ/EN = 5 V
fripple = 100 Hz;
Vripple = 1 Vpp
CQ = 10 µF, ceramic type 1)
Min.
Typ.
Max.
-5
–
5
mV
-10
–
10
mV
-15
–
15
mV
5.1.4
Load Regulation
steady-state
|dVQ,load|
–
–
10
mV
5.1.5
Line Regulation
steady-state
|dVQ,line|
–
–
10
mV
5.1.6
Power Supply Ripple
Rejection
PSRR
60
–
–
dB
Data Sheet
7
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
Table 1
Electrical Characteristics Tracking Regulator
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ; -40 °C ≤ Tj ≤ 150 °C;
all voltages with respect to ground (unless otherwise specified).
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Test Condition
5.1.7
Dropout Voltage
Vdr = VI - VQ
Vdr
–
280
600
mV
IQ = 200 mA 2)
5.1.8
Output Current Limitation
IQ,max
251
400
600
mA
5.1.9
Reverse Current
IQ
-10
-5.5
–
mA
5.1.10 Reverse Current
at Negative Input Voltage
II
-5
-2
–
mA
VQ = (VADJ - 0.1 V);
VADJ/EN = 5 V
VI = 0 V;
VQ = 16 V;
VADJ/EN = 5 V
VI = -16 V;
VQ = 0 V;
VADJ/EN = 5 V
0.1
0.5
µA
VFB = 5 V
–
200
°C
Tj increasing due to power
dissipation generated by the
IC1)
Feedback Input FB:
5.1.11 Feedback Input Biasing
Current
IFB
Overtemperature Protection:
5.1.12 Junction Temperature
Equilibrium
Tj,eq
151
1) Parameter not subject to production test; specified by design.
2) Measured when the output voltage VQ has dropped 100 mV from its nominal value.
Data Sheet
8
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
Typical Performance Characteristics Tracking Regulator
VADJ/EN = 5 V; VFB = VQ (unless otherwise noted)
Output Voltage VQ vs.
Adjust Voltage VADJ
Output Voltage VQ vs.
Input Voltage VI
VQ-VADJ.vsd
V Q [V]
VQ-VI.vsd
VI = 13.5 V
V Q [V]
Vdr
5
4
4
3
3
VADJ = 5 V
2
2
T j = 150 °C
T j = -40 °C
Tj = -40 °C
1
1
T j = 150 °C
1
2
3
1
4
5
3
7
VADJ [V]
VI [V]
Output Current Limitation IQ,max vs.
Input Voltage VI
Output Current Limitation IQ,max vs.
Output Voltage VQ
SOA.VSD
600
IQmax-VQ.vsd
VI = 13.5 V
VADJ = 5 V
I Q [mA]
5
T j = 25 °C
V Q [V]
400
T j = 125 °C
T j = 25°C
3
300
T j = 125°C
V ADJ = 5 V
200
2
1
100
0
10
20
30
0
40
VI [V]
Data Sheet
200
300
400
IQ [mA]
9
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
Typical Performance Characteristics Tracking Regulator
VADJ/EN = 5 V; VFB = VQ (unless otherwise noted)
Output Capacitor Series Resistor ESRCQ vs.
Output Current IQ
10
Output Capacitor Series Resistor ESRCQ vs.
Output Current IQ
10
ESR-IQ_10u.vsd
ESR-IQ_6u8.vsd
ESR CQ
ESR CQ
[Ω]
[Ω]
Stable
Region
1
Stable
Region
1
0.1
0.1
C Q = 10 µF
6 V < VI < 28 V
-40 °C < T j < 150 °C
0.01
0
50
100
150
C Q = 6.8 µF
6 V < VI < 28 V
-40 °C < T j < 150 °C
0.01
200
0
50
100
200
150
I Q [mA]
I Q [mA]
Line Regulation dVQ,line vs.
Input Voltage Change dVI
Power Supply
Ripple Rejection PSRR
2
PSRR.vsd
90
PSRR
∆ VQ [mV]
[dB]
IQ = 1 mA
0
60
-1
IQ = 100 mA
50
0.01
-2
VRIPPLE = 1 V
VIN = 13.5 V
C Q = 10 µF Ceramic
T j = 25 °C
0.1
1
IQ = 100 mA
-3
steady-state condition
10
0
100
0
5
10
15
20 25
30
35
∆VI [V]
f [kHz]
Data Sheet
VI,initial = 6 V
VADJ = 5 V
I Q = 10 mA
70
40
dVQ-dVI.vsd
10
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
Typical Performance Characteristics Tracking Regulator
VADJ/EN = 5 V; VFB = VQ (unless otherwise noted)
Load Regulation dVQ,line vs.
Output Current Change dIQ
Tracking Accuracy ∆VQ vs.
Junction Temperature Tj
dVQ-Tj.vsd
dVQ-dIQ.vsd
∆VQ
∆ VQ [mV]
[mV]
I Q,initial = 0 mA
VADJ = 5 V
2
0
IQ = 0.1 mA
T j = 25 °C
0
-1
IQ = 200 mA
-2
-2
Tj = 125 °C
-4
-3
steady-state condition
0
100
50
150
-40 -20
200
0
20
40
60 80 100 120 140
∆ΙQ [mA]
Line Transient Response
T j [°C]
Load Transient Response
dVI-reponse.vsd
dIQresponse.vsd
∆ VQ
[mV]
125
∆ VQ
50
[mV]
0
0
-25
I Q = 5 mA
C Q = 10 µF Ceramic
VI
VI = 13.5 V
VADJ = 5 V
CQ = 10 µF
ΙQ
[mA]
[V]
16
100
9
10
0
40
80
100
0
120
100
150
200
t [µs]
t [µs]
Data Sheet
50
11
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
Typical Performance Characteristics Tracking Regulator
VADJ/EN = 5 V; VFB = VQ (unless otherwise noted)
Dropout Voltage Vdr vs.
Output Current IQ
Dropout Voltage Vdr vs.
Junction Temperature Tj
Vdr-IQ_log.vsd
Vdr-Tj.vsd
600
V dr [mV]
V dr [mV]
1000
I Q = 200 mA
400
100
300
Tj = 150 °C
200
10
Tj = 25 °C
100
1
0.2
10
100
-40 -20
0
20
40
60
80 100 120 140
T j [°C]
IQ [mA]
Reverse Current II vs.
Input Voltage VI
Reverse Output Current IQ vs.
Output Voltage VQ
+1
+2
II-VI.vsd
I I [mA]
I Q [mA]
VQ = 0 V
VADJ = 5 V
-2
VI = 0 V
V ADJ = 5 V
-4
T j = 25 °C
-4
IQ-VQ.vsd
-8
T j = 150 °C
-6
T j = 25 °C
-12
T j = 150 °C
-8
-16
-32
-24
-16
-8
0
0
VI [V]
Data Sheet
8
16
24
32
VQ [V]
12
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
5.2
Current Consumption
Table 2
Electrical Characteristics Current Consumption
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ; -40 °C ≤ Tj ≤ 150 °C;
all voltages with respect to ground (unless otherwise specified).
Pos.
Parameter
Symbol
Min.
Typ.
Max.
5.2.1
Quiescent Current
Stand-by Mode
Iq1
–
0
Current Consumption
Iq2
–
5.2.2
Limit Values
Unit
Conditions
2
µA
120
150
µA
–
7
15
mA
–
1
3
mA
VQ = 0 V;
VADJ/EN ≤ 0.4 V;
Tj ≤ 85 °C
IQ ≤ 100 µA;
VADJ/EN = 5 V;
Tj ≤ 85 °C
IQ ≤ 200 mA;
VADJ/EN = 5 V
VADJ = VI = 5 V;
IQ = 0 mA
Iq = II - IQ
5.2.3
5.2.4
Current Consumption
Dropout Region; Iq = II - IQ
Data Sheet
Iq3
13
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
Typical Performance Characteristics Tracking Regulator
VADJ/EN = 5 V; VFB = VQ (unless otherwise noted)
Current Consumption Iq2 vs.
Junction Temperature Tj
Current Consumption Iq vs.
Output Current IQ
Iq-IQ.vsd
Iq-Tj.vsd
I q [mA]
I q [mA]
VI = 13.5V
IQ = 200 mA
10
V EN/ADJ = 5 V
10
VI = 6 V
1
1
VI > 9 V
I Q = 200 µA
0.1
0.1
0.01
-40 -20
0
20
40 60
0.01
0.2
80 100 120 140
1
10
Tj [°C]
Current Consumption Iq vs.
Input VoltageVI
30
Iq-VI.vsd
100
IQ [mA]
Quiescent Current Iq1 vs.
Junction Temperature Tj
Iq1-Tj.vsd
I q1 [µA]
25
20
VI = 13.5V
VEN/ADJ = 0 V
R LOAD = 25 Ω
I q [mA]
R LOAD = 50 Ω
R LOAD = 100 Ω
15
1
R LOAD = 500 Ω
10
5
0.1
-40 -20
0
0
10
20
30
40
20
40
60
80 100 120 140
T j [°C]
V I [V]
Data Sheet
0
14
Rev. 1.2, 2009-11-09
TLE4253
Electrical Characteristics
5.3
Adjust / Enable Input
In order to reduce the quiescent current to a minimum, the TLE4253 can be switched to stand-by mode by setting
the adjust/enable input “ADJ/EN” to “low”.
In case the pin “ADJ/EN is left open, an internal pull-down resistor keeps the voltage at the pin low and therefore
ensures that the regulator is switched off.
Table 3
Electrical Characteristics Adjust / Enable
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ; -40 °C ≤ Tj ≤ 150 °C;
all voltages with respect to ground (unless otherwise specified).
Pos.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
Typ.
Max.
5.3.1
Adjust / Enable
Low Signal Valid
VADJ/EN,low
–
–
0.4
V
–
–
V
–
3.8
5.5
µA
VQ = 0 V;
II < 2 µA;
Tj ≤ 85 °C
VQ settled:
|VQ - VADJ/EN| < 10 mV;
IQ = 10 mA
VADJ/EN = 5 V;
5.3.2
Adjust / Enable
High Signal Valid
(Tracking Region)
VADJ/EN,high
2
5.3.3
Adjust / Enable
Input Current
IADJ/EN
5.3.4
Adjust / Enable
internal pull-down resistor
RADJ/EN
1
1.5
2
MΩ
Typical Performance Characteristics Tracking Regulator
VADJ/EN = 5 V; VFB = VQ (unless otherwise noted)
Startup Sequence
4253_startup.vsd
Overshoot depends on
load current, CQ , ESR (CQ )
V [V]
4
VADJ
3
2
d VQ / dt =
( IQ,max-ILoad ) / C Q
1
0
20
40 60
80 100 120 140
t [µs]
Data Sheet
15
Rev. 1.2, 2009-11-09
TLE4253
Application Information
6
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
The application circuits shown are simplified examples. The function must be verified in the real application.
VBAT
µC, e.g. C167
Main µC supply, e.g.
TLE4271-2
I
Q
TLE4278
TLE4470
etc.
GND
VDD
I/O
VREF
5
EN/
ADJ
Q
1
TLE 4253 G
8
I
FB
4
e.g. off board
supply,
sensors
GND
2, 3, 6, 7
Figure 3
Application circuit: Output voltage VQ equal to reference voltage VREF
Figure 3 shows the typical schematic for applications where the tracker output voltage equals the reference
voltage VREF applied to the pin “EN/ADJ”. The pin “FB” is connected directly to the output. The reference voltage
is directly applied “EN/ADJ”.
Data Sheet
16
Rev. 1.2, 2009-11-09
TLE4253
Application Information
VBAT
µC, e.g. C167
Main µC supply, e.g.
TLE4271-2
I
Q
TLE4278
TLE4470
etc.
GND
VDD
I/O
VREF
R1ADJ
5
EN/
ADJ
R2ADJ
Q
1
VQ < VREF
TLE 4253 G
8
FB
I
4
GND
2, 3, 6, 7
Figure 4
Application circuit: Output voltage VQ lower than reference voltage VREF
In order to obtain a lower output voltage VQ at the tracker output than the reference voltage VREF, a voltage divider
according to Figure 4 has to be used. The output voltage VQ then calculates:
R2 ADJ
V Q = V REF ⋅  ----------------------------------------
R1 ADJ + R2 ADJ
With a given reference voltage VREF, the desired output voltage VQ and the resistor value R1ADJ, the resistor value
for R2ADJ is given by:
VQ
R2 ADJ = R1 ADJ ⋅  ---------------------------
 V REF – V Q
Taking into consideration also the effect of the internal EN/ADJ pull-down resistor, the external resistor divider’s
R2ADJ has to be selected to:
R2 ADJ ⋅ R PullDown ,min
R2 ADJ ,select =  ----------------------------------------------------------
 R PullDown ,min – R2 ADJ
Data Sheet
17
Rev. 1.2, 2009-11-09
TLE4253
Application Information
VBAT
µC, e.g. C167
Main µC supply, e.g.
TLE4271-2
I
Q
TLE4278
TLE4470
etc.
GND
VDD
I/O
VREF
5
EN/
ADJ
Q
TLE 4253 G
8
I
FB
GND
VQ > VREF
1
4
R1FB
R2FB
2, 3, 6, 7
Figure 5
Application circuit: Output voltage VQ higher than reference voltage VREF
For output voltages higher than the reference voltage, the voltage divider has to be applied between the feedback
and the output according to Figure 5. The equation for the output voltage with respect to the reference voltage is
given by:
R1 FB + R2 FB
V Q = V REF ⋅  ---------------------------------
R2 FB
Keep in mind that the input voltage has to be at minimum equal to the output voltage plus the dropout voltage of
the regulator.
With a given reference voltage VREF, the desired output voltage VQ and the resistor value R1FB, the resistor value
for R2FB is given by:
V REF
R2 FB = R1 FB ⋅  ---------------------------
V Q – V REF
Data Sheet
18
Rev. 1.2, 2009-11-09
TLE4253
Package Outlines
7
Package Outlines
2)
0.41+0.1
-0.06
0.2
M
B
A B 8x
e
0.19 +0.06
L
0.64 ±0.25
6 ±0.2
0.2
B
0.1
C
8 MAX.
1.27
4 -0.21)
1.75 MAX.
0.175 ±0.07
(1.45)
0.35 x 45˚
M
C 8x
A
HLG05506
8
5
1
4
Reflow Soldering
5 -0.2 1)
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
Dimensions:
e = 1.27
A = 5.69
L = 1.31
B = 0.65
GPS01181
Figure 6
Outline and Footprint PG-DSO-8
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Find all packages, sorts of packing and others at the Infineon Internet Page “Packages”:
Dimensions in mm
http://www.infineon.com/packages.
Data Sheet
19
Rev. 1.2, 2009-11-09
TLE4253
Package Outlines
0.35 x 45˚
1.27
0.41±0.09 2)
0.2
M
0.19 +0.06
0.08 C
Seating Plane
C A-B D 8x
0.64 ±0.25
D
0.2
6 ±0.2
8˚ MAX.
C
0.1 C D 2x
1.7 MAX.
Stand Off
(1.45)
0.1+0
-0.1
3.9 ±0.11)
M
D 8x
Bottom View
8
1
5
1
4
8
4
5
2.65 ±0.2
3 ±0.2
A
B
4.9 ±0.11)
0.1 C A-B 2x
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
3) JEDEC reference MS-012 variation BA
Figure 7
PG-DSO-8-27-PO V01
Outline and footprint PG-DSO-8 exposed pad (exposed pad)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Find all packages, sorts of packing and others at the Infineon Internet Page “Packages”:
Dimensions in mm
http://www.infineon.com/packages.
Data Sheet
20
Rev. 1.2, 2009-11-09
TLE4253
Revision History
8
Revision History
Revision Date
1.2
Changes
2009-11-09 Updated Version Data Sheet, version TLE4253E in PG-DSO-8 exposed pad and all
related description added:
In “Overview” on Page 2 picture for package PG-DSO-8 updated
In “Features” on Page 2 “package” replaced by “packages”
In “Functional Description” on Page 2 “a small PG-DSO-8 package” replaced by
“small PG-DSO-8 packages”; “The exposed pad (EP) package variant
PG-DSO-8 exposed pad offers extremely low thermal resistance.” added; “suits”
replaces by “makes”
In “Pin Assignment” on Page 4, package PG-DSO-8 exposed pad added
In “Pin Definitions and Functions” on Page 4 all definition for package
PG-DSO-8 exposed pad added
In “Thermal Resistance” on Page 6 all values for package PG-DSO-8 exposed pad
added (Item 4.3.6 - Item 4.3.10)
In “Adjust / Enable Input” on Page 15 typo corrected: “resistors” replaced by “resistor”
In “Package Outlines” on Page 19 package PG-DSO-8 exposed pad added
1.1
2008-08-19 Updated Version Final Datasheet for TLE4253GS:
“Package Outlines” on Page 19 updated;
In “Typical Performance Characteristics Tracking Regulator” on Page 14 Graph
“Current Consumption Iq vs. Input VoltageVI” on Page 14 added
1.0
2007-07-10 Initial Final Datasheet for TLE4253GS.
•
0.41
For the TLE4253ES (exposed pad) product variant, please refer to the respective
datasheet
2006-01-27 Target Datasheet
Data Sheet
21
Rev. 1.2, 2009-11-09
Edition 2009-11-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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