TI TMP320F2812PGFA

TMS320R2811, TMS320R2812
Digital Signal Processors
Data Manual
Literature Number: SPRS257
June 2004
ADVANCE INFORMATION concerns new
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Contents
Contents
Section
1
2
3
4
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Terminal Assignments for the GHH and ZHH Packages . . . . . . . . . . . . . . . . . . .
2.3.2
Pin Assignments for the PGF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Pin Assignments for the PBK Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Brief Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
C28x CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Memory Bus (Harvard Bus Architecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Real-Time JTAG and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
External Interface (XINTF) (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
M0, M1 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7
L0, L1, L2, L3, H0 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10
Peripheral Interrupt Expansion (PIE) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11
External Interrupts (XINT1, 2, 13, XNMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.14
Peripheral Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16
Peripheral Frames 0, 1, 2 (PFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer . . . . . . . . . . . . . . . . . . . . . . . .
3.2.18
32-Bit CPU-Timers (0, 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.19
Control Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.20
Serial Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
External Interface, XINTF (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
XREVISION Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2
Loss of Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4
External Reference Oscillator Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5
Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6
Low-Power Modes Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
32-Bit CPU-Timers 0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
June 2004
SPRS257
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Contents
4.2
5
6
4
Event Manager Modules (EVA, EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.1
General-Purpose (GP) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.2
Full-Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.3
Programmable Deadband Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.4
PWM Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.5
Double Update PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.6
PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.7
Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.8
Quadrature-Encoder Pulse (QEP) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.9
External ADC Start-of-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3
Enhanced Analog-to-Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4
Enhanced Controller Area Network (eCAN) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.5
Multichannel Buffered Serial Port (McBSP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.6
Serial Communications Interface (SCI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.7
Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.8
GPIO MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.1
Device and Development Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x) . . . . . . . . . . . . . . . . . . 86
6.5
Current Consumption Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.6
Reducing Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.7
Power Sequencing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.8
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.9
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.10
General Notes on Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.11
Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.12
Device Clock Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.13
Clock Requirements and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.13.1
Input Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.13.2
Output Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.14
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.15
Low-Power Mode Wakeup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.16
Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.16.1
PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.16.2
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.17
General-Purpose Input/Output (GPIO) − Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.18
General-Purpose Input/Output (GPIO) − Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.19
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.20
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.21
External Interface (XINTF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.22
XINTF Signal Alignment to XCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.23
External Interface Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.24
External Interface Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPRS257
June 2004
Contents
6.25
6.26
6.27
6.28
6.29
7
8
External Interface Ready-on-Read Timing With One External Wait State . . . . . . . . . . . . . . . . 118
External Interface Ready-on-Write Timing With One External Wait State . . . . . . . . . . . . . . . . 121
XHOLD and XHOLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
XHOLD/XHOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
On-Chip Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.29.1
ADC Absolute Maximum Ratings† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.29.2
ADC Electrical Characteristics Over Recommended
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.29.3
Current Consumption for Different ADC Configurations
(at 25-MHz ADCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.29.4
ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.29.5
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.29.6
Sequential Sampling Mode (Single-Channel) (SMODE = 0) . . . . . . . . . . . . . . . 131
6.29.7
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) . . . . . . . . . . . . . . 133
6.29.8
Definitions of Specifications and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.30
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.30.1
McBSP Transmit and Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.30.2
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Migration From F281x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.1
Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.2
Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8.3
Low-Profile Quad Flatpacks (LQFPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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Figures
List of Figures
Figure
Page
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2−3. TMS320R2811 128-Pin PBK LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3−1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3−2. R2812 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3−3. R2811 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3−4. External Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3−5. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3−6. Multiplexing of Interrupts Using the PIE Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3−7. Clock and Reset Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3−8. OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3−9. Recommended Crystal/ Clock Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3−10. Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4−1. CPU-Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4−3. Event Manager A Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4−4. Block Diagram of the R281x ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 4−5. ADC Pin Connections With Internal Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4−6. ADC Pin Connections With External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 4−7. eCAN Block Diagram and Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 4−8. eCAN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 4−9. McBSP Module With FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 4−12. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 5−1. TMS320x28x Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 6−1. R2812/R2811 Typical Current Consumption (With Peripheral Clocks Enabled) . . . . . . . . . . . . . . . . 87
Figure 6−2. Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 6−3. Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 6−4. 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 6−5. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 6−7. Power-on Reset in Microprocessor Mode (XMP/MC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 6−8. Warm Reset in Microcomputer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 6−9. Effect of Writing Into PLLCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 6−10. IDLE Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 6−11. STANDBY Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 6−12. HALT Wakeup Using XNMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 6−13. PWM Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 6−14. TDIRx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6
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Figures
Figure 6−15. EVASOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 6−16. EVBSOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 6−17. External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 6−18. General-Purpose Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 6−19. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 6−20. General-Purpose Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 6−21. SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 6−22. SPI Master External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 6−23. SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 6−25. Relationship Between XTIMCLK and SYSCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 6−26. Example Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 6−27. Example Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 6−28. Example Read With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 6−29. Example Read With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 6−30. Write With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 6−31. Write With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 6−32. External Interface Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 6−33. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . 126
Figure 6−34. ADC Analog Input Impedance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 6−35. ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 6−36. Sequential Sampling Mode (Single-Channel) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 6−37. Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 6−38. McBSP Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 6−39. McBSP Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 6−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . 138
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . 139
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . 140
Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . 141
Figure 7−1. TMS320R2812 179-Ball GHH MicroStar BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 7−2. TMS320R2812 179-Ball ZHH MicroStar BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 7−3. TMS320R2812 176-Pin PGF LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 7−4. TMS320R2811 128-Pin PBK LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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Tables
List of Tables
Table
Page
Table 2−1. Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2−2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3−1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3−2. Peripheral Frame 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−3. Peripheral Frame 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−4. Peripheral Frame 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−5. Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3−6. XINTF Configuration and Control Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−7. XREVISION Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−8. PIE Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 3−9. PIE Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 3−10. External Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 3−11. PLL, Clocking, Watchdog, and Low-Power Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 3−12. PLLCR Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 3−13. Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3−14. R281x Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 4−2. Module and Signal Names for EVA and EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 4−3. EVA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 4−4. ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 4−6. CAN Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 4−7. McBSP Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 4−8. SCI-A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 4−9. SCI-B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 4−10. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 4−11. GPIO Mux Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4−12. GPIO Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 6−2. TMS320R281x Clock Table and Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 6−3. Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 6−5. XCLKIN Timing Requirements − PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 6−6. Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 6−8. Reset (XRS) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 6−9. IDLE Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 6−10. STANDBY Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 6−11. HALT Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 6−12. PWM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−13. Timer and Capture Unit Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−14. External ADC Start-of-Conversion − EVA − Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 101
Table 6−15. External ADC Start-of-Conversion − EVB − Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 101
Table 6−16. Interrupt Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 6−17. Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 6−18. General-Purpose Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8
SPRS257
June 2004
Tables
Table 6−19. General-Purpose Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 6−20. SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 6−21. SPI Master Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 6−22. SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 6−23. SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 6−24. Relationship Between Parameters Configured in XTIMING and Duration of Pulse . . . . . . . . . . . . 112
Table 6−25. XINTF Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 6−26. External Memory Interface Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 6−27. External Memory Interface Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 6−28. External Memory Interface Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 6−29. External Memory Interface Read Switching Characteristics
(Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 6−30. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . 118
Table 6−31. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . . 118
Table 6−32. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . 118
Table 6−33. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) . . . 121
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) . . . . . . . . . . . . . . . 121
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) . . . . . . . . . . . . . . 121
Table 6−36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 6−37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . 126
Table 6−38. DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 6−39. AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 6−40. ADC Power-Up Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 6−41. Sequential Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 6−42. Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 6−43. McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 6−44. McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 6−45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . 138
Table 6−46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . 138
Table 6−47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . 139
Table 6−48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . 139
Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . 140
Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . 140
Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . 141
Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . 141
Table 6−53. Feature Comparison Between F281x and R281x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 7−1. Thermal Resistance Characteristics for 179-GHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 7−2. Thermal Resistance Characteristics for 179-ZHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 7−3. Thermal Resistance Characteristics for 176-PGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7−4. Thermal Resistance Characteristics for 128-PBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
June 2004
SPRS257
9
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10
SPRS257
June 2004
Features
Features
D High-Performance Static CMOS Technology
D
D
D
D
D
D
D
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
JTAG Boundary Scan Support†
High-Performance 32-Bit CPU
(TMS320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− Code and Pin Compatible to F2810,
F2811, and F2812 devices
− TMS320F24x/LF240x Processor Source
Code Compatible
On-Chip Memory
− 20K x 16 Total Single-Access RAM
(SARAM)
− L0 and L1: 2 Blocks of 4K x 16 Each
SARAM
− L2 and L3: 2 Blocks of 1K X 16 SARAM
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
SPI, SCI, and GPIO Boot Loader Modes to
Support Loading Code From Off-chip
Sources to On-chip RAM. SPI Boot Mode
Supports Loading From an External Serial
EEPROM.
Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
− Watchdog Timer Module
D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
D Three 32-Bit CPU-Timers
D Motor Control Peripherals
D
D
D
D
D
D
D
D
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP)
12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
Up to 56 General Purpose I/O (GPIO) Pins
Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
− JTAG Scan Controllers†
Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
Package Options
− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)
− 128-Pin LQFP Without External Memory
Interface (PBK) (2811)
Temperature Options:
− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)
− S/Q: −40°C to 125°C (GHH, ZHH, PGF,
PBK)
ADVANCE INFORMATION
1
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
† IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
June 2004
SPRS257
11
Introduction
2
Introduction
This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1
Description
The TMS320R2811 and TMS320R2812 devices, members of the TMS320C28x DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in Section 3, Functional Overview.
ADVANCE INFORMATION
Throughout this document, TMS320R2811 and TMS320R2812 are abbreviated as R2811 and R2812,
respectively.
TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12
SPRS257
June 2004
Introduction
2.2
Device Summary
Table 2−1 provides a summary of each device’s features.
R2811
R2812
Instruction Cycle (at 150 MHz)
6.67 ns
6.67 ns
Single-Access RAM (SARAM)
(16-bit word)
20K
20K
Boot ROM
Yes
Yes
—
Yes
EVA, EVB
EVA, EVB
FEATURE
External Memory Interface
Event Managers A and B
(EVA and EVB)
S
General-Purpose (GP) Timers
4
4
S
Compare (CMP)/PWM
16
16
S
Capture (CAP)/QEP Channels
6/2
6/2
Watchdog Timer
Yes
Yes
12-Bit ADC
Yes
Yes
16
16
3
3
Channels
S
32-Bit CPU Timers
SPI
Yes
Yes
SCIA, SCIB
SCIA, SCIB
CAN
Yes
Yes
McBSP
Yes
Yes
Digital I/O Pins (Shared)
56
56
3
3
SCIA, SCIB
External Interrupts
Supply Voltage
1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O
128-pin PBK
179-ball GHH
179-ball ZHH
176-pin PGF
A: −40°C to 85°C
Yes
Yes
S/Q: −40°C to 125°C
Yes
Yes
TMX
TMX
Packaging
Temperature Options†
Product
Status‡
ADVANCE INFORMATION
Table 2−1. Hardware Features†
†
The S temperature option has been replaced by the Q temperature option (40°C to 125°C) from silicon revision E onwards. Q stands for
−40°C to 125°C Q100 automotive fault grading.
‡ See Section 5.1, Device and Development Support Nomenclature for descriptions of TMS and TMX stages.
June 2004
SPRS257
13
Introduction
2.3
Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.
2.3.1
Terminal Assignments for the GHH and ZHH Packages
ADVANCE INFORMATION
See Table 2−2 for a description of each terminal’s function(s).
P
XZCS0AND1 PWM8
PWM10
VSS
VDD
CAP6
_QEPI2
XD[8]
VSS
VDD
N
SPISOMIA
PWM7
PWM9
XR/W
T4PWM
_T4CMP
C4TRIP
TEST2
VDDIO
XD[11]
XA[2]
XWE
M
SPISIMOA
XA[1]
XRD
PWM12
CAP4
_QEP3
CAP5
_QEP4
TEST1
XD[9]
X2
VSS
XA[3]
L
VDD
VSS
XD[6]
PWM11
XD[7]
C5TRIP
VDDIO
TDIRB
XD[10]
VDDIO
K
VSS
SPICLKA
XD[4]
SPISTEA
T3PWM
_T3CMP
VSS
C6TRIP
TCLKINB
X1/
XCLKIN
J
MCLKXA
MFSRA
XD[3]
VDDIO
H
VDD
MCLKRA
XD[1]
G
MDXA
MDRA
F
XMP/MC
ADCRESEXT
E
AVDDAVSSADCREFM ADCINA5 ADCXHOLD
ADCREFP
REFBG
REFBG
BGREFIN
SCIRXDB
PWM2
VSS
PWM3
PWM4
XD[12]
XHOLDA
PWM5
VDD
VSS
PWM6
XD[5]
XD[13]
T1PWM
_T1CMP
XA[4]
T2PWM
_T2CMP
VSS
MFSXA
XD[2]
CAP1
_QEP1
CAP2
_QEP2
CAP3
_QEPI1
XA[5]
T1CTRIP
_PDPINTA
XD[0]
VSS
XA[0]
T2CTRIP/
EVASOC
VDDIO
VDD
VSS
XA[6]
VSSA1
VDDA1
ADCINB7
C3TRIP XCLKOUT
XA[7]
TCLKINA
TDIRA
ADCINB3 ADCINB0 ADCINB1 ADCINA2
B
ADCINB2
1
2
SCITXDB
PWM1
C
VSSAIO
XZCS2
VDDIO
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
A
VDD
CANTXA CANRXA
D
VDDAIO
T3CTRIP T4CTRIP/
_PDPINTB EVBSOC
VSSA2
3
4
VDDIO
XA[13]
C2TRIP
XA[8]
C1TRIP
VSS
XRS
XA[18]
XINT2
_ADCSOC
XINT1
_XBIO
VSS
EMU0
TDO
TMS
XA[9]
VSS1
SCITXDA
VDD
EMU1
VSS
XA[12]
XA[10]
TDI
VDD
XA[17]
VSS
XA[15]
VDD
XD[14]
TRST
ADCLO ADCINA3 ADCINA7 XREADY
ADCINA0 ADCINA4
XNMI
_XINT13
XZCS6AND7 VSS
VDDA2
VDD1
SCIRXDA
XA[16]
XD[15]
XA[14]
XF
_XPLLDIS
TCK
TESTSEL
XA[11]
5
6
7
8
9
10
11
12
13
14
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View)
14
SPRS257
June 2004
Introduction
2.3.2
Pin Assignments for the PGF Package
XA[11]
TDI
XA[10]
V SS
V DD
TDO
TMS
XA[9]
C3TRIP
C2TRIP
C1TRIP
XA[8]
V SS
XCLKOUT
XA[7]
TCLKINA
TDIRA
T2CTRIP / EVASOC
V DDIO
V SS
V DD
XA[6]
T1CTRIP_PDPINTA
CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
V SS
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6
V DD
V SS
PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320R2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2.
See Table 2−2 for a description of each pin’s function(s).
89
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
VSS
VDD
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
88
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
133
XZCS6AND7
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XF_XPLLDIS
XA[13]
VSS
VDD
XA[14]
VDDIO
176
1
XZCS2
CANTXA
VSS
XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
VDDIO
XA[2]
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
XD[11]
XD[10]
TCLKINB
TDIRB
VSS
VDDIO
XD[9]
TEST1
TEST2
XD[8]
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
VSS
CAP4_QEP3
VDD
T4PWM_T4CMP
XD[7]
T3PWM_T3CMP
VSS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
45
V DDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
V DDA1
V SSA1
ADCRESEXT
XMP/ MC
XA[0]
V SS
MDRA
XD[0]
MDXA
V DD
XD[1]
MCLKRA
MFSXA
XD[2]
MCLKXA
MFSRA
XD[3]
V DDIO
V SS
XD[4]
SPICLKA
SPISTEA
XD[5]
V DD
V SS
XD[6]
SPISIMOA
SPISOMIA
XRD
XA[1]
XZCS0AND1
44
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View)
June 2004
SPRS257
15
ADVANCE INFORMATION
132
Introduction
2.3.3
Pin Assignments for the PBK Package
TDI
VSS
VDD
TDO
TMS
C3TRIP
C2TRIP
C1TRIP
VSS
XCLKOUT
TCLKINA
TDIRA
T2CTRIP/ EVASOC
VDDIO
VDD
T1CTRIP_PDPINTA
CAP3_QEPI1
CAP2_QEP2
CAP1_QEP1
T2PWM_T2CMP
T1PWM_T1CMP
PWM6
VDD
VSS
PWM5
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320R2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−3.
See Table 2−2 for a description of each pin’s function(s).
96
65
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
CANTXA
VDD
VSS
T4CTRIP/EVBSOC
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
TCLKINB
TDIRB
VSS
VDDIO
TEST1
TEST2
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
VDD
T4PWM_T4CMP
T3PWM_T3CMP
VSS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ADVANCE INFORMATION
64
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
97
TESTSEL
TRST
TCK
EMU0
XF_XPLLDIS
VDD
VSS
VDDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
VSS
VDD
SCITXDA
SCIRXDA
XRS
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
1
33
VDDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
VSS
MDRA
MDXA
VDD
MCLKRA
MFSXA
MCLKXA
MFSRA
VDDIO
VSS
SPICLKA
SPISTEA
VDD
VSS
SPISIMOA
SPISOMIA
32
Figure 2−3. TMS320R2811 128-Pin PBK LQFP
(Top View)
16
SPRS257
June 2004
Introduction
2.4
Signal Descriptions
Table 2−2 specifies the signals on the R281x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.
Table 2−2. Signal Descriptions†
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
XA[18]
D7
158
−
O/Z
−
XA[17]
B7
156
−
O/Z
−
XA[16]
A8
152
−
O/Z
−
XA[15]
B9
148
−
O/Z
−
XA[14]
A10
144
−
O/Z
−
XA[13]
E10
141
−
O/Z
−
XA[12]
C11
138
−
O/Z
−
XA[11]
A14
132
−
O/Z
XA[10]
C12
130
−
O/Z
−
XA[9]
D14
125
−
O/Z
−
XA[8]
E12
121
−
O/Z
−
XA[7]
F12
118
−
O/Z
−
XA[6]
G14
111
−
O/Z
−
XA[5]
H13
108
−
O/Z
−
XA[4]
J12
103
−
O/Z
−
XA[3]
M11
85
−
O/Z
−
XA[2]
N10
80
−
O/Z
−
XA[1]
M2
43
−
O/Z
−
XA[0]
G5
18
−
O/Z
19-bit
19
bit XINTF Address Bus
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
June 2004
SPRS257
17
ADVANCE INFORMATION
XINTF SIGNALS (2812 ONLY)
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
XD[15]
A9
147
−
I/O/Z
PU
XD[14]
B11
139
−
I/O/Z
PU
XD[13]
J10
97
−
I/O/Z
PU
XD[12]
L14
96
−
I/O/Z
PU
XD[11]
N9
74
−
I/O/Z
PU
XD[10]
L9
73
−
I/O/Z
PU
XD[9]
M8
68
−
I/O/Z
PU
XD[8]
P7
65
−
I/O/Z
PU
XD[7]
L5
54
−
I/O/Z
PU
XD[6]
L3
39
−
I/O/Z
PU
XD[5]
J5
36
−
I/O/Z
PU
XD[4]
K3
33
−
I/O/Z
PU
XD[3]
J3
30
−
I/O/Z
PU
XD[2]
H5
27
−
I/O/Z
PU
XD[1]
H3
24
−
I/O/Z
PU
XD[0]
G3
21
−
I/O/Z
PU
ADVANCE INFORMATION
NAME
DESCRIPTION
16 bit XINTF Data Bus
16-bit
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
18
SPRS257
June 2004
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
XMP/MC
XHOLD
F1
E7
17
159
−
−
I
I
PD
Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode. When
high, Zone 7 is enabled on the external interface. When low,
Zone 7 is disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is latched
into the XINTCNF2 register on a reset and the user can modify
this bit in software. The state of the XMP/MC pin is ignored
after reset.
PU
External Hold Request. XHOLD, when active (low), requests
the XINTF to release the external bus and place all buses and
strobes into a high-impedance state. The XINTF will release
the bus when any current access is complete and there are no
pending accesses on the XINTF.
XHOLDA
K10
82
−
O/Z
−
External Hold Acknowledge. XHOLDA is driven active (low)
when the XINTF has granted a XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state.
XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when
XHOLDA is active (low).
XZCS0AND1
P1
44
−
O/Z
−
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active
(low) when an access to the XINTF Zone 0 or Zone 1 is
performed.
XZCS2
P13
88
−
O/Z
−
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.
XZCS6AND7
B13
133
−
O/Z
−
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active
(low) when an access to the XINTF Zone 6 or Zone 7 is
performed.
XWE
N11
84
−
O/Z
−
Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
XRD
M3
42
−
O/Z
−
Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The XRD
and XWE signals are mutually exclusive.
XR/W
N4
51
−
O/Z
−
Read Not Write Strobe. Normally held high. When low, XR/W
indicates write cycle is active; when high, XR/W indicates read
cycle is active.
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
June 2004
SPRS257
19
ADVANCE INFORMATION
XINTF SIGNALS (2812 ONLY) (CONTINUED)
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
XINTF SIGNALS (2812 ONLY) (CONTINUED)
XREADY
B6
161
−
I
PU
Ready Signal. Indicates peripheral is ready to complete the
access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
ADVANCE INFORMATION
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
K9
77
58
I
Oscillator Input − input to the internal oscillator. This pin is also
used to feed an external clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
digital power supply (VDD), rather than the 3.3-V I/O supply
(VDDIO). A clamping diode may be used to clamp a buffered
clock signal to ensure that the logic-high level does not
exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
X2
M9
76
57
O
Oscillator Output
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1.
XCLKOUT
F11
119
87
O
−
TESTSEL
A13
134
97
I
PD
Test Pin. Reserved for TI. Must be connected to ground.
Device Reset (in) and Watchdog Reset (out).
XRS
D6
160
113
I/O
PU
Device reset. XRS causes the device to terminate execution.
The PC will point to the address contained at the location
0x3FFFC0. When XRS is brought to a high level, execution
begins at the location pointed to by the PC. This pin is driven
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low for the
watchdog reset duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal
pullup (100 µA, typical). It is recommended that this pin be
driven by an open-drain device.
TEST1
M7
67
51
I/O
−
This pin is a “no connect (NC)” (i.e., this pin is not connected
to any circuitry internal to the device).
TEST2
N7
66
50
I/O
−
This pin is a “no connect (NC)” (i.e., this pin is not connected
to any circuitry internal to the device).
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
20
SPRS257
June 2004
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
JTAG
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TRST
B12
135
98
I
PD
TCK
A12
136
99
I
PU
JTAG test clock with internal pullup
TMS
D13
126
92
I
PU
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising
edge of TCK.
TDI
C13
131
96
I
PU
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
TDO
D12
127
93
O/Z
−
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
EMU0
D11
137
100
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
EMU1
C9
146
105
I/O/Z
PU
Emulator pin 1. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS
ADCINA7
B5
167
119
I
ADCINA6
D5
168
120
I
ADCINA5
E5
169
121
I
ADCINA4
A4
170
122
I
ADCINA3
B4
171
123
I
ADCINA2
C4
172
124
I
ADCINA1
D4
173
125
I
ADCINA0
A3
174
126
I
8-Channel analog inputs for Sample-and-Hold A. The ADC
pins should not be driven before VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
June 2004
SPRS257
21
ADVANCE INFORMATION
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
179-PIN
GHH
AND
ZHH
176-PIN
PGF
ADCINB7
F5
9
9
I
ADCINB6
D1
8
8
I
ADCINB5
D2
7
7
I
ADCINB4
D3
6
6
I
ADCINB3
C1
5
5
I
ADCINB2
B1
4
4
I
ADCINB1
C3
3
3
I
ADCINB0
C2
2
2
I
NAME
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
ADVANCE INFORMATION
ADC ANALOG INPUT SIGNALS (CONTINUED)
ADCREFP
ADCREFM
E2
E4
11
10
8-Channel Analog Inputs for Sample-and-Hold B. The ADC
pins should not be driven before the VDDA1, VDDA2, and
VDDAIO pins have been fully powered up.
I/O
ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (2 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
10
I/O
ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (1 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
11
ADCRESEXT
F2
16
16
O
ADC External Current Bias Resistor (24.9 kΩ ±5%)
ADCBGREFIN
E6
164
116
I
Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG
E3
12
12
I
ADC Analog GND
AVDDREFBG
E1
13
13
I
ADC Analog Power (3.3-V)
ADCLO
B3
175
127
I
Common Low Side Analog Input. Connect to analog ground.
VSSA1
F3
15
15
I
ADC Analog GND
VSSA2
C5
165
117
I
ADC Analog GND
VDDA1
F4
14
14
I
ADC Analog 3.3-V Supply
VDDA2
A5
166
118
I
ADC Analog 3.3-V Supply
VSS1
C6
163
115
I
ADC Digital GND
VDD1
A6
162
114
I
ADC Digital 1.8-V (or 1.9-V) Supply
VDDAIO
B2
1
1
VSSAIO
A2
176
128
3.3-V Analog I/O Power Pin
Analog I/O Ground Pin
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
22
SPRS257
June 2004
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
H1
23
20
VDD
L1
37
29
VDD
P5
56
42
VDD
P9
75
56
VDD
P12
−
63
VDD
K12
100
74
VDD
G12
112
82
VDD
C14
128
94
VDD
B10
143
102
VDD
C8
154
110
VSS
G4
19
17
VSS
K1
32
26
VSS
L2
38
30
VSS
P4
52
39
VSS
K6
58
−
VSS
P8
70
53
VSS
M10
78
59
VSS
L11
86
62
VSS
K13
99
73
VSS
J14
105
−
VSS
G13
113
−
VSS
E14
120
88
VSS
B14
129
95
VSS
D10
142
−
VSS
C10
−
103
VSS
B8
153
109
VDDIO
J4
31
25
VDDIO
L7
64
49
VDDIO
L10
81
−
VDDIO
N14
−
−
VDDIO
G11
114
83
VDDIO
E9
145
104
VDDIO
N8
69
52
NAME
I/O/Z‡
PU/PD§
DESCRIPTION
POWER SIGNALS
1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2,
Recommended Operating Conditions,
Conditions
for voltage
requirements.
ADVANCE INFORMATION
VDD
Core and Digital I/O Ground Pins
3 3 V I/O Digital Power Pins
3.3-V
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
June 2004
SPRS257
23
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
GPIO OR PERIPHERAL SIGNALS
ADVANCE INFORMATION
GPIOA OR EVA SIGNALS
GPIOA0
PWM1 (O)
M12
92
68
I/O/Z
PU
GPIO or PWM Output Pin #1
GPIOA1
PWM2 (O)
M14
93
69
I/O/Z
PU
GPIO or PWM Output Pin #2
GPIOA2
PWM3 (O)
L12
94
70
I/O/Z
PU
GPIO or PWM Output Pin #3
GPIOA3
PWM4 (O)
L13
95
71
I/O/Z
PU
GPIO or PWM Output Pin #4
GPIOA4
PWM5 (O)
K11
98
72
I/O/Z
PU
GPIO or PWM Output Pin #5
GPIOA5
PWM6 (O)
K14
101
75
I/O/Z
PU
GPIO or PWM Output Pin #6
GPIOA6
T1PWM_T1CMP (I)
J11
102
76
I/O/Z
PU
GPIO or Timer 1 Output
GPIOA7
T2PWM_T2CMP (I)
J13
104
77
I/O/Z
PU
GPIO or Timer 2 Output
GPIOA8
CAP1_QEP1 (I)
H10
106
78
I/O/Z
PU
GPIO or Capture Input #1
GPIOA9
CAP2_QEP2 (I)
H11
107
79
I/O/Z
PU
GPIO or Capture Input #2
GPIOA10
CAP3_QEPI1 (I)
H12
109
80
I/O/Z
PU
GPIO or Capture Input #3
GPIOA11
TDIRA (I)
F14
116
85
I/O/Z
PU
GPIO or Timer Direction
GPIOA12
TCLKINA (I)
F13
117
86
I/O/Z
PU
GPIO or Timer Clock Input
GPIOA13
C1TRIP (I)
E13
122
89
I/O/Z
PU
GPIO or Compare 1 Output Trip
GPIOA14
C2TRIP (I)
E11
123
90
I/O/Z
PU
GPIO or Compare 2 Output Trip
GPIOA15
C3TRIP (I)
F10
124
91
I/O/Z
PU
GPIO or Compare 3 Output Trip
GPIOB OR EVB SIGNALS
GPIOB0
PWM7 (O)
N2
45
33
I/O/Z
PU
GPIO or PWM Output Pin #7
GPIOB1
GPIOB2
PWM8 (O)
P2
46
34
I/O/Z
PU
GPIO or PWM Output Pin #8
PWM9 (O)
N3
47
35
I/O/Z
PU
GPIO or PWM Output Pin #9
GPIOB3
PWM10 (O)
P3
48
36
I/O/Z
PU
GPIO or PWM Output Pin #10
GPIOB4
PWM11 (O)
L4
49
37
I/O/Z
PU
GPIO or PWM Output Pin #11
GPIOB5
PWM12 (O)
M4
50
38
I/O/Z
PU
GPIO or PWM Output Pin #12
GPIOB6
T3PWM_T3CMP (I)
K5
53
40
I/O/Z
PU
GPIO or Timer 3 Output
GPIOB7
T4PWM_T4CMP (I)
N5
55
41
I/O/Z
PU
GPIO or Timer 4 Output
GPIOB8
CAP4_QEP3 (I)
M5
57
43
I/O/Z
PU
GPIO or Capture Input #4
GPIOB9
CAP5_QEP4 (I)
M6
59
44
I/O/Z
PU
GPIO or Capture Input #5
GPIOB10
CAP6_QEPI2 (I)
P6
60
45
I/O/Z
PU
GPIO or Capture Input #6
GPIOB11
TDIRB (I)
L8
71
54
I/O/Z
PU
GPIO or Timer Direction
GPIOB12
TCLKINB (I)
K8
72
55
I/O/Z
PU
GPIO or Timer Clock Input
GPIOB13
C4TRIP (I)
N6
61
46
I/O/Z
PU
GPIO or Compare 4 Output Trip
GPIOB14
C5TRIP (I)
L6
62
47
I/O/Z
PU
GPIO or Compare 5 Output Trip
GPIOB15
C6TRIP (I)
K7
63
48
I/O/Z
PU
GPIO or Compare 6 Output Trip
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
24
SPRS257
June 2004
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
GPIOD OR EVA SIGNALS
GPIOD0
T1CTRIP_PDPINTA (I)
H14
110
81
I/O/Z
PU
Timer 1 Compare Output Trip
GPIOD1
T2CTRIP/EVASOC (I)
G10
115
84
I/O/Z
PU
Timer 2 Compare Output Trip or External
ADC Start-of-Conversion EV-A
GPIOD5
T3CTRIP_PDPINTB (I)
P10
79
60
I/O/Z
PU
Timer 3 Compare Output Trip
GPIOD6
T4CTRIP/EVBSOC (I)
P11
83
61
I/O/Z
PU
Timer 4 Compare Output Trip or External
ADC Start-of-Conversion EV-B
GPIOE0
XINT1_XBIO (I)
D9
149
106
I/O/Z
GPIOE1
XINT2_ADCSOC (I)
D8
151
108
GPIOE2
XNMI_XINT13 (I)
E8
150
107
GPIOD OR EVB SIGNALS
−
GPIO or XINT1 or XBIO input
I/O/Z
−
GPIO or XINT2 or ADC start of conversion
I/O/Z
PU
GPIO or XNMI or XINT13
GPIOF OR SPI SIGNALS
GPIOF0
SPISIMOA (O)
M1
40
31
I/O/Z
−
GPIO or SPI slave in, master out
GPIOF1
SPISOMIA (I)
N1
41
32
I/O/Z
−
GPIO or SPI slave out, master in
GPIOF2
SPICLKA (I/O)
K2
34
27
I/O/Z
−
GPIO or SPI clock
GPIOF3
SPISTEA (I/O)
K4
35
28
I/O/Z
−
GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIOF4
SCITXDA (O)
C7
155
111
I/O/Z
PU
GPIO or SCI asynchronous serial port TX
data
GPIOF5
SCIRXDA (I)
A7
157
112
I/O/Z
PU
GPIO or SCI asynchronous serial port RX
data
GPIOF6
CANTXA (O)
N12
GPIOF7
CANRXA (I)
N13
GPIOF OR CAN SIGNALS
87
64
I/O/Z
PU
GPIO or eCAN transmit data
89
65
I/O/Z
PU
GPIO or eCAN receive data
GPIOF OR McBSP SIGNALS
GPIOF8
MCLKXA (I/O)
J1
28
23
I/O/Z
PU
GPIO or transmit clock
GPIOF9
MCLKRA (I/O)
H2
25
21
I/O/Z
PU
GPIO or receive clock
GPIOF10
MFSXA (I/O)
H4
26
22
I/O/Z
PU
GPIO or transmit frame synch
GPIOF11
MFSRA (I/O)
J2
29
24
I/O/Z
PU
GPIO or receive frame synch
GPIOF12
MDXA (O)
G1
22
19
I/O/Z
−
GPIOF13
MDRA (I)
G2
20
18
I/O/Z
PU
GPIO or transmitted serial data
GPIO or received serial data
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
June 2004
SPRS257
25
ADVANCE INFORMATION
GPIOE OR INTERRUPT SIGNALS
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO
PERIPHERAL SIGNAL
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOF14
XF_XPLLDIS (O)
A11
140
101
I/O/Z
PU
This pin has three functions:
1. XF − General-purpose output pin.
2. XPLLDIS − This pin will be sampled
during reset to check if the PLL needs
to be disabled. The PLL will be
disabled if this pin is sensed low. HALT
and STANDBY modes cannot be used
when the PLL is disabled.
3. GPIO − GPIO function
ADVANCE INFORMATION
GPIOG OR SCI-B SIGNALS
GPIOG4
SCITXDB (O)
P14
90
66
I/O/Z
−
GPIO or SCI asynchronous serial port
transmit data
GPIOG5
SCIRXDB (I)
M13
91
67
I/O/Z
−
GPIO or SCI asynchronous serial port
receive data
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
‡
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with
the 3.3-V supply.
26
SPRS257
June 2004
Functional Overview
3
Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
Real-Time JTAG
CPU-Timer 2
TINT2
XINT13
XNMI
P
I
GPIO Pins
O
External Interrupt
Control
(XINT1/2/13, XNMI)
SCIA/SCIB
FIFO
SPI
FIFO
McBSP
FIFO
M
U
X
INT[12:1]
XRS
NMI
C28x CPU
X1/XCLKIN
X2
XF_XPLLDIS
Data(16)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
L0 SARAM
4K x 16
L2 SARAM
1K X 16
L3 SARAM
1K X 16
12-Bit ADC
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power
Modes
+
WatchDog)
Address(19)
L1 SARAM
4K x 16
eCAN
System Control
Control
INT13
EVA/EVB
16 Channels
External
Interface
(XINTF)‡
ADVANCE INFORMATION
PIE
(96 interrupts)†
TINT1
G
INT14
RS
CLKIN
H0 SARAM
8K × 16
Memory Bus
Boot ROM
4K × 16
Peripheral Bus
†
‡
45 of the possible 96 interrupts are used on the devices.
XINTF is available on the R2812 devices only.
Figure 3−1. Functional Block Diagram
June 2004
SPRS257
27
Functional Overview
3.1
Memory Map
Block
Start Address
On-Chip Memory
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
Data Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K × 16)
0x00 0800
Low 64K
(24x/240x Equivalent Data Space)
Prog Space
0x00 0000
0x00 0400
0x00 0D00
0x00 0E00
0x00 2000
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
XINTF Zone 0 (8K × 16, XZCS0AND1)
Reserved
Peripheral Frame 2
(4K × 16, Protected)
0x00 A400
Reserved
Reserved
0x00 7000
0x00 9000
Prog Space
Reserved
Peripheral Frame 1
(4K × 16, Protected)
0x00 A000
Data Space
M1 SARAM (1K × 16)
0x00 6000
0x00 8000
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
0x00 2000
0x00 4000
Reserved
Reserved
L0 SARAM (4K × 16)
L1 SARAM (4K × 16)
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
0x00 A800
XINTF Zone 2 (0.5M × 16, XZCS2)
0x08 0000
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
0x10 0000
0x18 0000
Reserved
Reserved
0x3F7FF8
High 64K
(24x/240x Equivalent
Program Space)
ADVANCE INFORMATION
External Memory XINTF
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
LEGEND:
128-bit Password (see Note H)
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x3F C000
XINTF Zone 7 (16K × 16, XZCS6AND7)
(Enabled if MP/MC = 1)
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A.
B.
C.
D.
E.
F.
G.
H.
Memory blocks are not to scale.
Reserved locations are reserved for future expansion. Application should not access these areas.
Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
“Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
The passwords are set to all ones.
Figure 3−2. R2812 Memory Map (See Notes A through H)
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SPRS257
June 2004
Functional Overview
Block
Start Address
On-Chip Memory
Data Space
0x00 0000
0x00 0040
0x00 0800
0x00 0D00
0x00 0E00
0x00 2000
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍ
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Reserved
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
Peripheral Frame 1
(4K × 16, Protected)
Peripheral Frame 2
(4K × 16, Protected)
Reserved
L0 SARAM (4K × 16,)
L1 SARAM (4K × 16)
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
0x00 A400
0x00 A800
ADVANCE INFORMATION
Low 64K
(24x/240x Equivalent Data Space)
0x00 0400
Prog Space
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
Reserved
0x3F 7FF8
High 64K
(24x/240x Equivalent
Program Space)
0x3F 8000
LEGEND:
0x3F A000
128-bit Password (see Note F)
H0 SARAM (8K × 16)
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. The passwords are set to all ones.
Figure 3−3. R2811 Memory Map (See Notes A through F)
June 2004
SPRS257
29
Functional Overview
The low 64K of the memory-address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only
execute from the “High 64K” memory area. Hence, the top 32K of H0 SARAM block can be used to run
24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7
(if MP/MC mode is high).
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones
share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample
or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
NOTE:
The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into
a single chip select (XZCS6AND7). See Section 3.5, “External Interface, XINTF (2812 only)”,
for details.
ADVANCE INFORMATION
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory
locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain
peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports
a block protection mode where a region of memory can be protected so as to make sure that operations occur
as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by
default, it will protect the selected zones.
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the
user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset
is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and
hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by
XMP/MC.
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3−1.
30
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June 2004
Functional Overview
Table 3−1. Wait States
AREA
WAIT-STATES
M0 and M1 SARAMs
0-wait
Fixed
Peripheral Frame 0
0-wait
Fixed
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Fixed
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed
L0, L1, L2, and L3 SARAMs
0-wait
H0 SARAM
0-wait
Fixed
Boot-ROM
1-wait
Fixed
XINTF
Programmable,
1-wait minimum
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
Brief Descriptions
3.2.1
C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant
software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop
not only their system control software in a high-level language, but also enables math algorithms to be
developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically
are handled by microcontroller devices. This efficiency removes the need for a second processor in many
systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x
to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive
floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical
registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.
The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables
the C28x to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
3.2.2
Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The R28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single
cycle 32-bit operations. The multiple-bus architecture, commonly termed “Harvard Bus”, enables the R28x
to fetch an instruction, read a data value, and write a data value in a single cycle. All peripherals and memories
attached to the memory bus prioritize memory accesses.
C28x and TMS320C2000 are trademarks of Texas Instruments.
June 2004
SPRS257
31
ADVANCE INFORMATION
3.2
COMMENTS
Functional Overview
Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur
on the memory bus.)
Lowest:
ADVANCE INFORMATION
3.2.3
Fetches
(Simultaneous program reads and fetches cannot occur
on the memory bus.)
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, R281x
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and
16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on R281x.
One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with
C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral
frame 1).
3.2.4
Real-Time JTAG and Analysis
R281x implements the standard IEEE 1149.1 JTAG interface. Additionally, R281x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through
non-time critical code while enabling time-critical interrupts to be serviced without interference. R281x
implements the real-time mode in hardware within the CPU. This is a unique feature to R281x, no software
monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
3.2.5
External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with
a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
3.2.6
M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on
C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both
program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The
partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer.
This makes for easier programming in high-level languages.
3.2.7
L0, L1, L2, L3, H0 SARAMs
R281x contains an additional 18K x 16 of single-access RAM (SARAM), divided into 5 blocks (4K + 4K +1K
+1K+ 8K). Each block can be independently accessed, minimizing pipeline stalls. Each block is mapped to
both program and data space.
32
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Functional Overview
3.2.8
Boot ROM
The Boot ROM is factory programmed with boot-loading software that can be used to download software from
an external interface. Boot-mode signals are provided that tell the bootloader software which boot mode to
use on power up. The Boot ROM on R281x devices is identical to that on F281x devices, except that the jump
to flash and jump to OTP modes are not available. The Boot Rom also contains standard tables such as
SIN/COS waveforms, for use in math-related algorithms.
3.2.9
Security
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE
block can support up to 96 peripheral interrupts. On R281x, 45 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt
lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block
that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.
It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled/disabled within the PIE block.
3.2.11
External Interrupts (XINT1, 2, 13, XNMI)
R281x supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked
external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected
for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time stamp the interrupt.
3.2.12 Oscillator and PLL
R281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL
is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in
software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer
to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
R281x supports a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when
a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event
managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
June 2004
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33
ADVANCE INFORMATION
R281x devices contain a non−utilizable code security module for compatibility with C281x and F281x devices.
The passwords for the security module are hard-wired in the device as all 0xFFFF. After a device reset, the
L0 and L1 SARAM blocks are in a locked condition until a dummy read of the passwords is performed. The
R281x Boot ROM performs a dummy read of the password locations. If execution after reset begins directly
in external memory on R2812 devices (i.e., MP/MC =1 ), the user should perform 8 dummy reads, one each
from address 0x3F7FF8 through 0x3F7FFF.
Functional Overview
3.2.15 Low-Power Modes
R281x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event.
HALT:
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. Only a reset or XNMI will wake the device from this
mode.
ADVANCE INFORMATION
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
R281x segregates peripherals into three sections. The mapping of peripherals is as follows:
XINTF:
External Interface Configuration Registers (2812 only)
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Timers:
CPU-Timers 0, 1, 2 Registers
PF1:
eCAN:
eCAN Mailbox and Control Registers
PF2:
SYS:
System Control Registers
GPIO:
GPIO Mux Configuration and Control Registers
PF0:
EV:
Event Manager (EVA/EVB) Control Registers
McBSP:
McBSP Control and TX/RX Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Peripheral Interface (SPI) Control and RX/TX Registers
ADC:
12-Bit ADC Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured
as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For
specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise
glitches.
3.2.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero.
The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time
OS (RTOS)/BIOS applications. CPU-Timer 2 is reserved for the DSP/BIOS real-time operating system
(DSP/BIOS RTOS), and is connected to INT14 of the CPU. CPU-Timer 1 is for general use, and is connected
to INT13 of the CPU. CPU-Timer 0 is also for general use, and is connected to the PIE block.
34
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June 2004
Functional Overview
3.2.19 Control Peripherals
R281x supports the following peripherals which are used for embedded control and communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four
two-phase motors. The event managers on R281x are compatible to the event managers
on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
3.2.20 Serial Port Peripherals
3.3
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
McBSP:
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of
the SPI. On R281x, the port supports a 16-level, receive and transmit FIFO for reducing
servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On R281x, the port supports a 16-level, receive and transmit FIFO for
reducing servicing overhead.
Register Map
R281x devices contain three peripheral register spaces. The spaces are categorized as follows:
•
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3−2.
•
Peripheral Frame 1:
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3−3.
•
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3−4.
June 2004
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ADVANCE INFORMATION
R281x supports the following serial communication peripherals:
Functional Overview
Table 3−2. Peripheral Frame 0 Registers†
ADVANCE INFORMATION
†
‡
ACCESS TYPE‡
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x00 0880
0x00 09FF
384
reserved
0x00 0A00
0x00 0B1F
288
XINTF Registers
0x00 0B20
0x00 0B3F
32
reserved
0x00 0B40
0x00 0BFF
192
CPU-TIMER0/1/2 Registers
0x00 0C00
0x00 0C3F
64
reserved
0x00 0C40
0x00 0CDF
160
PIE Registers
0x00 0CE0
0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00
0x00 0DFF
256
EALLOW protected
Reserved
0x00 0E00
0x00 0FFF
512
NAME
EALLOW protected
Not EALLOW protected
Not EALLOW protected
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
Table 3−3. Peripheral Frame 1 Registers¶
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
eCAN Registers
0x00 6000
0x00 60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN
control registers) are EALLOW-protected.
eCAN Mailbox RAM
0x00 6100
0x00 61FF
256
(128 x 32)
Not EALLOW-protected
reserved
0x00 6200
0x00 6FFF
3584
NAME
¶
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Table 3−4. Peripheral Frame 2 Registers†
ADDRESS RANGE
SIZE (x16)
reserved
0x00 7000
0x00 700F
16
System Control Registers
0x00 7010
0x00 702F
32
reserved
0x00 7030
0x00 703F
16
SPI-A Registers
0x00 7040
0x00 704F
16
NAME
†
ACCESS TYPE
EALLOW Protected
Not EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
36
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Functional Overview
Peripheral Frame 2 Registers† (Continued)
†
ADDRESS RANGE
SIZE (x16)
SCI-A Registers
0x00 7050
0x00 705F
ACCESS TYPE
16
reserved
0x00 7060
0x00 706F
16
External Interrupt Registers
0x00 7070
0x00 707F
16
reserved
0x00 7080
0x00 70BF
64
GPIO Mux Registers
0x00 70C0
0x00 70DF
32
EALLOW Protected
GPIO Data Registers
0x00 70E0
0x00 70FF
32
Not EALLOW Protected
ADC Registers
0x00 7100
0x00 711F
32
Not EALLOW Protected
reserved
0x00 7120
0x00 73FF
736
EV-A Registers
0x00 7400
0x00 743F
64
reserved
0x00 7440
0x00 74FF
192
EV-B Registers
0x00 7500
0x00 753F
64
reserved
0x00 7540
0x00 774F
528
SCI-B Registers
0x00 7750
0x00 775F
16
reserved
0x00 7760
0x00 77FF
160
McBSP Registers
0x00 7800
0x00 783F
64
reserved
0x00 7840
0x00 7FFF
1984
Not EALLOW Protected
Not EALLOW Protected
ADVANCE INFORMATION
NAME
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
3.4
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 3−5.
Table 3−5. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DEVICECNF
0x00 0880
0x00 0881
2
Device Configuration Register
reserved
0x00 0882
1
Not supported on Revision C and later silicon
DEVICEID
0x00 0883
1
Device ID Register (0x0001 − Silicon − Rev. A)
PROTSTART
0x00 0884
1
Block Protection Start Address Register
PROTRANGE
0x00 0885
1
Block Protection Range Address Register
reserved
0x00 0886
0x00 09FF
378
June 2004
DESCRIPTION
SPRS257
37
Functional Overview
3.5
External Interface, XINTF (2812 Only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812 devices.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the 2812 is mapped into five fixed zones shown in Figure 3−4.
Figure 3−4 shows the 2812 XINTF signals.
Data Space
Prog Space
0x00 0000
XD(15:0)
XA(18:0)
0x00 2000
ADVANCE INFORMATION
0x00 4000
XINTF Zone 0
(8K × 16)
XINTF Zone 1
(8K × 16)
XZCS0
XZCS1
XZCS0AND1
0x00 6000
0x08 0000
0x10 0000
XINTF Zone 2
(512K × 16)
XINTF Zone 6
(512K × 16)
XZCS2
XZCS6
XZCS6AND7
0x18 0000
0x3F C000
0x40 0000
XINTF Zone 7
(16K × 16)
(mapped here if MP/MC = 1)
XZCS7
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT (see Note E)
NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2
register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects
(XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable
glueless connection to many external memories and peripherals.
C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external memory
that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1.
D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory
that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the
MP/MC mode) then any external memory is still accessible via Zone 6 address space.
E. XCLKOUT is also pinned out on the 2810 and 2811.
Figure 3−4. External Interface Block Diagram
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June 2004
Functional Overview
The operation and timing of the external interface, can be controlled by the registers listed in Table 3−6.
Table 3−6. XINTF Configuration and Control Register Mappings
ADDRESS
SIZE (x16)
DESCRIPTION
XTIMING0
NAME
0x00 0B20
2
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register
XTIMING1
0x00 0B22
2
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register
XTIMING2
0x00 0B24
2
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register
XTIMING6
0x00 0B2C
2
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register
XTIMING7
0x00 0B2E
2
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register
XINTCNF2
0x00 0B34
2
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register
XBANK
0x00 0B38
1
XINTF Bank Control Register
XREVISION
0x00 0B3A
1
XINTF Revision Register
Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect
to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 6−25.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320F28x DSP
External Interface (XINTF) Reference Guide (literature number SPRU067).
3.5.2
XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in Table 3−7.
Table 3−7. XREVISION Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
15−0
REVISION
R
0x0004
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
June 2004
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39
ADVANCE INFORMATION
3.5.1
Functional Overview
3.6
Interrupts
Figure 3−5 shows how the various interrupt sources are multiplexed within R281x devices.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
WAKEINT
LPMINT
ADVANCE INFORMATION
PIE
96 Interrupts†
INT1 to INT12
Interrupt Control
Watchdog
Low-Power Modes
XINT1
XINT1CR(15:0)
XINT1CTR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
C28x CPU
XINT2CTR(15:0)
TINT0
TINT2
INT14
TIMER 2 (for RTOS)
TINT1
TIMER 1
MUX
INT13
GPIO
MUX
TIMER 0
select
enable
NMI
Interrupt Control
XNMI_XINT13
XNMICR(15:0)
XNMICTR(15:0)
†
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3−5. Interrupt Sources
40
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June 2004
Functional Overview
Figure 3−6 shows how the interrupts are multiplexed using the PIE block. Eight PIE block interrupts are
grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96
possible interrupts. On R281x, 45 of these are used by peripherals as shown in Table 3−8.
IFR(12:1)
INTM
IER(12:1)
INT1
INT2
1
MUX
INT11
INT12
INTx
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
Global
Enable
(Enable)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
From
Peripherals or
External
Interrupts
Figure 3−6. Multiplexing of Interrupts Using the PIE Block
Table 3−8. PIE Peripheral Interrupts†
CPU
INTERRUPTS
†
PIE INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
INT2
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
INT3
reserved
CAPINT3
(EV-A)
INT4
reserved
INT5
INTx.4
INTx.3
INTx.2
INTx.1
XINT1
reserved
PDPINTB
(EV-B)
PDPINTA
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
reserved
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
INT6
reserved
reserved
MXINT
(McBSP)
MRINT
(McBSP)
reserved
reserved
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
INT7
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ECAN0INT
(CAN)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
reserved
reserved
ECAN1INT
(CAN)
INT10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
June 2004
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41
ADVANCE INFORMATION
(Flag)
CPU
0
Functional Overview
Table 3−9. PIE Configuration and Control Registers
ADVANCE INFORMATION
NAME
ADDRESS
Size (x16)
DESCRIPTION
PIECTRL
0x0000−0CE0
1
PIE, Control Register
PIEACK
0x0000−0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0000−0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0000−0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0000−0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0000−0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0000−0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0000−0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0000−0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0000−0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0000−0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0000−0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0000−0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0000−0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0000−0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0000−0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0000−0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0000−0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0000−0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0000−0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0000−0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0000−0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0000−0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0000−0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0000−0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0000−0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0000−0CFA
0x0000−0CFF
6
Reserved
Note:
42
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
SPRS257
June 2004
Functional Overview
3.6.1
External Interrupts
Table 3−10. External Interrupt Registers
ADDRESS
SIZE (x16)
XINT1CR
0x00 7070
1
XINT1 control register
DESCRIPTION
XINT2CR
0x00 7071
1
XINT2 control register
reserved
0x00 7072
0x00 7076
5
XNMICR
0x00 7077
1
XNMI control register
XINT1CTR
0x00 7078
1
XINT1 counter register
XINT2CTR
0x00 7079
1
XINT2 counter register
reserved
0x00 707A
0x00 707E
5
XNMICTR
0x00 707F
1
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more
information, see the TMS320F28x System Control and Interrupts Reference Guide (literature number
SPRU078).
June 2004
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43
ADVANCE INFORMATION
NAME
Functional Overview
3.7
System Control
This section describes R281x oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3−7 shows the various clock and reset domains in R281x devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
C28x
CPU
X1/XCLKIN
PLL
OSC
ADVANCE INFORMATION
Power
Modes
Control
System
Control
Registers
eCAN
Peripheral Bus
Low-Speed Prescaler
I/O
LSPCLK
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
I/O
GPIO
MUX
GPIOs
HSPCLK
High-Speed Prescaler
Peripheral
Registers
XF_XPLLDIS
Clock Enables
Peripheral
Registers
Peripheral
Registers
X2
High-Speed Peripherals
EV-A/B
I/O
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3−7. Clock and Reset Domains
The PLL, clocking, watchdog and low-power modes are controlled by the registers listed in Table 3−11.
44
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Functional Overview
Table 3−11. PLL, Clocking, Watchdog, and Low-Power Mode Registers†
SIZE (x16)
reserved
0x00 7010
0x00 7017
8
reserved
0x00 7018
1
reserved
0x00 7019
1
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
LOSPCP
†
‡
DESCRIPTION
0x00 701B
1
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
PCLKCR
0x00 701C
1
Peripheral Clock Control Register
reserved
0x00 701D
1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
LPMCR1
0x00 701F
1
Low Power Mode Control Register 1
reserved
0x00 7020
1
PLLCR
0x00 7021
1
PLL Control Register‡
SCSR
0x00 7022
1
System Control & Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
reserved
0x00 7024
1
WDKEY
0x00 7025
1
reserved
0x00 7026
0x00 7028
3
WDCR
0x00 7029
1
reserved
0x00 702A
0x00 702F
6
Watchdog Reset Key Register
Watchdog Control Register
All of the above registers can only be accessed, by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not
reset PLLCR.
3.7.1
OSC and PLL Block
Figure 3−8 shows the OSC and PLL block on R281x.
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ADVANCE INFORMATION
ADDRESS
NAME
Functional Overview
XPLLDIS
Latch
XF_XPLLDIS
XRS
OSCCLK (PLL Disabled)
X1/XCLKIN
XCLKIN
0
CLKIN
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
CPU
SYSCLKOUT
1
4-Bit PLL Select
X2
PLL
ADVANCE INFORMATION
4-Bit PLL Select
PLL Block
Figure 3−8. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to R281x devices using the X1/XCLKIN and X2
pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and
the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0]
set the clocking ratio.
Table 3−12. PLLCR Register Bit Definitions
BIT(S)
NAME
TYPE
XRS RESET†
15:4
reserved
R=0
0:0
DESCRIPTION
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.
3:0
†
DIV
R/W
0,0,0,0
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.
3.7.2
Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still
issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical
frequency of 1−4 MHz. The PLLCR register should have been written to with a non-zero value for this feature
to work.
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Functional Overview
Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset
or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing
(i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the
application firmware to detect the input clock failure and initiate necessary shut-down procedure for the
system.
3.7.3
PLL-Based Clock Module
R281x has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for
the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different
CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be
re-enabled (if need be) after the PLL module has stabilized, which takes 131 072 XCLKIN cycles.
•
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
•
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the X1/XCLKIN pin.
X1/XCLKIN
Cb1
(see Note A)
X2
Crystal
X1/XCLKIN
Cb2
(see Note A)
(a)
X2
External Clock Signal
(Toggling 0 −VDD)
NC
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 3−9. Recommended Crystal / Clock Connection
Table 3−13. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module
in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
3.7.4
XCLKIN
External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
•
Fundamental mode, parallel resonant
•
CL (load capacitance) = 12 pF
•
CL1 = CL2 = 24 pF
•
Cshunt = 6 pF
•
ESR range = 25 to 40 Ω
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ADVANCE INFORMATION
The PLL-based clock module provides two modes of operation:
Functional Overview
3.7.5
Watchdog Block
The watchdog block on R281x is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter
has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog
counter. Figure 3−10 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
ADVANCE INFORMATION
Clear Counter
Internal
Pullup
WDKEY(7:0)
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
WDRST
WDINT
XRS
Core-reset
WDCR (WDCHK(2:0))
WDRST
(See Note A)
1
0
Bad
WDCHK
Key
SCSR (WDENINT)
1
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3−10. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional
is the watchdog. The Watchdog module will run off the PLL clock or the oscillator clock. The WDINT signal
is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7.6,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.7.6
Low-Power Modes Block
The low-power modes on R281x are similar to the 240x devices. Table 3−14 summarizes the various modes.
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Functional Overview
MODE
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT†
Normal
X,X
on
on
on
−
on‡
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
Debugger§
off
off
XRS,
WDINT,
XINT1,
XNMI,
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
Debugger§
off
off
XRS,
XNMI,
Debugger§
IDLE
0,0
on
on
on
STANDBY
0,1
(watchdog still running)
off
HALT
1,X
(oscillator and PLL turned off,
watchdog not functional)
†
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
‡ The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional
while on the 24x/240x the clock is turned off.
§ On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is
recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them when the IDLE instruction was executed.
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ADVANCE INFORMATION
Table 3−14. R281x Low-Power Modes
Peripherals
4
Peripherals
The integrated peripherals of R281x are described in the following subsections:
ADVANCE INFORMATION
4.1
•
Three 32-bit CPU-Timers
•
Two event-manager modules (EVA, EVB)
•
Enhanced analog-to-digital converter (ADC) module
•
Enhanced controller area network (eCAN) module
•
Multichannel buffered serial port (McBSP) module
•
Serial communications interface modules (SCI-A, SCI-B)
•
Serial peripheral interface (SPI) module
•
Digital I/O and shared pin functions
32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on R281x devices (CPU-TIMER0/1/2).
CPU-Timer 2 is reserved for the real-time OS (such as DSP/BIOS). CPU-Timer 0/1 can be used in user
applications. These timers are different from the general-purpose (GP) timers that are present in the Event
Manager modules (EVA, EVB).
NOTE: If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
SYSCLKOUT
TCR.4
(Timer Start Status)
16-Bit Prescale Counter
PSCH:PSC
Borrow
32-Bit Timer Period
PRDH:PRD
32-Bit Counter
TIMH:TIM
Borrow
TINT
Figure 4−1. CPU-Timers
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Peripherals
In R281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4−2.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
INT13
TINT1
CPU-TIMER 1
XINT13
TINT2
CPU-TIMER 2
Reserved RTOS
(DSP/BIOS)
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B)
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 4−1 are used to configure the timers. For more information, see the TMS320F28x System Control
and Interrupts Reference Guide (literature number SPRU078).
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ADVANCE INFORMATION
INT14
Peripherals
ADVANCE INFORMATION
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
SIZE (x16)
TIMER0TIM
0x00 0C00
1
CPU-Timer 0, Counter Register
TIMER0TIMH
0x00 0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x00 0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x00 0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x00 0C04
1
CPU-Timer 0, Control Register
reserved
0x00 0C05
1
TIMER0TPR
0x00 0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x00 0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x00 0C08
1
CPU-Timer 1, Counter Register
TIMER1TIMH
0x00 0C09
1
CPU-Timer 1, Counter Register High
TIMER1PRD
0x00 0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x00 0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x00 0C0C
1
CPU-Timer 1, Control Register
reserved
0x00 0C0D
1
TIMER1TPR
0x00 0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x00 0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x00 0C10
1
CPU-Timer 2, Counter Register
TIMER2TIMH
0x00 0C11
1
CPU-Timer 2, Counter Register High
TIMER2PRD
0x00 0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x00 0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x00 0C14
1
CPU-Timer 2, Control Register
reserved
0x00 0C15
1
TIMER2TPR
0x00 0C16
1
CPU-Timer 2, Prescale Register
TIMER2TPRH
0x00 0C17
1
CPU-Timer 2, Prescale Register High
reserved
0x00 0C18
0x00 0C3F
40
4.2
DESCRIPTION
Event Manager Modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,
and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 4−2 shows the module and signal names
used. Table 4−2 shows the features and functionality available for the event-manager modules and highlights
EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ. Table 4−3 lists the EVA registers. For more information, see the
TMS320F28x DSP Event Manager (EV) Reference Guide (literature number SPRU065).
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Peripherals
Table 4−2. Module and Signal Names for EVA and EVB
EVB
SIGNAL
MODULE
SIGNAL
GP Timers
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
Compare Units
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP Channels
QEP1
QEP2
QEPI1
QEP1
QEP2
QEP3
QEP4
QEPI2
QEP3
QEP4
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
Compare
C1TRIP
C2TRIP
C3TRIP
Compare
C4TRIP
C5TRIP
C6TRIP
External Clock Inputs
External Trip Inputs
External Trip Inputs
†
EVA
MODULE
T1CTRIP_PDPINTA†
T2CTRIP/EVASOC
T3CTRIP_PDPINTB†
T4CTRIP/EVBSOC
In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB.
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ADVANCE INFORMATION
EVENT MANAGER MODULES
Peripherals
ADVANCE INFORMATION
Table 4−3. EVA Registers†
NAME
ADDRESS
SIZE
(x16)
GPTCONA
0x00 7400
1
GP Timer Control Register A
DESCRIPTION
T1CNT
0x00 7401
1
GP Timer 1 Counter Register
T1CMPR
0x00 7402
1
GP Timer 1 Compare Register
T1PR
0x00 7403
1
GP Timer 1 Period Register
T1CON
0x00 7404
1
GP Timer 1 Control Register
T2CNT
0x00 7405
1
GP Timer 2 Counter Register
T2CMPR
0x00 7406
1
GP Timer 2 Compare Register
T2PR
0x00 7407
1
GP Timer 2 Period Register
T2CON
0x00 7408
1
GP Timer 2 Control Register
EXTCONA‡
0x00 7409
1
GP Extension Control Register A
COMCONA
0x00 7411
1
Compare Control Register A
ACTRA
0x00 7413
1
Compare Action Control Register A
DBTCONA
0x00 7415
1
Dead-Band Timer Control Register A
CMPR1
0x00 7417
1
Compare Register 1
CMPR2
0x00 7418
1
Compare Register 2
CMPR3
0x00 7419
1
Compare Register 3
CAPCONA
0x00 7420
1
Capture Control Register A
CAPFIFOA
0x00 7422
1
Capture FIFO Status Register A
CAP1FIFO
0x00 7423
1
Two-Level Deep Capture FIFO Stack 1
CAP2FIFO
0x00 7424
1
Two-Level Deep Capture FIFO Stack 2
CAP3FIFO
0x00 7425
1
Two-Level Deep Capture FIFO Stack 3
CAP1FBOT
0x00 7427
1
Bottom Register Of Capture FIFO Stack 1
CAP2FBOT
0x00 7428
1
Bottom Register Of Capture FIFO Stack 2
CAP3FBOT
0x00 7429
1
Bottom Register Of Capture FIFO Stack 3
EVAIMRA
0x00 742C
1
Interrupt Mask Register A
EVAIMRB
0x00 742D
1
Interrupt Mask Register B
EVAIMRC
0x00 742E
1
Interrupt Mask Register C
EVAIFRA
0x00 742F
1
Interrupt Flag Register A
EVAIFRB
0x00 7430
1
Interrupt Flag Register B
EVAIFRC
0x00 7431
1
Interrupt Flag Register C
†
The EV-B register set is identical except the address range is from 0x00−7500 to 0x00−753F. The above registers are mapped to Zone 2. This
space allows only 16-bit accesses. 32-bit accesses produce undefined results.
‡ New register compared to 24x/240x
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Peripherals
Peripheral Write Bus
TX FIFO
Interrupt
To CPU
TX FIFO _15
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX FIFO _15
—
—
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
LSPCLK
DXR2 Transmit Buffer
McBSP Registers
and Control Logic
16
DXR1 Transmit Buffer
16
CLKX
XSR2
XSR1
DX
RSR2
RSR1
DR
16
CLKR
Expand Logic
RBR2 Register
RBR1 Register
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
MRINT
RX Interrupt Logic
RX FIFO
Interrupt
To CPU
FSX
Compand Logic
16
McBSP
16
ADVANCE INFORMATION
MXINT
FSR
16
RX FIFO _15
RX FIFO _15
—
—
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4−3. Event Manager A Functional Block Diagram (See Note A)
4.2.1
General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
•
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
•
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
•
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
•
A 16-bit timer-control register,TxCON, for reads or writes
•
Selectable internal or external input clocks
June 2004
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55
Peripherals
•
A programmable prescaler for internal or external clock inputs
•
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
•
A selectable direction input pin (TDIRx) (to count up or down when directional up- / down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up / down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the
time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP
timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period
and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse
width as needed.
ADVANCE INFORMATION
4.2.2
Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
4.2.3
Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit
output signal. The output states of the deadband generator are configurable and changeable as needed by
way of the double-buffered ACTRx register.
4.2.4
PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
4.2.5
Double Update PWM Mode
The R281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM operation
mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are
independently modifiable in each PWM period. To support this mode, the compare register that determines
the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning
of a PWM period and another time in the middle of a PWM period. The compare registers in R281x Event
Managers are all buffered and support three compare value reload/update (value in buffer becoming active)
modes. These modes have earlier been documented as compare value reload conditions. The reload
condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR
Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for
compare value reload.
4.2.6
PWM Characteristics
Characteristics of the PWMs are as follows:
56
•
16-bit registers
•
Wide range of programmable deadband for the PWM output pairs
•
Change of the PWM carrier frequency for PWM frequency wobbling as needed
SPRS257
June 2004
Peripherals
•
Change of the PWM pulse widths within and after each PWM period as needed
•
External-maskable power and drive-protection interrupts
•
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
•
Minimized CPU overhead using auto-reload of the compare and period registers
•
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after
PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx
register.
•
PDPINTA pin status is reflected in bit 8 of COMCONA register.
−
PDPINTB pin status is reflected in bit 8 of COMCONB register.
EXTCON register bits provide options to individually trip control for each PWM pair of signals
Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of
three capture circuits.
•
4.2.8
Capture units include the following features:
−
One 16-bit capture control register, CAPCONx (R/W)
−
One 16-bit capture FIFO status register, CAPFIFOx
−
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
−
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
−
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet the input qualification circuitry requirements. The input pins
CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]
−
User-specified transition (rising edge, falling edge, or both edges) detection
−
Three maskable interrupt flags, one for each capture unit
−
The capture pins can also be used as general-purpose interrupt pins, if they are not used for the
capture function.
Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with
EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
4.2.9
External ADC Start-of-Conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
June 2004
SPRS257
57
ADVANCE INFORMATION
4.2.7
−
Peripherals
4.3
Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4−4. The ADC module consists
of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
•
12-bit ADC core with built-in S/H
•
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
•
Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
•
16-channel, MUXed inputs
•
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
•
Sixteen result registers (individually addressable) to store conversion values
ADVANCE INFORMATION
−
The digital value of the input analog voltage is derived by:
Digital Value + 4095
•
Input Analog Voltage * ADCLO
3
Multiple triggers as sources for the start-of-conversion (SOC) sequence
−
S/W − software immediate start
−
EVA − Event manager A (multiple event sources within EVA)
−
EVB − Event manager B (multiple event sources within EVB)
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
•
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
•
EVA and EVB triggers can operate independently in dual-sequencer mode
•
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in R281x has been enhanced to provide flexible interface to event managers A and B. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC
clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service
event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel
module. Although there are multiple input channels and two sequencers, there is only one converter in the
ADC module. Figure 4−4 shows the block diagram of the R281x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has
the choice of selecting any one of the respective eight channels available through an analog MUX. In the
cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once
the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform
oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
58
SPRS257
June 2004
Peripherals
System
Control Block
SYSCLKOUT
High-Speed
Prescaler
ADCENCLK
C28x
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
S/H
12-Bit
ADC
Module
ADCINB0
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
S/H
ADCINB7
ADC Control Registers
S/W
EVA
SOC
Sequencer 1
Sequencer 2
S/W
SOC
EVB
ADCSOC
Figure 4−4. Block Diagram of the R281x ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2 , AVDDREFBG ) from the digital
supply. Figure 4−5 shows the ADC pin connections for R281x devices.
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will
still function. This is necessary to make sure all registers and modes go into their default reset state. The
analog module will however be in a low-power inactive state. As soon as reset goes high, then the clock to
the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms
range) before the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the
CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
Figure 4−5 shows the ADC pin-biasing for internal reference and Figure 4−6 shows the ADC pin-biasing for
external reference.
June 2004
SPRS257
59
ADVANCE INFORMATION
ADCINA7
Peripherals
ADCINA[7:0]
ADCINB[7:0]
ADCLO
Test Pin ADCBGREFIN†
ADVANCE INFORMATION
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
24.9 kW§
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Analog Power
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Reference Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Analog I/O Power
VDDAIO
VSSAIO
ADC Digital Power
VDD1
VSS1
10 mF‡
10 mF‡
ADCREFP and ADCREFM should not
be loaded by external circuitry
Analog 3.3 V
Analog Ground
1.8 V can use the same 1.8 V (or 1.9 V) supply as
Digital Ground
the digital core but separate the two with a
ferrite bead or a filter
†
Provide access to this pin in PCB layouts. Intended for test purposes only.
TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent
§ 24.9-kΩ resistor is applicable for the full range of the ADC.
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
‡
Figure 4−5. ADC Pin Connections With Internal Reference (See Notes A and B)
NOTE:
The temperature rating of any recommended component must match the rating of the end
product.
60
SPRS257
June 2004
Peripherals
Test Pin
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCBGREFIN
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Input
ADCREFP
2V
ADC Reference Medium Input
ADCREFM
1V
Analog Input 0−3 V With Respect to ADCLO
Connect to Analog Ground
24.9 kW
1 mF − 10 mF
ADC Analog Power
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Reference Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Analog I/O Power
VDDAIO
VSSAIO
ADC Digital Power
VDD1
VSS1
(See
Note C)
1 mF −10 mF
ADVANCE INFORMATION
ADC 16-Channel Analog Inputs
Analog 3.3 V
Analog Ground
1.8 V Can use the same 1.8-V (or 1.9-V)
Digital Ground
supply as the digital core but separate the
two with a ferrite bead or a filter
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP−ADCREFM)
= 1 V $ 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of
external reference is critical for overall gain. The voltage ADCREFP−ADCREFM will determine the overall accuracy.
Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the
TMS320F28x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more
information.
Figure 4−6. ADC Pin Connections With External Reference
June 2004
SPRS257
61
Peripherals
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4−4.
ADVANCE INFORMATION
Table 4−4. ADC Registers†
†
62
NAME
ADDRESS
SIZE
(x16)
ADCTRL1
0x00 7100
1
ADC Control Register 1
DESCRIPTION
ADCTRL2
0x00 7101
1
ADC Control Register 2
ADCMAXCONV
0x00 7102
1
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x00 7103
1
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x00 7104
1
ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3
0x00 7105
1
ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4
0x00 7106
1
ADC Channel Select Sequencing Control Register 4
ADCASEQSR
0x00 7107
1
ADC Auto-Sequence Status Register
ADCRESULT0
0x00 7108
1
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x00 7109
1
ADC Conversion Result Buffer Register 1
ADCRESULT2
0x00 710A
1
ADC Conversion Result Buffer Register 2
ADCRESULT3
0x00 710B
1
ADC Conversion Result Buffer Register 3
ADCRESULT4
0x00 710C
1
ADC Conversion Result Buffer Register 4
ADCRESULT5
0x00 710D
1
ADC Conversion Result Buffer Register 5
ADCRESULT6
0x00 710E
1
ADC Conversion Result Buffer Register 6
ADCRESULT7
0x00 710F
1
ADC Conversion Result Buffer Register 7
ADCRESULT8
0x00 7110
1
ADC Conversion Result Buffer Register 8
ADCRESULT9
0x00 7111
1
ADC Conversion Result Buffer Register 9
ADCRESULT10
0x00 7112
1
ADC Conversion Result Buffer Register 10
ADCRESULT11
0x00 7113
1
ADC Conversion Result Buffer Register 11
ADCRESULT12
0x00 7114
1
ADC Conversion Result Buffer Register 12
ADCRESULT13
0x00 7115
1
ADC Conversion Result Buffer Register 13
ADCRESULT14
0x00 7116
1
ADC Conversion Result Buffer Register 14
ADCRESULT15
0x00 7117
1
ADC Conversion Result Buffer Register 15
ADCTRL3
0x00 7118
1
ADC Control Register 3
ADCST
0x00 7119
1
ADC Status Register
reserved
0x00 711C
0x00 711F
4
The above registers are Peripheral Frame 2 Registers.
SPRS257
June 2004
Peripherals
4.4
Enhanced Controller Area Network (eCAN) Module
•
Fully compliant with CAN protocol, version 2.0B
•
Supports data rates up to 1 Mbps
•
Thirty-two mailboxes, each with the following properties:
−
Configurable as receive or transmit
−
Configurable with standard or extended identifier
−
Has a programmable receive mask
−
Supports data and remote frame
−
Composed of 0 to 8 bytes of data
−
Uses a 32-bit time stamp on receive and transmit message
−
Protects against reception of new message
−
Holds the dynamically programmable priority of transmit message
−
Employs a programmable interrupt scheme with two interrupt levels
−
Employs a programmable alarm on transmission or reception time-out
•
Low-power mode
•
Programmable wake-up on bus activity
•
Automatic reply to a remote request message
•
Automatic retransmission of a frame in case of loss of arbitration or error
•
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
Self-test mode
−
Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details.
June 2004
SPRS257
63
ADVANCE INFORMATION
The CAN module has the following features:
Peripherals
eCAN0INT
Controls Address
eCAN1INT
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
32
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
ADVANCE INFORMATION
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4−7. eCAN Block Diagram and Interface Circuit
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs
64
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
3.3 V
Standby
Adjustable
Yes
−−
−40°C to 85°C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
−−
−40°C to 125°C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
−−
−40°C to 85°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
−−
−40°C to 125°C
SN65HVD232
3.3 V
None
None
None
−−
−40°C to 85°C
SN65HVD232Q
3.3 V
None
None
None
−−
−40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic
Loopback
−40°C to 125°C
SPRS257
June 2004
Peripherals
Table 4−5. 3.3-V eCAN Transceivers for the TMS320R281x DSPs (Continued)
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD234
3.3 V
Standby & Sleep
Adjustable
None
−−
−40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud
Loopback
−40°C to 125°C
eCAN Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
eCAN Memory (512 Bytes)
6040h
607Fh
6080h
60BFh
60C0h
60FFh
ADVANCE INFORMATION
6000h
603Fh
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Control and Status Registers
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Global Acceptance Mask − CANGAM
Master Control − CANMC
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
eCAN Memory RAM (512 Bytes)
6100h−6107h
Mailbox 0
6108h−610Fh
Mailbox 1
6110h−6117h
Mailbox 2
6118h−611Fh
Mailbox 3
6120h−6127h
Mailbox 4
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
61E0h−61E7h
Mailbox 28
61E8h−61EFh
Mailbox 29
61F0h−61F7h
Mailbox 30
61F8h−61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h−61E9h
Message Identifier − MSGID
61EAh−61EBh
Message Control − MSGCTRL
61ECh−61EDh
Message Data Low − MDL
61EEh−61EFh
Message Data High − MDH
Figure 4−8. eCAN Memory Map
June 2004
SPRS257
65
Peripherals
The CAN registers listed in Table 4−6 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
ADVANCE INFORMATION
Table 4−6. CAN Registers Map†
†
REGISTER NAME
ADDRESS
SIZE
(x32)
DESCRIPTION
CANME
0x00 6000
1
Mailbox enable
CANMD
0x00 6002
1
Mailbox direction
CANTRS
0x00 6004
1
Transmit request set
CANTRR
0x00 6006
1
Transmit request reset
CANTA
0x00 6008
1
Transmission acknowledge
CANAA
0x00 600A
1
Abort acknowledge
CANRMP
0x00 600C
1
Receive message pending
CANRML
0x00 600E
1
Receive message lost
CANRFP
0x00 6010
1
Remote frame pending
CANGAM
0x00 6012
1
Global acceptance mask
CANMC
0x00 6014
1
Master control
CANBTC
0x00 6016
1
Bit-timing configuration
CANES
0x00 6018
1
Error and status
CANTEC
0x00 601A
1
Transmit error counter
CANREC
0x00 601C
1
Receive error counter
CANGIF0
0x00 601E
1
Global interrupt flag 0
CANGIM
0x00 6020
1
Global interrupt mask
CANGIF1
0x00 6022
1
Global interrupt flag 1
CANMIM
0x00 6024
1
Mailbox interrupt mask
CANMIL
0x00 6026
1
Mailbox interrupt level
CANOPC
0x00 6028
1
Overwrite protection control
CANTIOC
0x00 602A
1
TX I/O control
CANRIOC
0x00 602C
1
RX I/O control
CANTSC
0x00 602E
1
Time stamp counter (Reserved in SCC mode)
CANTOC
0x00 6030
1
Time-out control (Reserved in SCC mode)
CANTOS
0x00 6032
1
Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1.
66
SPRS257
June 2004
Peripherals
4.5
Multichannel Buffered Serial Port (McBSP) Module
•
Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices, except the DMA features
•
Full-duplex communication
•
Double-buffered data registers which allow a continuous data stream
•
Independent framing and clocking for receive and transmit
•
External shift clock generation or an internal programmable frequency shift clock
•
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
•
8-bit data transfers with LSB or MSB first
•
Programmable polarity for both frame synchronization and data clocks
•
HIghly programmable internal clock and frame generation
•
Support A-bis mode
•
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
Works with SPI-compatible devices
•
Two 16 x 16-level FIFO for Transmit channel
•
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
•
T1/E1 framers
•
MVIP switching-compatible and ST-BUS-compliant devices including:
•
−
MVIP framers
−
H.100 framers
−
SCSA framers
−
IOM-2 compliant devices
−
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
−
IIS-compliant devices
McBSP clock rate = CLKG =
CLKSRG
, where CLKSRG source could be LSPCLK, CLKX, or CLKR.
(1 ) CLKGDIV)
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum.
Figure 4−9 shows the block diagram of the McBSP module with FIFO, interfaced to the R281x version of
Peripheral Frame 2.
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
June 2004
SPRS257
67
ADVANCE INFORMATION
The McBSP module has the following features:
Peripherals
Peripheral Write Bus
TX FIFO
Interrupt
MXINT
To CPU
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX FIFO _15
TX FIFO _15
—
—
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
ADVANCE INFORMATION
LSPCLK
DXR2 Transmit Buffer
McBSP Registers
and Control Logic
16
DXR1 Transmit Buffer
16
CLKX
XSR2
XSR1
DX
RSR2
RSR1
DR
16
CLKR
Expand Logic
RBR2 Register
RBR1 Register
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
MRINT
To CPU
RX Interrupt Logic
RX FIFO
Interrupt
FSX
Compand Logic
16
McBSP
16
FSR
16
RX FIFO _15
RX FIFO _15
—
—
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4−9. McBSP Module With FIFO
68
SPRS257
June 2004
Peripherals
Table 4−7 provides a summary of the McBSP registers.
Table 4−7. McBSP Register Summary
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
−
−
−
0x0000
McBSP Receive Buffer Register
−
−
−
0x0000
McBSP Receive Shift Register
−
−
−
0x0000
McBSP Transmit Shift Register
DRR2
00
R
0x0000
McBSP Data Receive Register 2
− Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR1
01
R
0x0000
McBSP Data Receive Register 1
− Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2
02
W
0x0000
McBSP Data Transmit Register 2
− Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1
03
W
0x0000
McBSP Data Transmit Register 1
− Write Second if the word size is greater than 16 bits,
else write to DXR1 only
ADVANCE INFORMATION
DATA REGISTERS, RECEIVE, TRANSMIT†
McBSP CONTROL REGISTERS
SPCR2
04
R/W
0x0000
McBSP Serial Port Control Register 2
SPCR1
05
R/W
0x0000
McBSP Serial Port Control Register 1
RCR2
06
R/W
0x0000
McBSP Receive Control Register 2
RCR1
07
R/W
0x0000
McBSP Receive Control Register 1
XCR2
08
R/W
0x0000
McBSP Transmit Control Register 2
XCR1
09
R/W
0x0000
McBSP Transmit Control Register 1
SRGR2
0A
R/W
0x0000
McBSP Sample Rate Generator Register 2
SRGR1
0B
R/W
0x0000
McBSP Sample Rate Generator Register 1
MCR2
0C
R/W
0x0000
McBSP Multichannel Register 2
MULTICHANNEL CONTROL REGISTERS
MCR1
0D
R/W
0x0000
McBSP Multichannel Register 1
RCERA
0E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
RCERB
0F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
XCERA
10
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
XCERB
11
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
PCR1
12
R/W
0x0000
McBSP Pin Control Register
RCERC
13
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
RCERD
14
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
XCERC
15
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
XCERD
16
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
†
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
June 2004
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69
Peripherals
Table 4−7. McBSP Register Summary (Continued)
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
RCERE
17
R/W
0x0000
McBSP Receive Channel Enable Register Partition E
RCERF
18
R/W
0x0000
McBSP Receive Channel Enable Register Partition F
XCERE
19
R/W
0x0000
McBSP Transmit Channel Enable Register Partition E
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
XCERF
1A
R/W
0x0000
McBSP Transmit Channel Enable Register Partition F
RCERG
1B
R/W
0x0000
McBSP Receive Channel Enable Register Partition G
RCERH
1C
R/W
0x0000
McBSP Receive Channel Enable Register Partition H
XCERG
1D
R/W
0x0000
McBSP Transmit Channel Enable Register Partition G
XCERH
1E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)
ADVANCE INFORMATION
FIFO Data Registers‡
DRR2
00
R
0x0000
McBSP Data Receive Register 2 − Top of receive FIFO
− Read First FIFO pointers will not advance
DRR1
01
R
0x0000
McBSP Data Receive Register 1 − Top of receive FIFO
− Read Second for FIFO pointers to advance
DXR2
02
W
0x0000
McBSP Data Transmit Register 2 − Top of transmit FIFO
− Write First FIFO pointers will not advance
DXR1
03
W
0x0000
McBSP Data Transmit Register 1 − Top of transmit FIFO
− Write Second for FIFO pointers to advance
MFFTX
20
R/W
0xA000
McBSP Transmit FIFO Register
MFFRX
21
R/W
0x201F
McBSP Receive FIFO Register
FIFO Control Registers
†
‡
MFFCT
22
R/W
0x0000
McBSP FIFO Control Register
MFFINT
23
R/W
0x0000
McBSP FIFO Interrupt Register
MFFST
24
R/W
0x0000
McBSP FIFO Status Register
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
4.6
Serial Communications Interface (SCI) Module
R281x devices include two serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
−
SCITXD: SCI transmit-output pin
−
SCIRXD: SCI receive-input pin
NOTE:
70
SPRS257
Both pins can be used as GPIO if not used for SCI.
June 2004
Peripherals
•
Baud rate programmable to 64K different rates
−
Baud rate =
=
LSPCLK , when BRR ≠ 0
(BRR ) 1) * 8
LSPCLK ,
when BRR = 0
16
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
Data-word format
−
One start bit
−
Data-word length programmable from one to eight bits
−
Optional even/odd/no parity bit
−
One or two stop bits
•
Four error-detection flags: parity, overrun, framing, and break detection
•
Two wake-up multiprocessor modes: idle-line and address bit
•
Half- or full-duplex operation
•
Double-buffered receive and transmit functions
•
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
−
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
−
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
•
Max bit rate + 150 MHz + 9.375
2 8
•
NRZ (non-return-to-zero) format
•
Ten SCI module control registers located in the control register frame beginning at address 7050h
10 6 bńs
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is
accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing
to the upper byte has no effect.
Enhanced features:
•
Auto baud-detect hardware logic
•
16-level transmit/receive FIFO
June 2004
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71
ADVANCE INFORMATION
•
Peripherals
Figure 4−10 shows the SCI module block diagram.
SCICTL1.1
Frame Format and Mode
Parity
Even/Odd Enable
SCITXD
TXSHF
Register
8
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
TXENA
TXRDY
Transmitter−Data
Buffer Register
8
TX INT ENA
SCICTL2.7
TX FIFO
Interrupts
TX FIFO _0
SCICTL2.0
TXINT
TX Interrupt
Logic
TX FIFO _1
−−−−−
TX FIFO _15
SCITXD
TX EMPTY
SCICTL2.6
To CPU
SCI TX Interrupt select logic
SCITXBUF.7−0
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 − 8
ADVANCE INFORMATION
Baud Rate
MSbyte
Register
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
Baud Rate
LSbyte
Register
RXENA
8
SCICTL1.0
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7−0
RXRDY
8
BRKDT
RX FIFO _15
−−−−−
RX FIFO_1
RX FIFO _0
SCIRXBUF.7−0
RX/BK INT ENA
SCIRXST.6
RX FIFO
Interrupts
SCIRXST.5
RX Interrupt
Logic
To CPU
RX FIFO registers
SCIRXST.7
SCIRXST.4 − 2
RX Error
FE OE PE
RXINT
RXFFOVF
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram
72
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June 2004
Peripherals
The SCI port operation is configured and controlled by the registers listed in Table 4−8 and Table 4−9.
Table 4−8. SCI-A Registers†
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRA
0x00 7050
1
SCI-A Communications Control Register
SCICTL1A
0x00 7051
1
SCI-A Control Register 1
SCIHBAUDA
0x00 7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x00 7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x00 7054
1
SCI-A Control Register 2
SCIRXSTA
0x00 7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x00 7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x00 7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x00 7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA
0x00 705A
1
SCI-A FIFO Transmit Register
SCIFFRXA
0x00 705B
1
SCI-A FIFO Receive Register
SCIFFCTA
0x00 705C
1
SCI-A FIFO Control Register
SCIPRIA
0x00 705F
1
SCI-A Priority Control Register
ADVANCE INFORMATION
†
NAME
Shaded registers are new registers for the FIFO mode.
Table 4−9. SCI-B Registers†‡
†
‡
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRB
0x00 7750
1
SCI-B Communications Control Register
SCICTL1B
0x00 7751
1
SCI-B Control Register 1
SCIHBAUDB
0x00 7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x00 7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x00 7754
1
SCI-B Control Register 2
SCIRXSTB
0x00 7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x00 7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x00 7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x00 7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB
0x00 775A
1
SCI-B FIFO Transmit Register
SCIFFRXB
0x00 775B
1
SCI-B FIFO Receive Register
SCIFFCTB
0x00 775C
1
SCI-B FIFO Control Register
SCIPRIB
0x00 775F
1
SCI-B Priority Control Register
Shaded registers are new registers for the FIFO mode.
Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
4.7
Serial Peripheral Interface (SPI) Module
R281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
June 2004
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73
Peripherals
The SPI module features include:
•
Four external pins:
−
SPISOMI: SPI slave-output/master-input pin
−
SPISIMO: SPI slave-input/master-output pin
−
SPISTE: SPI slave transmit-enable pin
−
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
Two operational modes: master and slave
•
Baud rate: 125 different programmable rates
ADVANCE INFORMATION
−
LSPCLK
, when BRR ≠ 0
(SPIBRR ) 1)
when BRR = 0, 1, 2, 3
= LSPCLK ,
4
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted
such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
Baud rate =
•
Data word length: one to sixteen data bits
•
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
−
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
−
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
−
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
−
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
•
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register
is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing
to the upper byte has no effect.
Enhanced feature:
74
•
16-level transmit/receive FIFO
•
Delayed transmit control
SPRS257
June 2004
Peripherals
The SPI port operation is configured and controlled by the registers listed in Table 4−10.
Table 4−10. SPI Registers
ADDRESS
SIZE (x16)
0x00 7040
1
SPI Configuration Control Register
DESCRIPTION
SPICTL
0x00 7041
1
SPI Operation Control Register
SPISTS
0x00 7042
1
SPI Status Register
SPIBRR
0x00 7044
1
SPI Baud Rate Register
SPIRXEMU
0x00 7046
1
SPI Receive Emulation Buffer Register
SPIRXBUF
0x00 7047
1
SPI Serial Input Buffer Register
SPITXBUF
0x00 7048
1
SPI Serial Output Buffer Register
SPIDAT
0x00 7049
1
SPI Serial Data Register
SPIFFTX
0x00 704A
1
SPI FIFO Transmit Register
SPIFFRX
0x00 704B
1
SPI FIFO Receive Register
SPIFFCT
0x00 704C
1
SPI FIFO Control Register
SPIPRI
0x00 704F
1
SPI Priority Control Register
NOTE: The registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
June 2004
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75
ADVANCE INFORMATION
NAME
SPICCR
Peripherals
Figure 4−11 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
−−−−−
SPIINT/SPIRXINT
RX FIFO Interrupt
RX FIFO _15
RX Interrupt
Logic
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
−−−−−
TX Interrupt
Logic
TX FIFO Interrupt
ADVANCE INFORMATION
TX FIFO _1
TX FIFO _0
SPITXINT
16
SPI INT FLAG
SPITXBUF
Buffer Register
16
SPI INT
ENA
SPISTS.6
SPICTL.0
16
M
M
SPIDAT
Data Register
S
SPIDAT.15 − 0
M
S
SW1
S
SPISIMO
M
S
SW2
SPISOMI
Talk
SPICTL.1
SPISTE†
State Control
Master/Slave
SPI Char
SPICCR.3 − 0
3
2
1
SW3
M
SPI Bit Rate
LSPCLK
SPIBRR.6 − 0
6
†
5
4
3
2
SPICTL.2
S
0
1
0
S
M
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
SPISTE is driven low by the master for a slave device.
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
76
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June 2004
Peripherals
4.8
GPIO MUX
The GPIO Mux registers, are used to select the operation of shared pins on R281x devices. The pins can be
individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the GPxMUX
registers). If selected for “Digital I/O” mode, registers are provided to configure the pin direction (via the
GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers).
Table 4−11 lists the GPIO Mux Registers.
Table 4−11. GPIO Mux Registers†‡§
ADDRESS
SIZE (x16)
0x00 70C0
1
GPIO A Mux Control Register
REGISTER DESCRIPTION
GPADIR
0x00 70C1
1
GPIO A Direction Control Register
GPAQUAL
0x00 70C2
1
GPIO A Input Qualification Control Register
reserved
0x00 70C3
1
GPBMUX
0x00 70C4
1
GPIO B Mux Control Register
GPBDIR
0x00 70C5
1
GPIO B Direction Control Register
GPBQUAL
0x00 70C6
1
GPIO B Input Qualification Control Register
reserved
0x00 70C7
1
reserved
0x00 70C8
1
reserved
0x00 70C9
1
reserved
0x00 70CA
1
reserved
0x00 70CB
1
GPDMUX
0x00 70CC
1
GPIO D Mux Control Register
GPDDIR
0x00 70CD
1
GPIO D Direction Control Register
GPDQUAL
0x00 70CE
1
GPIO D Input Qualification Control Register
reserved
0x00 70CF
1
GPEMUX
0x00 70D0
1
GPIO E Mux Control Register
GPEDIR
0x00 70D1
1
GPIO E Direction Control Register
GPEQUAL
0x00 70D2
1
GPIO E Input Qualification Control Register
reserved
0x00 70D3
1
GPFMUX
0x00 70D4
1
GPIO F Mux Control Register
GPFDIR
0x00 70D5
1
GPIO F Direction Control Register
reserved
0x00 70D6
1
reserved
0x00 70D7
1
GPGMUX
0x00 70D8
1
GPIO G Mux Control Register
GPGDIR
0x00 70D9
1
GPIO G Direction Control Register
reserved
0x00 70DA
1
reserved
0x00 70DB
1
reserved
0x00 70DC
0x00 70DF
4
ADVANCE INFORMATION
NAME
GPAMUX
†
Reserved locations will return undefined values and writes will be ignored.
Not all inputs will support input signal qualification.
§ These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
‡
June 2004
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77
Peripherals
If configured for digital I/O mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 4−12 lists the GPIO Data Registers. For more information, see the TMS320F28x System
Control and Interrupts Reference Guide (literature number SPRU078).
ADVANCE INFORMATION
Table 4−12. GPIO Data Registers†‡
†
‡
NAME
ADDRESS
SIZE (x16)
GPADAT
0x00 70E0
1
GPIO A Data Register
REGISTER DESCRIPTION
GPASET
0x00 70E1
1
GPIO A Set Register
GPACLEAR
0x00 70E2
1
GPIO A Clear Register
GPATOGGLE
0x00 70E3
1
GPIO A Toggle Register
GPBDAT
0x00 70E4
1
GPIO B Data Register
GPBSET
0x00 70E5
1
GPIO B Set Register
GPBCLEAR
0x00 70E6
1
GPIO B Clear Register
GPBTOGGLE
0x00 70E7
1
GPIO B Toggle Register
reserved
0x00 70E8
1
reserved
0x00 70E9
1
reserved
0x00 70EA
1
reserved
0x00 70EB
1
GPDDAT
0x00 70EC
1
GPIO D Data Register
GPDSET
0x00 70ED
1
GPIO D Set Register
GPDCLEAR
0x00 70EE
1
GPIO D Clear Register
GPDTOGGLE
0x00 70EF
1
GPIO D Toggle Register
GPEDAT
0x00 70F0
1
GPIO E Data Register
GPESET
0x00 70F1
1
GPIO E Set Register
GPECLEAR
0x00 70F2
1
GPIO E Clear Register
GPETOGGLE
0x00 70F3
1
GPIO E Toggle Register
GPFDAT
0x00 70F4
1
GPIO F Data Register
GPFSET
0x00 70F5
1
GPIO F Set Register
GPFCLEAR
0x00 70F6
1
GPIO F Clear Register
GPFTOGGLE
0x00 70F7
1
GPIO F Toggle Register
GPGDAT
0x00 70F8
1
GPIO G Data Register
GPGSET
0x00 70F9
1
GPIO G Set Register
GPGCLEAR
0x00 70FA
1
GPIO G Clear Register
GPGTOGGLE
0x00 70FB
1
GPIO G Toggle Register
reserved
0x00 70FC
0x00 70FF
4
Reserved locations will return undefined values and writes will be ignored.
These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
78
SPRS257
June 2004
Peripherals
Figure 4−12 shows how the various register bits select the various modes of operation.
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
GPxQUAL
Register
Digital I/O
GPxMUX
Register Bit
HighImpedance
Control
GPxDIR
Register Bit
0
1
MUX
1
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
XRS
Internal (Pullup or Pulldown)
PIN
NOTES: A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value
written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the
corresponding direction bit is zero (input mode).
B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period.
The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0’s or all 1’s). This feature
removes unwanted spikes from the input signal.
Figure 4−12. Modes of Operation
NOTE:
The input function of the GPIO pin and the input path to the peripheral are always enabled.
It is the output function of the GPIO pin that is multiplexed with the output path of the primary
(peripheral) function. Since the output buffer of a pin connects back to the input buffer, any
GPIO signal present at the pin will be propagated to the peripheral module as well. Therefore,
when a pin is configured for GPIO operation, the corresponding peripheral functionality (and
interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently
triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO
pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will put PWM pins in a
high-impedance state. The CxTRIP and TxCTRIP pins will also put the corresponding PWM
pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.
June 2004
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79
ADVANCE INFORMATION
0
Peripheral I/O
Development Support
5
Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of R281x-based applications:
Software Development Tools
ADVANCE INFORMATION
•
Code Composer Studio Integrated Development Environment (IDE)
−
C/C++ Compiler
−
Code generation tools
−
Assembler/Linker
−
Cycle Accurate Simulator
•
Application algorithms
•
Sample applications code
Hardware Development Tools
5.1
•
R2812 eZdsp
•
JTAG-based emulators − SPI515, XDS510PP, XDS510PP Plus, XDS510 USB
•
Universal 5-V dc power supply
•
Documentation and cables
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each [TMS320] DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320R2812GHH). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/ TMDX) through fully qualified production
devices/tools (TMS / TMDS).
TMX
Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development−support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.“
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
TMS320 is a trademark of Texas Instruments.
80
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Development Support
Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PBK) and temperature range (for example, A). Figure 5−1 provides a legend for reading
the complete device name for any TMS320x28x family member.
R
2812
PBK
A
PREFIX
TMX = experimental device
TMP = prototype device
TMS = qualified device
DEVICE FAMILY
320 = TMS320 DSP Family
TECHNOLOGY
F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O)
C = ROM (1.8-V/1.9-V Core/3.3-V I/O)
R = RAM only (1.8-V/1.9-V Core/3.3-V I/O)
†
BGA =
LQFP =
TEMPERATURE RANGE
A
S
Q
= −40°C to 85°C
= −40°C to 125°C
= −40°C to 125°C − Q100
fault grading
PACKAGE TYPE†
GHH = 179-ball MicroStar BGA
ZHH = 179-ball MicroStar BGA (lead-free)
PGF = 176-pin LQFP
PBK = 128-pin LQFP
DEVICE
2811
2812
Ball Grid Array
Low-Profile Quad Flatpack
Figure 5−1. TMS320x28x Device Nomenclature
5.2
Documentation Support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets
and data manuals, with design specifications; and hardware and software applications. Useful reference
documentation includes:
TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes the
central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital
signal processors (DSPs). It also describes emulation features available on these DSPs.
TMS320C28x Peripheral Reference Guide (literature number SPRU566) describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
TMS320F28x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060)
describes the ADC module. The module is a 12−bit pipelined ADC. The analog circuits of this converter,
referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample−and−hold
(S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits,
referred to as the wrapper in this document, include programmable conversion sequencer, result registers,
interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules.
TMS320F28x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and
features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the
device on-chip boot ROM and identifies where all of the information is located within that memory.
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TMS 320
Development Support
TMS320F28x Enhanced Controller Area Network (eCAN) Reference Guide (literature number SPRU074)
describes the eCAN that uses established protocol to communicate serially with other controllers in electrically
noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module
provides a versatile and robust serial communication interface. The eCAN module implemented in the C28x
DSP is compatible with the CAN 2.0B standard (active).
TMS320F28x Event Manager (EV) Reference Guide (literature number SPRU065) describes the EV
modules that provide a broad range of functions and features that are particularly useful in motion control and
motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units,
capture units, and quadrature-encoder pulse (QEP) circuits.
TMS320F28x External Interface (XINTF) Reference Guide (literature number SPRU067) describes the
external interface (XINTF) of the 28x digital signal processors (DSPs).
TMS320F28x Multichannel Buffered Serial Ports (McBSPs) Reference Guide (literature number
SPRU061) describes the McBSP) available on the C28x devices. The McBSPs allow direct interface between
a DSP and other devices in a system.
ADVANCE INFORMATION
TMS320F28x Serial Communication Interface (SCI) Reference Guide (literature number SPRU051)
describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules
support digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format.
TMS320F28x Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059) describes
the SPI − a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (one to sixteen bits) to be shifted into and out of the device at a programmed bit−transfer rate. The SPI
is used for communications between the DSP controller and external peripherals or another controller.
TMS320F28x System Control and Interrupts Reference Guide (literature number SPRU078) describes
the various interrupts and system control features of the 28x digital signal processors (DSPs).
3.3 V DSP for Digital Motor Control Application Report (literature number SPRA550). New generations
of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher
performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce no
additional system cost and no significant complication in interfacing with TTL and CMOS compatible
components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like 5-V based
designs, good engineering practice should be exercised to minimize noise and EMI effects by proper
component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed signal
environment, with high and low voltage analog and switching signals, such as a motor control system. In
addition, software techniques such as Random PWM method can be used by special features of the Texas
Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation.
This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control applications.
The application report first describes a scenario of a 3.3-V-only motor controller indicating that for most
applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V − 5-V
interfacing techniques are then discussed for the situations where such interfacing is needed. On-chip 3.3-V
ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are
addressed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system’s
noise and EMI effects are summarized in the last section.
The TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608) describes
the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x core.
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number
SPRU625) describes development using DSP/BIOS.
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TMS320C28x Assembly Language Tools User’s Guide (literature number SPRU513) describes the
assembly language tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x
device.
TMS320C28x Optimizing C Compiler User’s Guide (literature number SPRU514) describes the
TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces
TMS320 DSP assembly language source code for the TMS320C28x device.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
To send comments regarding this data manual, use the [email protected] email address, which is
a repository for feedback. For questions and support, contact the Product Information Center listed at the
http://www.ti.com/sc/docs/pic/home.htm site.
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Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
Electrical Specifications
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320R281x DSPs.
6.1
Absolute Maximum Ratings
ADVANCE INFORMATION
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature
ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
†
Supply voltage range, VDDIO , VDDA1, VDDA2, VDDAIO, and AVDDREFBG . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Supply voltage range, VDD, VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 2.5 V
Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO)† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating ambient temperature ranges, TA: A version (GHH, PGF, PBK)‡ . . . . . . . . . . . . . . − 40°C to 85°C
TA: S version (GHH, PGF, PBK)‡§ . . . . . . . . . . . . − 40°C to 125°C
TA: Q version (GHH, PGF, PBK)‡ . . . . . . . . . . . . . − 40°C to 125°C
Storage temperature range, Tstg† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Continuous clamp current per pin is± 2 mA
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
§ Replaced by Q temperature option from silicon revision E onwards
‡
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Electrical Specifications
Recommended Operating Conditions†
MIN
VDDIO
Device supply voltage, I/O
NOM
MAX
UNIT
3.14
3.3
3.47
1.8 V (135 MHz)
1.71
1.8
1.89
1.9 V (150 MHz)
1.81
1.9
2
VDD , VDD1
Device supply voltage,
voltage CPU
VSS
Supply ground
VDDA1 , VDDA2 ,
AVDDREFBG, VDDAIO
ADC supply voltage
fSYSCLKOUT
Device clock frequency
(system clock)
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IOH
High-level
High
level output source current,
VOH = 2.4 V
All I/Os except Group 2
IOL
Low-level
Low
level output sink current,
VOL = VOL MAX
All I/Os except Group 2
TA
Ambient
A
bi t
temperature
0
3.14
3.3
3.47
2
150
VDD = 1.8 V ± 5%
2
135
2
VDDIO
0.7VDD
VDD
All inputs except XCLKIN
All inputs except XCLKIN
0.8
XCLKIN (@ 50 µA max)
Group
Group
V
V
VDD = 1.9 V ± 5%
XCLKIN (@ 50 µA max)
V
0.3VDD
−4
2‡
−8
4
2‡
8
V
MHz
V
V
mA
mA
A version
− 40
85
S version§
− 40
125
Q version
− 40
125
°C
MAX
UNIT
°C
†
See Section 6.7 for power sequencing of VDDIO , VDDAIO , VDD , VDDA1 , VDDA2 , and AVDDREFBG .
‡ Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
§ Replaced by Q temperature option from silicon revision E onwards
6.3
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)
PARAMETER
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
¶
MIN
IOH = IOHMAX
2.4
IOH = 50 µA
TYP
V
VDDIO − 0.2
IOL = IOLMAX
VDDIO = 3.3 V,
VIN = 0 V
04
0.4
All I/Os§ (including XRS)
except EVB
−80
−140
−190
GPIOB/EVB
−13
−25
−35
V
Input
p
current
(low level)
With pullup
With pulldown
VDDIO = 3.3 V, VIN = 0 V
±2
With pullup
VDDIO = 3.3 V, VIN = VDD
±2
IIH
Input
current
(hi h level)
l
l)
(high
With pulldown¶
VDDIO = 3.3 V,
VIN = VDD
IOZ
Output current,
high-impedance state
(off-state)
Ci
Input capacitance
2
pF
Co
Output capacitance
3
pF
IIL
§
TEST CONDITIONS
28
50
VO = VDDIO or 0 V
80
±2
A
µA
µA
µ
µA
The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5.
The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.
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6.2
Electrical Specifications
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x)
ADVANCE INFORMATION
MODE
†
‡
TEST CONDITIONS
IDD
TYP
IDDA†
IDDIO
MAX‡
TYP
MAX‡
TYP
Operational
All peripheral clocks are enabled. All PWM pins
are toggled at 100 kHz.
Data is continuously transmitted out of the SCIA,
SCIB, and CAN ports. The hardware multiplier is
exercised.
Code is running out of internal SARAM.
214 mA
5 mA
40 mA
IDLE
− XCLKOUT is turned off
− All peripheral clocks
are on, except ADC
125 mA
5 mA
1 µA
STANDBY
− Peripheral clocks are
turned off
− Pins without an internal
PU/PD are tied
high/low
3 mA
5 µA
1 µA
HALT
− Peripheral clocks are
turned off
− Pins without an internal
PU/PD are tied
high/low
− Input clock is disabled
10 µA
5 µA
1 µA
MAX‡
IDDA includes current into VDDA1, VDDA2, AVDDREFBG , and VDDAIO pins.
MAX numbers are at 125°C, and max voltage (VDD = 2.0 V; VDDIO, VDDA = 3.6 V).
NOTE:
HALT and STANDBY modes cannot be used when the PLL is disabled.
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Electrical Specifications
6.5
Current Consumption Graphs
240
IDD
IDDIO
IDDA
Total
210
Current (mA)
180
150
120
90
30
0
0
5
15
30
45
60
75
90
105
120
135
150
SYSCLOCKOUT (MHz)
Figure 6−1. R2812/R2811 Typical Current Consumption (With Peripheral Clocks Enabled)
6.6
Reducing Current Consumption
28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 6−1 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals.
Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz)†
PERIPHERAL MODULE
IDD CURRENT REDUCTION (mA)
eCAN
12
EVA
6
EVB
6
ADC
8‡
SCI
4
SPI
5
McBSP
13
†
All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks
are turned on.
‡ This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the
elimination of the current drawn by the analog portion of the ADC (ICCA) as well.
6.7
Power Sequencing Requirements
Power sequencing is not required on the R281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp
together. R281x can also be used on boards that have F281x power sequencing implemented; however, if
the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least
1 V.
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60
Electrical Specifications
6.8
Signal Transition Levels
Note that some of the signals use different reference voltages, see the recommended operating conditions
table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of
0.4 V.
Figure 6−2 shows output levels.
2.4 V (VOH)
80%
20%
0.4 V (VOL)
Figure 6−2. Output Levels
ADVANCE INFORMATION
Output transition times are specified as follows:
•
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
•
For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total
voltage range and higher and the level at which the output is said to be high is 80% of the total voltage
range and higher.
Figure 6−3 shows the input levels.
2.0 V (VIH)
90%
10%
0.8 V (VIL)
Figure 6−3. Input Levels
Input transition times are specified as follows:
•
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the
total voltage range and lower.
•
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the
total voltage range and higher.
NOTE: See the individual timing diagrams for levels used for testing timing parameters.
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Electrical Specifications
6.9
Timing Parameter Symbology
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don’t care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
6.10 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this document.
6.11
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timing.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6−4. 3.3-V Test Load Circuit
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ADVANCE INFORMATION
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Electrical Specifications
6.12 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on R281x DSPs. Table 6−2 lists the cycle times of various clocks.
Table 6−2. TMS320R281x Clock Table and Nomenclature
MIN
tc(OSC) , Cycle time
On chip oscillator clock
On-chip
Frequency
tc(CI) , Cycle time
XCLKIN
tc(SCO) , Cycle time
tc(XCO) , Cycle time
ADVANCE INFORMATION
tc(HCO) , Cycle time
35
MHz
ns
4
150
MHz
6.67
500
ns
2
150
MHz
6.67
2000
ns
0.5
150
MHz
13.3‡
6.67
Frequency
LSPCLK
150
26.6‡
13.3
tc(ADCCLK) , Cycle time†
75
40
tc(SPC) , Cycle time
tc(CKG) , Cycle time
MHz
20
MHz
20
MHz
ns
50
ns
Frequency
tc(XTIM) , Cycle time
XTIMCLK
25
50
Frequency
McBSP
MHz
ns
Frequency
SPI clock
MHz
ns
37.5‡
Frequency
ADC clock
ns
75‡
tc(LCO) , Cycle time
ns
250
Frequency
HSPCLK
UNIT
50
20
Frequency
XCLKOUT
MAX
6.67
Frequency
SYSCLKOUT
NOM
28.6
6.67
ns
Frequency
150
MHz
†
The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower.
ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
‡ This is the default reset value if SYSCLKOUT = 150 MHz.
6.13 Clock Requirements and Characteristics
6.13.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6−3. Input Clock Frequency
PARAMETER
fx
Input clock frequency
fl
90
Limp mode clock frequency
SPRS257
MIN
TYP
MAX
Resonator
20
Crystal
20
35
XCLKIN
4
150
UNIT
35
2
MHz
MHz
June 2004
Electrical Specifications
Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled
NO.
C8
tc(CI)
Cycle time, XCLKIN
MIN
MAX
UNIT
6.67
250
ns
Up to 30 MHz
6
30 MHz to 150 MHz
2
Up to 30 MHz
6
30 MHz to 150 MHz
2
C9
tf(CI)
Fall time,
time XCLKIN
ns
C10
tr(CI)
C
time XCLKIN
Rise time,
C11
tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
40
60
%
C12
tw(CIH)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
60
%
MIN
MAX
UNIT
6.67
250
ns
ns
Table 6−5. XCLKIN Timing Requirements − PLL Disabled
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time,
time XCLKIN
C10
tr(CI)
Rise time,
time XCLKIN
C11
tw(CIL)
Pulse duration,
duration X1/XCLKIN low as a percentage of tc(CI)
C12
tw(CIH)
C
duration X1/XCLKIN high as a percentage of tc(CI)
Pulse duration,
C
Up to 30 MHz
6
30 MHz to 150 MHz
2
Up to 30 MHz
6
30 MHz to 150 MHz
2
XCLKIN ≤ 120 MHz
40
60
120 < XCLKIN ≤ 150 MHz
45
55
XCLKIN ≤ 120 MHz
40
60
120 < XCLKIN ≤ 150 MHz
45
55
ns
ADVANCE INFORMATION
NO.
C8
ns
%
%
Table 6−6. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module
in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
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Electrical Specifications
6.13.2 Output Clock Characteristics
Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)†‡
No.
PARAMETER
MIN
TYP
MAX
UNIT
6.67§
C1
tc(XCO)
Cycle time, XCLKOUT
C3
tf(XCO)
Fall time, XCLKOUT
ns
C4
tr(XCO)
Rise time, XCLKOUT
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H−2
H+2
ns
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H−2
H+2
ns
C7
tp
PLL lock time
131 072tc(CI)
ns
2
ns
2
ns
†
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
§ The PLL must be used for maximum frequency operation.
‡
C10
C9
ADVANCE INFORMATION
C8
XCLKIN
(see Note A)
C6
C3
C1
C4
C5
XCLKOUT
(see Note B)
NOTES: A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6−5 is
intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6−5. Clock Timing
6.14 Reset Timing
Table 6−8. Reset (XRS) Timing Requirements†
MIN
†
‡
tw(RSL1)
Pulse duration, stable XCLKIN to XRS high
tw(RSL2)
Pulse duration,
duration XRS low
tw(WDRS)
Pulse duration, reset pulse generated by watchdog
td(EX)
Delay time, address/data valid after XRS high
tOSCST‡
Oscillator start-up time
tsu(XPLLDIS)
th(XPLLDIS)
NOM
8tc(CI)
Warm reset
512tc(CI)
1
UNIT
cycles
8tc(CI)
WD-initiated reset
MAX
cycles
512tc(CI)
cycles
32tc(CI)
cycles
10
ms
Setup time for XPLLDIS pin
16tc(CI)
cycles
Hold time for XPLLDIS pin
16tc(CI)
cycles
th(XMP/MC)
Hold time for XMP/MC pin
16tc(CI)
cycles
th(boot-mode)
Hold time for boot-mode pins
2520tc(CI)§
cycles
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
92
SPRS257
June 2004
Electrical Specifications
VDDIO, VDDAn†,
VDDAIO (3.3 V)
(See Note A)
VDD, VDD1
(1.8 V (or 1.9 V))
2.5 V
0.3 V
XCLKIN
X1
XCLKIN/8 (See Note B)
XCLKOUT
User-Code Dependent
tOSCST
tw(RSL1)
ADVANCE INFORMATION
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
td(EX)
tsu(XPLLDIS)
XPLLDIS Sampling
XF/XPLLDIS
XMP/MC
See Note D
I/O Pins
User-Code Dependent
th(XPLLDIS)
(Don’t Care)
GPIOF14
th(XMP/MC)
th(boot-mode)
(see Note C)
Boot-Mode Pins
User-Code Execution Phase
(Don’t Care)
User-Code Dependent
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
NOTES: A. VDDAn − VDDA1/VDDA2 and AVDDREFBG
B. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This
explains why XCLKOUT = XCLKIN/8 during this phase.
C. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then
samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM
execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL
enabled.
D. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least
1 V and 3.3-V supply reaches 2.5 V.
Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0)
June 2004
SPRS257
93
Electrical Specifications
VDDIO, VDDAn,
VDDAIO (3.3 V)
2.5 V
VDD, VDD1 (1.8 V (or
1.9 V))
0.3 V
XCLKIN
X1
tOSCST
XCLKOUT
tw(RSL)
XRS
td(EX)
ADVANCE INFORMATION
User-Code Dependent
XCLKIN/8 (See Note A)
Address/Data/
Control
(Don’t Care)
XF/XPLLDIS
(Don’t Care)
XPLLDIS Sampling
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
th(XPLLDIS)
GPIOF14/XF (User-Code Dependent)
tsu(XPLLDIS)
XMP/MC
th(XMP/MC)
I/O Pins
(Don’t Care)
User-Code Dependent
See Note B
Input Configuration (State Depends on Internal PU/PD)
NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V..
Figure 6−7. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
94
SPRS257
June 2004
Electrical Specifications
XCLKIN
X1
XCLKIN/8
XCLKOUT
(XCLKIN * 5)
User-Code Dependent
tw(RSL2)
td(EX)
Address/Data/
Control
XF/XPLLDIS
XMP/MC
User-Code Execution
(Don’t Care)
tsu(XPLLDIS)
GPIOF14/XF
(Don’t Care)
Peripheral/GPIO Function
th(XPLLDIS)
(Don’t Care)
XPLLDIS Sampling
th(XMP/MC)
Boot-ROM Execution Starts
Boot-Mode Pins
User-Code Execution Phase
GPIO Pins as Input
GPIOF14
User-Code Dependent
(Don’t Care)
ADVANCE INFORMATION
XRS
th(boot-mode)†
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
†
After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT
Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The
BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot
modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6−8. Warm Reset in Microcomputer Mode
June 2004
SPRS257
95
Electrical Specifications
X1/XCLKIN
Write to PLLCR
SYSCLKOUT
XCLKIN*2
XCLKIN/2
XCLKIN*4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131 072 XCLKIN Cycles Long.)
(Changed CPU Frequency)
ADVANCE INFORMATION
Figure 6−9. Effect of Writing Into PLLCR Register
96
SPRS257
June 2004
Electrical Specifications
6.15 Low-Power Mode Wakeup Timing
Table 6−9 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 6−9. IDLE Mode Switching Characteristics
PARAMETER
tw(WAKE-INT)
td(WAKE-IDLE)
Pulse duration, external wake-up
signal
TEST CONDITIONS
MIN
Without input qualifier
2 * tc(SCO)
Cycles
1 * tc(SCO) + IQT†
Cycles
8 * tc(SCO)
Cycles
IQT†
Cycles
With input qualifier
TYP
MAX
UNIT
Delay time, external wake signal to
program execution resume‡
− Wake-up from SARAM
− Wake-up from SARAM
Without input qualifier
With input qualifier
8 * tc(SCO) +
†
ADVANCE INFORMATION
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)
‡ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
td(WAKE−IDLE)
A0−A15
XCLKOUT†
tw(WAKE−INT)
WAKE INT‡
†
‡
XCLKOUT = SYSCLKOUT
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6−10. IDLE Entry and Exit Timing
Table 6−10 is also the STANDBY Mode Wake-Up Timing Requirements table.
Table 6−10. STANDBY Mode Switching Characteristics
PARAMETER
td(IDLE-XCOH)
Delay time, IDLE instruction
executed to XCLKOUT high
tw(WAKE-INT)
Pulse duration, external
wake-up signal
td(WAKE-STBY)
TEST CONDITIONS
MIN
TYP
32 * tc(SCO)
Without input qualifier
With input qualifier
12 * tc(CI)
(2 +
QUALSTDBY)†
12 * tc(CI)
MAX
UNIT
Cycles
Cycles
* tc(CI)
Cycles
12 * tc(CI)
Cycles
Delay time, external wake
signal to program execution
resume‡
− Wake-up from SARAM
Without input qualifier
− Wake-up from SARAM
With input qualifier
12 * tc(CI) + tw(WAKE-INT)
Cycles
†
QUALSTDBY is a 6-bit field in the LPMCR0 register.
‡ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
June 2004
SPRS257
97
Electrical Specifications
A
C
E
B
Device
Status
STANDBY
D
F
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/XCLKIN
td(IDLE−XCOH)
ADVANCE INFORMATION
XCLKOUT†
32 SYSCLKOUT Cycles
NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32−cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake−up signal is driven active (negative edge triggered shown as an example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device will respond to the interrupt (if enabled).
Figure 6−11. STANDBY Entry and Exit Timing
Table 6−11. HALT Mode Switching Characteristics
PARAMETER
MIN
td(IDLE-XCOH)
Delay time, IDLE instruction executed to XCLKOUT high
tw(WAKE-XNMI)
Pulse duration, XNMI wakeup signal
2 * tc(CI)
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
8 * tc(CI)
tp
SPRS257
45 * tc(SCO)
MAX
UNIT
Cycles
Cycles
Cycles
131 072 * tc(CI) Cycles
PLL lock-up time
td(wake)
98
32 * tc(SCO)
TYP
Delay time, PLL lock to program execution resume
− Wake-up from SARAM
35*tc(SCO)
Cycles
June 2004
Electrical Specifications
A
C
E
B
Device
Status
D
HALT
Flushing Pipeline
G
F
HALT
PLL Lock−up Time
Wake−up Latency
Normal
Execution
XNMI
tw(WAKE−XNMI)
tp
td(INT)
X1/XCLKIN
td(IDLE−XCOH)
Oscillator Start-up Time
32 SYSCLKOUT Cycles
† XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
Figure 6−12. HALT Wakeup Using XNMI
June 2004
SPRS257
99
ADVANCE INFORMATION
XCLKOUT†
Electrical Specifications
6.16 Event Manager Interface
6.16.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 6−12. PWM Switching Characteristics†‡
PARAMETER
TEST CONDITIONS
tw(PWM)§
Pulse duration, PWMx output high/low
td(PWM)XCO
Delay time, XCLKOUT high to PWMx output switching
MIN
MAX
25
XCLKOUT = SYSCLKOUT/4
UNIT
ns
10
ns
†
See the GPIO output timing for fall/rise times for PWM pins.
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
§ PWM outputs may be 100%, 0%, or increments of t
c(HCO) with respect to the PWM period.
‡
Table 6−13. Timer and Capture Unit Timing Requirements¶#
ADVANCE INFORMATION
MIN
Without input qualifier
MAX
2 * tc(SCO)
UNIT
tw(TDIR)
Pulse duration
duration, TDIRx low/high
tw(CAP)
Pulse duration,
duration CAPx input low/high
tw(TCLKINL)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
40
60
%
tw(TCLKINH)
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
40
60
%
tc(TCLKIN)
Cycle time, TCLKINx
With input qualifier
Without input qualifier
With input qualifier
cycles
1 * tc(SCO) + IQT||
2 * tc(SCO)
cycles
1 * tc(SCO) + IQT||
4 * tc(HCO)
ns
¶
The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is
2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling
period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples will be taken over five sampling
windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles.
However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
# Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
|| Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
XCLKOUT†
td(PWM)XCO
tw(PWM)
PWMx
†
XCLKOUT = SYSCLKOUT
Figure 6−13. PWM Output Timing
XCLKOUT†
tw(TDIR)
TDIRx
†
XCLKOUT = SYSCLKOUT
Figure 6−14. TDIRx Timing
100
SPRS257
June 2004
Electrical Specifications
Table 6−14. External ADC Start-of-Conversion − EVA − Switching Characteristics†
MIN
PARAMETER
td(XCOH-EVASOCL)
tw(EVASOCL)
†
Delay time, XCLKOUT high to EVASOC low
MAX
UNIT
1 * tc(SCO)
cycle
32 * tc(HCO)
Pulse duration, EVASOC low
ns
XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVASOCL)
tw(EVASOCL)
EVASOC
Table 6−15. External ADC Start-of-Conversion − EVB − Switching Characteristics†
MIN
PARAMETER
†
td(XCOH-EVBSOCL)
Delay time, XCLKOUT high to EVBSOC low
tw(EVBSOCL)
Pulse duration, EVBSOC low
MAX
UNIT
1 * tc(SCO)
cycle
32 * tc(HCO)
ns
XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVBSOCL)
tw(EVBSOCL)
EVBSOC
Figure 6−16. EVBSOC Timing
June 2004
SPRS257
101
ADVANCE INFORMATION
Figure 6−15. EVASOC Timing
Electrical Specifications
6.16.2 Interrupt Timing
Table 6−16. Interrupt Switching Characteristics
PARAMETER
td(PDP-PWM)HZ
td(TRIP-PWM)HZ
td(INT)
†
MIN
Without input
Delay time, PDPINTx low to PWM qualifier
high impedance state
high-impedance
With input qualifier
Delay time, CxTRIP/TxCTRIP
signals low to PWM
high-impedance state
UNIT
12
ns
1 * tc(SCO) + IQT + 12†
Without input
qualifier
3 * tc(SCO)
ns
[2 * tc(SCO)] + IQT†
With input qualifier
Delay time, INT low/high to interrupt-vector fetch
MAX
tqual + 12tc(XCO)
ns
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)
Table 6−17. Interrupt Timing Requirements
ADVANCE INFORMATION
MIN
†
tw(INT)
Pulse duration
duration, INT input low/high
tw(PDP)
duration PDPINTx input low
Pulse duration,
tw(CxTRIP)
Pulse duration,
duration CxTRIP input low
tw(TxCTRIP)
Pulse duration,
duration TxCTRIP input low
with no qualifier
with qualifier
with no qualifier
with qualifier
with no qualifier
with qualifier
with no qualifier
with qualifier
2 * tc(SCO)
1 * tc(SCO) + IQT†
2 * tc(SCO)
1 * tc(SCO) + IQT†
2 * tc(SCO)
1 * tc(SCO) + IQT†
2 * tc(SCO)
1 * tc(SCO) + IQT†
MAX
UNIT
cycles
cycles
cycles
cycles
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)
102
SPRS257
June 2004
Electrical Specifications
XCLKOUT†
tw(PDP), tw(CxTRIP), tw(TxCTRIP)
TxCTRIP, CxTRIP,
PDPINTx‡
td(PDP-PWM)HZ , td(TRIP-PWM)HZ
PWM§
tw(INT)
td(INT)
Interrupt Vector
A0−A15
†
XCLKOUT = SYSCLKOUT
TxCTRIP − T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP
CxTRIP − C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP
PDPINTx − PDPINTA or PDPINTB
§ PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin). The
state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
‡
Figure 6−17. External Interrupt Timing
6.17 General-Purpose Input/Output (GPIO) − Output Timing
Table 6−18. General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
UNIT
cycle
td(XCOH-GPO)
Delay time
time, XCLKOUT high to GPIO low/high
All GPIOs
1 * tc(SCO)
tr(GPO)
Rise time, GPIO switching low to high
All GPIOs
10
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
10
ns
fGPO
Toggling frequency, GPO pins
20
MHz
ns
XCLKOUT
td(XCOH-GPO)
GPIO
tf(GPO)
tr(GPO)
Figure 6−18. General-Purpose Output Timing
June 2004
SPRS257
103
ADVANCE INFORMATION
XNMI, XINT1, XINT2
Electrical Specifications
6.18 General-Purpose Input/Output (GPIO) − Input Timing
See Note A
GPIO
Signal
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
QUALPRD
Sampling Window
SYSCLKOUT
ADVANCE INFORMATION
QUALPRD = 1
(2 x SYSCLKOUT cycles) x 5
Output From
Qualifier
NOTES: A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary
from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value “n”, the qualification sampling
period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin will be sampled). Six consecutive samples
must be of the same value for a given input to be recognized.
B. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs
should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure six sampling windows for detection to occur.
Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 6−19. GPIO Input Qualifier − Example Diagram for QUALPRD = 1
Table 6−19. General-Purpose Input Timing Requirements
MIN
tw(GPI)
G
†
Pulse duration
duration, GPIO low/high
All GPIOs
With no qualifier
With qualifier
2 * tc(SCO)
1 * tc(SCO) + IQT†
MAX
UNIT
cycles
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)
XCLKOUT
GPIOxn
tw(GPI)
Figure 6−20. General-Purpose Input Timing
104
NOTE:
The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC
pins as well.
SPRS257
June 2004
June 2004
6.19 SPI Master Mode Timing
Table 6−20. SPI Master Mode External Timing (Clock Phase = 0)†‡
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
NO.
1
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
UNIT
MIN
MAX
MIN
MAX
5tc(LCO)
127tc(LCO)
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M −0.5tc(LCO) −10
0.5tc(SPC)M −0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M −0.5tc(LCO) −10
0.5tc(SPC)M −0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)−10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)−10
0.5tc(SPC)M + 0.5tc(LCO)
td(SPCH-SIMO)M
Delay time, SPICLK high to
SPISIMO valid (clock polarity = 0)
− 10
10
− 10
10
td(SPCL-SIMO)M
Delay time, SPICLK low to
SPISIMO valid (clock polarity = 1)
− 10
10
− 10
10
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid
after SPICLK low
(clock polarity = 0)
0.5tc(SPC)M −10
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid
after SPICLK high
(clock polarity = 1)
0.5tc(SPC)M −10
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
0
0
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
0
0
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid
after SPICLK low
(clock polarity = 0)
0.25tc(SPC)M −10
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid
after SPICLK high
(clock polarity = 1)
0.25tc(SPC)M −10
2§
3§
4§
5§
8§
9§
ns
ns
ns
ns
0.5tc(SPC)M + 0.5tc(LCO) −10
ns
0.5tc(SPC)M + 0.5tc(LCO) −10
ns
0.5tc(SPC)M −0.5tc(LCO) −10
ns
SPRS257
†
105
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK or
LSPCLK
‡t
c(SPC) = SPI clock cycle time =
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
ADVANCE INFORMATION
Electrical Specifications
0.5tc(SPC)M −0.5tc(LCO)−10
Electrical Specifications
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
ADVANCE INFORMATION
9
SPISOMI
Master In Data
Must Be Valid
SPISTE†
†
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−21. SPI Master Mode External Timing (Clock Phase = 0)
106
SPRS257
June 2004
June 2004
Table 6−21. SPI Master Mode External Timing (Clock Phase = 1)†‡
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
NO.
MIN
1
MAX
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
MIN
UNIT
MAX
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M −0.5tc (LCO)−10
0.5tc(SPC)M − 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M −0.5tc (LCO)−10
0.5tc(SPC)M −0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) −10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M −10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) −10
0.5tc(SPC)M + 0.5tc(LCO)
tsu(SIMO-SPCH)M
Setup time, SPISIMO data
valid before SPICLK high
(clock polarity = 0)
0.5tc(SPC)M −10
tsu(SIMO-SPCL)M
Setup time, SPISIMO data
valid before SPICLK low
(clock polarity = 1)
0.5tc(SPC)M −10
0.5tc(SPC)M −10
tv(SPCH-SIMO)M
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)M −10
0.5tc(SPC)M −10
tv(SPCL-SIMO)M
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)M −10
0.5tc(SPC)M −10
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high
(clock polarity = 0)
0
0
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low
(clock polarity = 1)
0
0
tv(SPCH-SOMI)M
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 0)
0.25tc(SPC)M −10
0.5tc(SPC)M −10
tv(SPCL-SOMI)M
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 1)
0.25tc(SPC)M −10
2§
3§
6§
7§
10§
127tc(LCO)
ns
ns
ns
0.5tc(SPC)M −10
ns
ns
ns
ns
0.5tc(SPC)M −10
SPRS257
†
107
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK or
LSPCLK
‡t
c(SPC) = SPI clock cycle time =
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
ADVANCE INFORMATION
Electrical Specifications
11§
5tc(LCO)
Electrical Specifications
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Data Valid
Master Out Data Is Valid
10
ADVANCE INFORMATION
11
SPISOMI
Master In Data
Must Be Valid
SPISTE†
†
In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−22. SPI Master External Timing (Clock Phase = 1)
108
SPRS257
June 2004
Electrical Specifications
6.20 SPI Slave Mode Timing
Table 6−22. SPI Slave Mode External Timing (Clock Phase = 0)†‡
12
13§
14§
15§
MIN
Cycle time, SPICLK
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S −10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S −10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S −10
0.5tc(SPC)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S −10
0.5tc(SPC)S
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375tc(SPC)S −10
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S −10
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75tc(SPC)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S
16§
19§
MAX
4tc(LCO)‡
tc(SPC)S
20§
UNIT
ns
ns
ns
ns
ns
ns
ns
†
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
tc(SPC) = SPI clock cycle time = LSPCLK or
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
‡
June 2004
SPRS257
109
ADVANCE INFORMATION
NO.
Electrical Specifications
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
ADVANCE INFORMATION
20
SPISIMO
SPISIMO Data
Must Be Valid
SPISTE†
†
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain
low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−23. SPI Slave Mode External Timing (Clock Phase = 0)
110
SPRS257
June 2004
Electrical Specifications
Table 6−23. SPI Slave Mode External Timing (Clock Phase = 1)†‡
NO.
13§
14§
17§
MIN
Cycle time, SPICLK
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S −10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S −10
0.5tc(SPC)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S −10
0.5tc(SPC)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S −10
0.5tc(SPC)S
tsu(SOMI-SPCH)S
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
0.125tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0.75tc(SPC)S
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75tc(SPC)S
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S
18§
21§
MAX
tc(SPC)S
22§
8tc(LCO)
UNIT
ns
ns
ns
ns
ns
ns
ADVANCE INFORMATION
12
ns
†
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
tc(SPC) = SPI clock cycle time = LSPCLK or
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
‡
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
Data Valid
SPISOMI Data Is Valid
21
22
SPISIMO
SPISIMO Data
Must Be Valid
SPISTE†
†
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 1)
June 2004
SPRS257
111
Electrical Specifications
6.21 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6−24 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 6−24. Relationship Between Parameters Configured in XTIMING and Duration of Pulse†‡
DURATION (ns)
ADVANCE INFORMATION
DESCRIPTION
†
‡
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
XRDLEAD x tc(XTIM)
(XRDLEAD x 2) x tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) x tc(XTIM)
(XRDACTIVE x 2 + WS + 1) x tc(XTIM)
TR
Trail period, read access
XRDTRAIL x tc(XTIM)
(XRDTRAIL x 2) x tc(XTIM)
LW
Lead period, write access
XWRLEAD x tc(XTIM)
(XWRLEAD x 2) x tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) x tc(XTIM)
(XWRACTIVE x 2 + WS + 1) x tc(XTIM)
TW
Trail period, write access
XWRTRAIL x tc(XTIM)
(XWRTRAIL x 2) x tc(XTIM)
tc(XTIM) − Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
•
If the XREADY signal is ignored (USEREADY = 0), then:
1. Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions§:
XRDLEAD
XRDACTIVE
≥1
§
XRDTRAIL
≥0
XWRLEAD
≥0
XWRACTIVE
≥1
≥0
XWRTRAIL
≥0
X2TIMING
0, 1
No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when not sampling XREADY§:
XRDLEAD
§
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Valid
1
0
0
1
0
0
0, 1
No hardware to detect illegal XTIMING configurations
112
SPRS257
June 2004
Electrical Specifications
•
If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then:
1. Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2. Active:
AR ≥ 2 x tc(XTIM)
AW ≥ 2 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions†:
XRDLEAD
XRDACTIVE
≥1
†
XRDTRAIL
≥1
XWRLEAD
≥0
XWRACTIVE
≥1
XWRTRAIL
≥1
≥0
X2TIMING
0, 1
No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when using Synchronous XREADY†:
†
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Valid
1
1
0
1
1
0
0, 1
No hardware to detect illegal XTIMING configurations
•
If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1. Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2. Active:
AR ≥ 2 x tc(XTIM)
AW ≥ 2 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
3. Lead + Active:
LR + AR ≥ 4 x tc(XTIM)
LW + AW ≥ 4 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions†:
XRDLEAD
XRDACTIVE
≥1
†
XRDTRAIL
≥2
XWRLEAD
XWRACTIVE
≥1
0
XWRTRAIL
≥2
0
X2TIMING
0, 1
No hardware to detect illegal XTIMING configurations
or†
XRDLEAD
XRDACTIVE
≥2
†
XRDTRAIL
≥1
XWRLEAD
XWRACTIVE
≥2
0
XWRTRAIL
≥1
0
X2TIMING
0, 1
No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when using Asynchronous XREADY†:
XRDLEAD
†
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Invalid
1
1
0
1
1
0
0
Valid
1
1
0
1
1
0
1
Valid
1
2
0
1
2
0
0, 1
0
2
1
0
0, 1
Valid
2
1
No hardware to detect illegal XTIMING configurations
June 2004
SPRS257
113
ADVANCE INFORMATION
XRDLEAD
Invalid
Electrical Specifications
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6−25.
Table 6−25. XINTF Clock Configurations
Mode
SYSCLKOUT
XTIMCLK
XCLKOUT
1
Example:
150 MHz
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
2
Example:
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
3
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
4
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6−25.
XTIMING0
ADVANCE INFORMATION
XTIMING1
XTIMING2
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
SYSCLKOUT
R28x
CPU
/2
1†
XTIMCLK
0
XINTCNF2
(XTIMCLK)
†
/2
1†
0
XINTCNF2
(CLKMODE)
0
1
XCLKOUT
0
XINTCNF2
(CLKOFF)
Default Value after reset
Figure 6−25. Relationship Between XTIMCLK and SYSCLKOUT
6.22 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of
XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency
of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either
on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation
XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or
XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the
notation XCOH is used.
114
SPRS257
June 2004
Electrical Specifications
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
•
XR/W active low
XRDL
XRD active low
XWEL
XWE active low
XRDH
XRD inactive high
XWEH
XWE inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead +
active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with
respect to the falling edge of XCLKOUT.
Examples:
June 2004
XRNWL
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
•
Zone chip-select active low
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the
total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd,
then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
•
XZCSL
XZCSH
Zone chip-select inactive high
XRNWH
XR/W inactive high
SPRS257
115
ADVANCE INFORMATION
•
Electrical Specifications
6.23 External Interface Read Timing
Table 6−26. External Memory Interface Read Switching Characteristics
PARAMETER
MAX
UNIT
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
td(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
†
ns
Hold time, address valid after XRD inactive high
†
ns
th(XA)XRD
†
MIN
td(XCOH-XZCSL)
−2
−2
1
ns
3
ns
2
ns
1
ns
1
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6−27. External Memory Interface Read Timing Requirements
ADVANCE INFORMATION
MIN
MAX
UNIT
14‡
ns
AR − 12‡
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
(LR + AR) −
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
12
ns
th(XD)XRD
Hold time, read data valid after XRD inactive high
‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−24.
0
ns
Trail
Active
Lead
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
XR/W
ta(A)
th(XD)XRD
ta(XRD)
DIN
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−26. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
≥1
†
XRDACTIVE
XRDTRAIL
≥0
≥0
USEREADY
0
X2TIMING
0
XWRLEAD
N/A†
XWRACTIVE
N/A†
XWRTRAIL
N/A†
READYMODE
N/A†
N/A = “Don’t care” for this example
116
SPRS257
June 2004
Electrical Specifications
6.24 External Interface Write Timing
Table 6−28. External Memory Interface Write Switching Characteristics
MIN
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
td(XCOH-XA)
MAX
UNIT
1
ns
3
ns
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
1
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active low
−2
−2
0
ns
4
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
th(XD)XWE
Hold time, write data valid after XWE inactive high
ns
†
ns
TW−2‡
ns
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
4
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
‡ TW = Trail period, write access. See Table 6−24.
ns
ADVANCE INFORMATION
PARAMETER
†
Active
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
DOUT
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−27. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
N/A†
†
XRDACTIVE
XRDTRAIL
N/A†
N/A†
USEREADY
0
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
≥0
XWRTRAIL
≥0
READYMODE
N/A†
N/A = “Don’t care” for this example
June 2004
SPRS257
117
Electrical Specifications
6.25 External Interface Ready-on-Read Timing With One External Wait State
Table 6−29. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MAX
UNIT
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
td(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
†
ns
Hold time, address valid after XRD inactive high
†
ns
th(XA)XRD
†
MIN
td(XCOH-XZCSL)
−2
−2
1
ns
3
ns
2
ns
1
ns
1
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6−30. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
ADVANCE INFORMATION
MIN
‡
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
Hold time, read data valid after XRD inactive high
MAX
UNIT
14‡
ns
AR − 12‡
ns
(LR + AR) −
12
ns
0
ns
LR = Lead period, read access. AR = Active period, read access. See Table 6−24.
Table 6−31. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)§
MIN
§
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (Synch) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
3
ns
15
ns
0
ns
The first XREADY (Synch) sample occurs with respect to E in Figure 6−28:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6−32. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)¶
MIN
¶
tsu(XRDYAsynchL)XCOHL
Setup time, XREADY (Asynch) low before XCLKOUT high/low
th(XRDYAsynchL)
Hold time, XREADY (Asynch) low
te(XRDYAsynchH)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
tsu(XRDYAsynchH)XCOHL
Setup time, XREADY (Asynch) high before XCLKOUT high/low
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
MAX
11
UNIT
ns
8
ns
3
ns
11
ns
0
ns
The first XREADY (Asynch) sample occurs with respect to E in Figure 6−29:
E = (XRDLEAD + XRDACTIVE −2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
118
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Electrical Specifications
See Notes A and B
WS (Synch)
Active
Lead
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
th(XD)XRD
XD[0:15]
ADVANCE INFORMATION
DIN
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
Figure 6−28. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
≥1
†
XRDACTIVE
XRDTRAIL
3
≥1
USEREADY
1
X2TIMING
0
XWRLEAD
N/A†
XWRACTIVE
N/A†
XWRTRAIL
N/A†
READYMODE
0 = XREADY
(Synch)
N/A = “Don’t care” for this example
June 2004
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119
Electrical Specifications
WS (Asynch)
See Notes
A and B
Active
Lead
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
ADVANCE INFORMATION
th(XD)XRD
DIN
XD[0:15]
tsu(XRDYasynchL)XCOHL
te(XRDYasynchH)
th(XRDYasynchL)
th(XRDYasynchH)XZCSH
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
E. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE −2) tc(XTIM)
Figure 6−29. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
≥1
†
XRDACTIVE
XRDTRAIL
3
≥1
USEREADY
1
X2TIMING
0
XWRLEAD
N/A†
XWRACTIVE
N/A†
XWRTRAIL
N/A†
READYMODE
1 = XREADY
(Asynch)
N/A = “Don’t care” for this example
120
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Electrical Specifications
6.26 External Interface Ready-on-Write Timing With One External Wait State
Table 6−33. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
†
‡
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XWEL)
MIN
MAX
UNIT
1
ns
3
ns
2
ns
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
1
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active low
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
th(XD)XWE
Hold time, write data valid after XWE inactive high
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
−2
−2
0
ns
4
ns
†
ns
TW−2‡
ns
4
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access (see Table 6−24)
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)§
MIN
§
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (Synch) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
3
ns
15
ns
0
ns
The first XREADY (Synch) sample occurs with respect to E in Figure 6−30:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)¶
MIN
¶
tsu(XRDYasynchL)XCOHL
Setup time, XREADY (Asynch) low before XCLKOUT high/low
th(XRDYasynchL)
Hold time, XREADY (Asynch) low
te(XRDYasynchH)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
tsu(XRDYasynchH)XCOHL
Setup time, XREADY (Asynch) high before XCLKOUT high/low
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
MAX
11
UNIT
ns
8
ns
3
ns
11
ns
0
ns
The first XREADY (Synch) sample occurs with respect to E in Figure 6−31:
E = (XWRLEAD + XWRACTIVE − 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
June 2004
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121
ADVANCE INFORMATION
PARAMETER
td(XCOH-XZCSL)
Electrical Specifications
WS (Synch)
See
Notes A
and B
Trail
Active
Lead 1
See Note C
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYsynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
ADVANCE INFORMATION
XR/W
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES:
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an
access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 6−30. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
N/A†
122
SPRS257
XRDACTIVE
N/A†
XRDTRAIL
N/A†
USEREADY
1
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
0 = XREADY
(Synch)
June 2004
Electrical Specifications
WS (Asynch)
See Notes
A and B
Trail
Active
Lead 1
See Note C
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
th(XRDYasynchH)XZCSH
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
XR/W
ADVANCE INFORMATION
XWE
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE −2) tc(XTIM)
Figure 6−31. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
N/A†
†
XRDACTIVE
XRDTRAIL
N/A†
N/A†
USEREADY
1
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
1 = XREADY
(Asynch)
N/A = “Don’t care” for this example
June 2004
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123
Electrical Specifications
6.27 XHOLD and XHOLDA
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
ADVANCE INFORMATION
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XZCS0AND1
XD[15:0]
XZCS2
XWE, XRD
XZCS6AND7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events. Detailed timing diagram will be released in a future revision of this data sheet.
124
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June 2004
Electrical Specifications
6.28 XHOLD/XHOLDA Timing
Table 6−36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)†‡
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)
ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
5tc(XTIM)
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
4tc(XTIM)
ns
†
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
‡ The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
XD[15:0]
td(HH-BV)
High-Impedance
Valid
Valid
ÁÁ
ÁÁ
Á
Á
High-Impedance
See Note A
Valid
See Note B
NOTES: A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6−32. External Interface Hold Waveform
June 2004
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125
ADVANCE INFORMATION
td(HL-Hiz)
Electrical Specifications
Table 6−37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)†‡§
MIN
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
td(HH-HAH)
td(HH-BV)
MAX
UNIT
4tc(XTIM)+tc(XCO)
ns
4tc(XTIM+2tc(XCO)
ns
Delay time, XHOLD high to XHOLDA high
4tc(XTIM)
ns
Delay time, XHOLD high to Bus valid
6tc(XTIM)
ns
†
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
‡ The state of XHOLD is latched on the rising edge of XTIMCLK.
§ After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus,
for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.
ADVANCE INFORMATION
XCLKOUT
(1/2 XTIMCLK)
td(HL-HAL)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HiZ)
td(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
High-Impedance
Á
Á
Valid
XA[18:0]
Valid
XD[15:0]
See Note A
NOTES:
High-Impedance
Á
Á
Á
Á
Á
Valid
High-Impedance
See Note B
A All pending XINTF accesses are completed.
B Normal XINTF operation resumes.
Figure 6−33. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
126
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Electrical Specifications
6.29 On-Chip Analog-to-Digital Converter
6.29.1 ADC Absolute Maximum Ratings †
Supply voltage range,
VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG . . . . . . . . . . . . . . . . . . −0.3 V to 4.6 V
VSS1 to VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
Analog Input (ADCIN) Clamp Current, total (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA‡
†
ADVANCE INFORMATION
Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. Stresses beyond those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
‡ The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above V
DDA or below VSS. The continuous clamp
current per pin is ± 2 mA.
June 2004
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127
Electrical Specifications
6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions
Table 6−38. DC Specifications (See Note 1)
PARAMETER
MIN
Resolution
ADC clock (See Note 2)
TYP
MAX
UNIT
12
Bits
1
kHz
25
MHz
±1.5
LSB
±1
LSB
ACCURACY
INL (Integral nonlinearity)
DNL (Differential nonlinearity)
Offset error (See Note 3)
±80
LSB
Overall gain error with internal reference
(See Note 4)
±50
LSB
±50
LSB
Channel-to-channel offset variation
±8
LSB
Channel-to-channel Gain variation
±8
LSB
ADVANCE INFORMATION
Overall gain error with external reference
(See Note 5)
If ADCREFP-ADCREFM = 1 V ±0.1%
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
(See Note 6)
ADCLO
0
−5
Input capacitance
0
3
V
5
mV
±5
µA
10
Input leakage current
3
pF
INTERNAL VOLTAGE REFERENCE (See Note 4)
Accuracy, ADCVREFP
2
V
Accuracy, ADCVREFM
1
V
Voltage difference, ADCREFP - ADCREFM
1
V
50
PPM/°C
100
µV
Temperature coefficient
Reference noise
EXTERNAL VOLTAGE REFERENCE (See Note 5)
Accuracy, ADCVREFP
1.9
2
2.1
V
Accuracy, ADCVREFM
0.95
1
1.05
V
Input voltage difference,
ADCREFP - ADCREFM
0.99
1
1.01
V
NOTES: 1.
2.
3.
4.
Tested at 12.5-MHz ADCCLK
If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single tirmmed internal band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination
of the gain error shown here and the voltage reference accuracy (ADCREFP - ADCREFM). A software-based calibration
procedure is recommended for better accuracy. See F2812 ADC Calibration Application Note (literature number SPRA989) and
Section 5.2, Documentation Support, for relevant documents.
5. In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP-ADCREFM) will
determine the overall accuracy.
6. Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another
pin. To avoid this, the analog inputs should be kept within these limits.
128
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Electrical Specifications
Table 6−39. AC Specifications
PARAMETER
MIN
TYP
MAX
UNIT
SINAD
Signal-to-noise ratio + distortion
64
dB
SNR
Signal-to-noise ratio
66
dB
THD (100 kHz)
Total harmonic distortion
−68
dB
ENOB (SNR)
Effective number of bits
10.7
Bits
SFDR
Spurious free dynamic range
70
dB
6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)‡
IDDAIO (TYP)
IDD1 (TYP)
40 mA
1 µA
0.5 mA
7 mA
1 µA
1 µA
‡
0
0
0
ADC OPERATING MODE/CONDITIONS
Mode A (Operational Mode):
− BG and REF enabled
− PWD disabled
5 µA
Mode B:
− ADC clock enabled
− BG and REF enabled
− PWD enabled
5 µA
Mode C:
− ADC clock enabled
− BG and REF disabled
− PWD enabled
0
Mode D:
− ADC clock disabled
− BG and REF disabled
− PWD enabled
ADVANCE INFORMATION
IDDA (TYP)§
Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
§I
DDA − includes current into VDDA1 / VDDA2 and AVDDREFBG
June 2004
SPRS257
129
Electrical Specifications
Rs
Source
Signal
ADCIN0
Ron
1 kΩ
Switch
Cp
10 pF
ac
Ch
1.25 pF
28x DSP
Typical Values of the Input Circuit Components:
ADVANCE INFORMATION
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):
1 kΩ
1.25 pF
10 pF
50 Ω
Figure 6−34. ADC Analog Input Impedance Model
6.29.4 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
Request for
ADC
Conversion
td(PWD)
Figure 6−35. ADC Power-Up Control Bit Timing
Table 6−40. ADC Power-Up Delays†
†
td(BGR)
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the PWDNADC bit is enabled.
td(PWD)
Delay time for power
power-down
down control to be stable. Bit 7 of the ADCTRL3 register
(PWDNADC) is to be set to 1 before any ADC conversions are initiated.
MIN
TYP
MAX
UNIT
7
8
10
ms
20
50
1
ms
µs
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions
are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.
130
SPRS257
June 2004
Electrical Specifications
6.29.5 Detailed Description
6.29.5.1
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2.0 V and ADCVREFM is set to 1.0 V.
6.29.5.2
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a
time. These inputs are software-selectable.
6.29.5.3
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
6.29.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected
channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
June 2004
SPRS257
131
ADVANCE INFORMATION
6.29.5.4
Electrical Specifications
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschx_n+1
tdschx_n
ADVANCE INFORMATION
ADC Event Trigger
from EV or Other
Sources
tSH
Figure 6−36. Sequential Sampling Mode (Single-Channel) Timing
Table 6−41. Sequential Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event
trigger to sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/
Acquisition width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schx_n)
Delay time for first result
to appear in the Result
register
4tc(ADCCLK)
160 ns
td(schx_n+1)
Delay time for successive
results to appear in the
Result register
132
SPRS257
(2 + Acqps) *
tc(ADCCLK)
REMARKS
Acqps value = 0-15
ADCTRL1[8:11]
80 ns
June 2004
Electrical Specifications
6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0
to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The
Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide
(maximum).
In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ...,
A7/B7, and not in other combinations (such as A1/B3, etc.).
Sample n
Analog Input on
Channel Ax
Analog Input on
Channel Bv
Sample n+1
Sample n+2
ADVANCE INFORMATION
NOTE:
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
tSH
ADC Event Trigger
from EV or Other
Sources
td(SH)
tdschA0_n+1
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 6−37. Simultaneous Sampling Mode Timing
Table 6−42. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event
trigger to sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/
Acquisition Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schA0_n)
Delay time for first result
to appear in Result
register
4tc(ADCCLK)
160 ns
td(schB0_n)
Delay time for first result
to appear in Result
register
5tc(ADCCLK)
200 ns
td(schA0_n+1)
Delay time for
successive results to
appear in Result register
(3 + Acqps) *
tc(ADCCLK)
120 ns
td(schB0_n+1)
Delay time for
successive results to
appear in Result register
(3 + Acqps) *
tc(ADCCLK)
120 ns
June 2004
REMARKS
Acqps value = 0-15
ADCTRL1[8:11]
SPRS257
133
Electrical Specifications
6.29.8 Definitions of Specifications and Terminology
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined
as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
ADVANCE INFORMATION
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code
transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N+
(SINAD * 1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
134
SPRS257
June 2004
Electrical Specifications
6.30 Multichannel Buffered Serial Port (McBSP) Timing
6.30.1 McBSP Transmit and Receive Timing
Table 6−43. McBSP Timing Requirements†‡
McBSP module clock (CLKG,
(CLKG CLKX,
CLKX CLKR) range
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P-7
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
Setup time,
time external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time,
time external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time,
time DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time,
time DR valid after CLKR low
M19
tsu(FXH-CKXL)
time external FSX high before CLKX low
Setup time,
M20
th(CKXL-FXH)
Hold time,
time external FSX high after CLKX low
20§
MHz
kHz
ns
1
M11
tsu(FRH-CKRL)
UNIT
50
(CLKG CLKX
McBSP module cycle time (CLKG,
CLKX, CLKR) range
M15
MAX
1
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKX int
18
CLKX ext
2
CLKX int
0
CLKX ext
6
ms
ns
ns
7
ns
7
ns
ns
ns
ns
ns
ns
ns
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
CLKSRG
‡ 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
.
(1 ) CLKGDV)
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
§ Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed
limit (20 MHz).
June 2004
SPRS257
135
ADVANCE INFORMATION
MIN
NO.
Electrical Specifications
Table 6−44. McBSP Switching Characteristics†‡
PARAMETER
NO.
MAX
UNIT
M1
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D-5§
D+5§
ns
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C-5§
C+5§
ns
M4
td(CKRH-FRV)
Delay time,
time CLKR high to internal FSR valid
M5
td(CKXH-FXV)
time CLKX high to internal FSX valid
Delay time,
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int
8
CLKX ext
14
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX int
9
CLKX ext
28
CLKX int
8
CLKX ext
14
CLKX int
P+8
M7
ADVANCE INFORMATION
MIN
td(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
Enable time, CLKX high to DX driven
M8
M9
M10
DXENA = 0
ten(CKXH-DX)
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
Delay time, FSX high to DX valid
DXENA = 0
td(FXH-DXV)
ten(FXH-DX)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
DXENA = 1
Enable time, FSX high to DX driven
DXENA = 0
ns
CLKR int
0
4
ns
CLKR ext
3
27
ns
CLKX int
0
4
CLKX ext
3
27
CLKX ext
ns
ns
ns
P + 14
CLKX int
0
CLKX ext
6
CLKX int
P
CLKX ext
P+6
FSX int
ns
8
FSX ext
14
FSX int
P+8
FSX ext
P + 14
FSX int
0
FSX ext
6
FSX int
P
ns
ns
Only applies to first bit transmitted when in Data DXENA = 1
FSX ext
P+6
Delay 0 (XDATDLY=00b) mode
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ 2P = 1/CLKG in ns.
§ C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
136
SPRS257
June 2004
Electrical Specifications
M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
Bit (n−1)
(n−2)
(n−3)
M17
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−2)
M17
(n−3)
ADVANCE INFORMATION
DR
(RDATDLY=00b)
M18
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 6−38. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
M14
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
DX
(XDATDLY=00b)
M10
Bit 0
M9
M7
Bit (n−1)
(n−2)
Bit 0
Bit (n−1)
(n−2)
(n−3)
M7
M6
DX
(XDATDLY=10b)
(n−4)
M7
M8
DX
(XDATDLY=01b)
(n−3)
M8
Bit 0
Bit (n−1)
(n−2)
Figure 6−39. McBSP Transmit Timing
June 2004
SPRS257
137
Electrical Specifications
6.30.2 McBSP as SPI Master or Slave Timing
Table 6−45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
NO
NO.
MIN
SLAVE
MAX
MIN
MAX
UNIT
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
P-10
8P-10
ns
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
P-10
8P-10
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P+10
ns
M33
tc(CKX)
Cycle time, CLKX
16P
ns
2P
Table 6−46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†
ADVANCE INFORMATION
NO
NO.
†
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M32
LSB
M33
MSB
CLKX
M25
M24
FSX
M28
DX
M29
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
138
SPRS257
June 2004
Electrical Specifications
Table 6−47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†
MASTER
NO
NO.
MIN
MAX
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
P-10
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P-10
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
2P
SLAVE
MIN
UNIT
MAX
8P-10
ns
8P-10
ns
16P+10
ns
16P
ns
Table 6−48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†
†
MASTER
PARAMETER
MIN
MAX
SLAVE
MIN
UNIT
MAX
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
P+6
7P+6
ns
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M38
Bit 0
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
June 2004
SPRS257
139
ADVANCE INFORMATION
NO
NO.
Electrical Specifications
Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†
MASTER
NO
NO.
MIN
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
P-10
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P-10
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MAX
UNIT
8P-10
ns
8P-10
ns
8P+10
ns
16P
ns
2P
Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†
ADVANCE INFORMATION
NO
NO.
†
MASTER
PARAMETER
MIN
MAX
SLAVE
MIN
UNIT
MAX
M43
th(CKXH-FXL)
Hold time, FSX low after CLKX high
2P
ns
M44
td(FXL-CKXL)
Delay time, FSX low to CLKX low
P
ns
M47
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
6
6P + 6
ns
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M52
MSB
M51
LSB
CLKX
M43
M44
FSX
M47
DX
M48
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
140
SPRS257
June 2004
Electrical Specifications
Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†
NO
NO.
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
M58
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
P - 10
8P - 10
ns
M59
th(CKXL-DRV)
Hold time, DR valid after CLKX low
P - 10
8P - 10
ns
16P +
10
ns
16P
ns
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61
tc(CKX)
Cycle time, CLKX
2P
Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†
MASTER‡
PARAMETER
MIN
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
M56
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
SLAVE
MAX
MIN
MAX
UNIT
P
ns
2P
ns
P+6
7P + 6
ns
6
4P + 6
ns
†
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
‡ C = CLKX low pulse width = P
D = CLKX high pulse width = P
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
June 2004
SPRS257
141
ADVANCE INFORMATION
NO
NO.
Electrical Specifications
7
Migration From F281x Devices
Table 6−53 shows the differences between F281x and R281x features. F281x stands for TMS320F2810,
TMS320F2811, and TMS320F2812 devices. R281x stands for TMS320R2811 and TMS320R2812 devices.
Table 6−53. Feature Comparison Between F281x and R281x Devices
FEATURES
R2811
F2811
R2812
F2812
Instruction Cycle (at 150 MHz)
6.67 ns
6.67 ns
6.67 ns
6.67 ns
Single−Access RAM (SARAM)
(16−bit word)
20K
18K
20K
18K
Disabled
Selectable
Disabled
Selectable
On−chip Non−Voltaile memory
No
Yes
No
Yes
F281x Flash/OTP space are reserved in
R281x devices.
Boot ROM
Yes
Yes
Yes
Yes
Same Boot ROM code as F281x devices.
Flash/OTP Boot ROM
No
Yes
No
Yes
Not available on R281x
SPI−EEPROM Boot
Yes
Yes
Yes
Yes
H0 SARAM Boot
Yes
Yes
Yes
Yes
SCI, Parallel I/O Boot
Yes
Yes
Yes
Yes
External Memory Interface
No
No
Yes
Yes
EVA, EVB
EVA, EVB
EVA, EVB
EVA, EVB
General−Purpose (GP) Timers
4
4
4
4
Compare (CMP)/PWM
16
16
16
16
Capture (CAP)/QEP Channels
6/2
6/2
6/2
6/2
Watchdog Timer
Yes
Yes
Yes
Yes
12−Bit ADC
Yes
Yes
Yes
Yes
Channels
16
16
16
16
32−Bit CPU Timers
3
3
3
3
Yes
Yes
Yes
Yes
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
CAN
Yes
Yes
Yes
Yes
McBSP
Yes
Yes
Yes
Yes
Digital I/O Pins (Shared)
56
56
56
56
External Interrupts
3
3
3
3
150 MHz
150 MHz
150 MHz
150 MHz
ADVANCE INFORMATION
Code Security feature
Event Managers A and B
(EVA and EVB)
SPI
SCIA, SCIB
Supply Voltage − 1.9 V, 3.3 V,
(5%)
142
SPRS257
R281X MIGRATION CONSIDERATIONS
R281x SARAM execution is single cycle,
zero−wait-state at 150 MHz.
Additional 2K words of SARAM −L2/L3
blocks −See section 3.2.7.
Code secuirty in R281x affects L0/L1
SARAM. However, CSM password
locations are preset as 0xFFFF to facilitate
easy unsecuring. See Section 3.2.9.
Internal reference trimmed for gain
accuracy. Supports external reference
mode as in F281x devices. See Section 4.3.
June 2004
Electrical Specifications
Table 6−53. Feature Comparison Between F281x and R281x Devices (Continued)
FEATURES
R2811
F2811
R2812
F2812
Supply Voltage − 1.8 V, 3.3 V,
(5%)
135 MHz
135 MHz
135 MHz
135 MHz
Power sequencing
Optional
Required
Optional
Required
Packaging
128−pin
128−pin
179−ball/
176−pin
179−ball/
176−pin
PBK
PBK
GHH, ZHH,
PGF
GHH, ZHH,
PGF
A: −40°C to 85°C
Yes
Yes
Yes
Yes
S/Q: −40°C to 125°C
Yes
Yes
Yes
Yes
Product Status
TMX
TMS
TMX
TMS
F281x
version
F281x
version
F281x
version
F281x
version
2.2x or
above
2.2x or
above
2.2x or
above
2.2x or
above
USB version
XDS510PP+
R281X MIGRATION CONSIDERATIONS
Power sequencing is optional in R281x
devices. See Section 6.7.
Lead−free options in all packages
Reference Guides
See the F281x −CPU and peripheral
reference guides listed in Section 5.2 and in
the TMS320F28x Peripherals Reference
Guide (literature number SPRU566).
Code Development
CCS
eZdsp
Emulators
C281x C/C++ Header Files
and Peripheral Examples
(literature number SPRC097)
June 2004
All versions
All versions
All versions
All versions
Rev.1.0
Rev.1.0
Rev.1.0
Rev.1.0
XDS510/XDS510PP+, XDS510USB or
other compatible emulators
Use DSP281x C/C++−header files rev 1.0
or later. Disable or remove sections that are
not applicable to R281x, such as Flash and
OTP.
SPRS257
143
ADVANCE INFORMATION
Temperature Options
Mechanical Data
8
Mechanical Data
8.1
Ball Grid Array (BGA)
GHH (S-PBGA-N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
10,40 TYP
SQ
0,80
0,40
A1 Corner
0,80
0,40
ADVANCE INFORMATION
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4173504−3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.
D. This package is not lead-free and needs a minimum reflow temperature of 220°C but not exceeding 235°C.
Figure 7−1. TMS320R2812 179-Ball GHH MicroStar BGA
Table 7−1. Thermal Resistance Characteristics for 179-GHH
PARAMETER
179-GHH PACKAGE
UNIT
PsiJT
0.658
°C / W
ΘJA
42.57
°C / W
ΘJC
16.08
°C / W
MicroStar BGA is a trademark of Texas Instruments.
144
SPRS257
June 2004
Mechanical Data
8.2
Plastic Ball Grid Array
ZHH (S−PBGA−N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
SQ
10,40 TYP
0,80
0,40
P
N
M
L
K
J
H
G
F
E
D
C
B
A
ADVANCE INFORMATION
0,80
0,40
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A1 Corner
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4204739/A 10/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar BGAt configuration.
This package is lead-free and needs a minimum reflow temperature of 250°C but not exceeding 260°C.
Figure 7−2. TMS320R2812 179-Ball ZHH MicroStar BGA
Table 7−2. Thermal Resistance Characteristics for 179-ZHH
PARAMETER
179-ZHH PACKAGE
UNIT
PsiJT
0.658
°C / W
ΘJA
42.57
°C / W
ΘJC
16.08
°C / W
MicroStar BGA is a trademark of Texas Instruments.
June 2004
SPRS257
145
Mechanical Data
8.3
Low-Profile Quad Flatpacks (LQFPs)
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
88
133
0,27
0,17
0,08 M
ADVANCE INFORMATION
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
0,25
0,05 MIN
26,20
SQ
25,80
0°− 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
NOTES: A.
B.
C.
D.
4040134 / B 11/96
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This package is lead-free and needs a minimum reflow temperature of 220°C but not exceeding 235°C.
Figure 7−3. TMS320R2812 176-Pin PGF LQFP
Table 7−3. Thermal Resistance Characteristics for 176-PGF
146
SPRS257
PARAMETER
176-PGF PACKAGE
UNIT
PsiJT
0.247
°C / W
ΘJA
41.88
°C / W
ΘJC
9.73
°C / W
June 2004
Mechanical Data
PBK (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
0,40
96
0,07 M
65
128
33
1
ADVANCE INFORMATION
64
97
0,13 NOM
32
Gage Plane
12,40 TYP
14,20
SQ
13,80
16,20
SQ
15,80
0,25
0,05 MIN
0°− 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040279-3 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This package is lead-free and needs a minimum reflow temperature of 220°C but not exceeding 235°C.
Figure 7−4. TMS320R2811 128-Pin PBK LQFP
Table 7−4. Thermal Resistance Characteristics for 128-PBK
June 2004
PARAMETER
128-PBK PACKAGE
UNIT
PsiJT
0.271
°C / W
ΘJA
41.65
°C / W
ΘJC
10.76
°C / W
SPRS257
147