TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 D D D D D D D Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201 – 6-, 5-ns Instruction Cycle Time – 167-, 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 1336, 1 600 MIPS Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201B – 5-, 4.3-ns Instruction Cycle Time – 200-, and 233-MHz Clock Rates – Eight 32-Bit Instructions/Cycle – 1600, 1 860 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) ’C62x CPU Core – Eight Independent Functional Units: – Six ALUs (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Results) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization 1M-Bit On-Chip SRAM – 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) – 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201) – 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B) 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM and SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel GJC/GJL/GGP 352-PIN BALL GRID ARRAY (BGA) PACKAGES (BOTTOM VIEW) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 D D D D D D D D D D D 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 16-Bit Host-Port Interface (HPI) – Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial Peripheral Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked Loop (PLL) Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan Compatible 352-Pin BGA Package (GGP Suffix) (’6201) 352-Pin BGA Package (GJC Suffix) (’6201B) 352-Pin BGA Package (GJL Suffix) (’6201B) CMOS Technology – 0.25-µm/5-Level Metal Process (’6201) – 0.18-µm/5-Level Metal Process (’6201B) 3.3-V I/Os, 2.5-V Internal (’6201) 3.3-V I/Os, 1.8-V Internal (’6201B) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 description The TMS320C62x† DSPs (including the TMS320C6201 and the TMS320C6201B devices) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C6201 (’C6201) and the TMS320C6201B (’C6201B) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the ’C6201 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6201B is a newer revision of the ’C6201 with performance of up to 1860 MIPS at a clock rate of 233 MHz. The ’C6201/’C6201B DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. Each of these processors have 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. Both the ’C6201 and the ’C6201B can produce two multiply-accumulates (MACs) per cycle—for a total of 400 million MACs per second (MMACS) for the ’C6201, and a total of 466 MMACS for the ’C6201B. The ’C62x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’C6201/’C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the ’C6201 consists of a 64K-byte block of RAM, while data memory of the ’C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The ’C62x has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the ’C62x DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the ’C6201/’C6201B Processors CHARACTERISTICS DESCRIPTION Device Number TMS320C6201 TMS320C6201B On-Chip Memory 512-Kbit Program Memory 512-Kbit Data Memory (organized as a single block) 512-Kbit Program Memory 512-Kbit Data Memory (organized as two blocks) Peripherals 2 Multichannel Buffered Serial Ports (McBSPs) 2 General-Purpose Timers Host-Port Interface (HPI) External Memory Interface (EMIF) 2 Multichannel Buffered Serial Ports (McBSPs) 2 General-Purpose Timers Host-Port Interface (HPI) External Memory Interface (EMIF) Cycle Time 5 ns (TMS320C6201-200), 6 ns (TMS320C6201-167) 4.3 ns (TMS320C6201B-233), 5 ns (TMS320C6201B-200) Package Type 35 mm × 35 mm, 352-Pin BGA (GGP) 35 mm × 35 mm, 352-Pin BGA (GJC), 27 mm × 27 mm, 352-Pin BGA (GJL) Nominal Voltage 2.5 V Core 3.3 V I/O 1.8 V Core 3.3 V I/O TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation. † Where unique device characteristics are specified, TMS320C6201 and TMS320C6201B identifiers are used. For generic characteristics, no identifiers are needed, ’C62x is used, or ’C6000 is used. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 functional block diagram Timers Interrupt Selector McBSPs HPI Control DMA Control EMIF Control Peripheral Bus Controller Host-Port Interface DMA Controller Data Memory Data Memory Controller PLL CPU EMIF Power Down Program Memory Controller BootConfig. Program Memory/Cache POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the ’C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 CPU description (continued) Program Memory 32-Bit Address 256-Bit Data ÁÁ ÁÁ ÁÁ Á Á Á Á Á External Memory Interface Á Á Á Á Á Á ’C62x CPU Program Fetch Control Registers Instruction Dispatch Instruction Decode Data Path A Data Path B Register File A Register File B Control Logic ÁÁ Á Á ÁÁ ÁÁ ÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á Á ÁÁÁ Á Á ÁÁ ÁÁ Á Á ÁÁ ÁÁ ÁÁ ÁÁ Á Á Test .L1 .S1 .M1 .D1 .D2 .M2 .S2 Data Memory 32-Bit Address 8-, 16-, 32-Bit Data .L2 Emulation Interrupts Additional Peripherals: Timers, Serial Ports, etc. Figure 1. TMS320C62x CPU Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 CPU description (continued) ÁÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ Á ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ Á ÁÁÁÁ ÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁÁÁ src1 .L1 src2 dst long dst long src ST1 Data Path A long src long dst dst .S1 src1 8 8 32 8 Register File A (A0–A15) src2 .M1 dst src1 src2 LD1 DA1 DA2 .D1 .D2 dst src1 src2 2X 1X src2 src1 dst LD2 src2 .M2 src1 dst src2 Data Path B src1 dst long dst long src Register File B (B0–B15) .S2 ST2 long src long dst dst .L2 src2 8 32 8 src1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Á 8 Figure 2. TMS320C62x CPU Data Paths 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Control Register File TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF Boot Mode BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0 Reset and Interrupts RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 Little ENDIAN Big ENDIAN LENDIAN Clock/PLL TMS TDO TDI TCK TRST EMU1 EMU0 JTAG Emulation RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status HD[15:0] HCNTL0 HCNTL1 16 Data HPI (Host-Port Interface) Register Select Control HHWIL HBE1 HBE0 Half-Word/Byte Select HAS HR/W HCS HDS1 HDS2 HRDY HINT Figure 3. CPU and Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 signal groups description (continued) 32 ED[31:0] Data Asynchronous Memory Control CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 HOLD HOLDA ARE AOE AWE ARDY Memory Map Space Select 20 Word Address SBSRAM Control SSADS SSOE SSWE SSCLK SDRAM Control SDA10 SDRAS SDCAS SDWE SDCLK Byte Enables HOLD/ HOLDA EMIF (External Memory Interface) TOUT1 Timer 1 Timer 0 TOUT0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Receive Receive CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 4. Peripheral Signals 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions SIGNAL GGP, GJC PIN NO. GJL PIN NO. TYPE† CLKIN C10 B9 I Clock Input CLKOUT1 AF22 AC18 O Clock output at full device speed CLKOUT2 O Clock output at half of device speed NAME DESCRIPTION CLOCK/PLL AF20 AC16 CLKMODE1 C6 D8 CLKMODE0 C5 C7 PLLFREQ3 A9 A9 PLLFREQ2 D11 D11 PLLFREQ1 PLLV‡ B10 B10 D12 B11 PLLG‡ C12 PLLF I Clock-mode select • Selects whether the CPU clock frequency = input clock frequency x4 or x1 PLL frequency range (3, 2, and 1) I • The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. PLL analog VCC connection for the low-pass filter C12 A§ A§ A11 D12 A§ PLL low-pass filter connection to external components and a bypass capacitor TMS L3 L3 I TDO W2 U4 O/Z TDI R4 T2 I JTAG test port data in (features an internal pullup) TCK R3 R3 I JTAG test port clock TRST T1 R4 I JTAG test port reset (features an internal pulldown) EMU1 Y1 V3 I/O/Z EMU0 W3 W2 I/O/Z RESET K2 K2 I Device reset NMI L2 L2 I Nonmaskable interrupt • Edge-driven (rising edge) EXT_INT7 U3 U2 EXT_INT6 V2 T4 EXT_INT5 W1 V1 I External interrupts • Edge-driven (rising edge) EXT_INT4 U4 V2 IACK Y2 Y1 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 AA1 V4 INUM2 W4 Y2 INUM1 AA2 AA1 O Active interrupt identification number • Valid during IACK for all active interrupts (not just external) • Encoding order follows the interru interrupt-service t service fetch fetch-packet acket ordering INUM0 AB1 W4 PLL analog GND connection for the low-pass filter JTAG EMULATION JTAG test port mode select (features an internal pullup) JTAG test port data out Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS LITTLE ENDIAN/BIG ENDIAN LENDIAN H3 G2 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing POWER-DOWN STATUS PD D3 E2 O Power-down mode 2 or 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL GGP, GJC PIN NO. GJL PIN NO. TYPE† HINT H26 J26 O Host interrupt (from DSP to host) HCNTL1 F23 G24 I Host control – selects between control, address, or data registers HCNTL0 D25 F25 I Host control – selects between control, address, or data registers HHWIL C26 E26 I Host half-word select – first or second half-word (not necessarily high or low order) NAME DESCRIPTION HOST-PORT INTERFACE (HPI) HBE1 E23 F24 I Host byte select within word or half-word HBE0 D24 E25 I Host byte select within word or half-word HR/W C23 B22 I Host read or write select HD15 B13 A12 HD14 B14 D13 HD13 C14 C13 HD12 B15 D14 HD11 D15 B15 HD10 B16 C15 HD9 A17 D15 HD8 B17 B16 HD7 D16 C16 HD6 B18 B17 HD5 A19 D16 HD4 C18 A18 HD3 B19 B18 HD2 C19 D17 HD1 B20 C18 HD0 B21 A20 HAS C22 C20 I Host address strobe HCS B23 B21 I Host chip select HDS1 D22 C21 I Host data strobe 1 HDS2 A24 D20 I Host data strobe 2 HRDY J24 J25 O Host ready (from DSP to host) BOOTMODE4 D8 C8 BOOTMODE3 B4 B6 BOOTMODE2 A3 D7 BOOTMODE1 D5 C6 I/O/Z Host port data (used for transfer of data, Host-port data address, address and control) BOOT MODE I Boot mode BOOTMODE0 C4 B5 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME GGP, GJC PIN NO. GJL PIN NO. TYPE† DESCRIPTION EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AE22 AD20 CE2 AD26 AA24 CE1 AB24 AB26 CE0 AC26 AA25 BE3 AB25 Y24 BE2 AA24 W23 BE1 Y23 AA26 BE0 AA26 W25 EA21 J26 K25 EA20 K25 L24 EA19 L24 L25 EA18 K26 M23 EA17 M26 M25 EA16 M25 M24 EA15 P25 N23 EA14 P24 P24 EA13 R25 P23 EA12 T26 R25 EA11 R23 R24 EA10 U26 R23 EA9 U25 T25 EA8 T23 T24 EA7 V26 U25 O/Z Memory space enables • Enabled by bits 24 and 25 of the word address • Only one asserted during any external data access Byte-enable control O/Z • Decoded from the two lowest bits of the internal address • Byte-write enables for most types of memory • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF – ADDRESS EA6 V25 T23 EA5 W26 V26 EA4 V24 V25 EA3 W25 U23 O/Z External address (word address) EA2 Y26 V24 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL GGP, GJC PIN NO. GJL PIN NO. ED31 AB2 Y3 ED30 AC1 AA2 ED29 AA4 AB1 ED28 AD1 AA3 ED27 AC3 AB2 ED26 AD4 AE5 ED25 AF3 AD6 ED24 AE4 AC7 ED23 AD5 AE6 ED22 AF4 AD7 ED21 AE5 AC8 ED20 AD6 AD8 ED19 AE6 AC9 ED18 AD7 AF7 ED17 AC8 AD9 ED16 AF7 AC10 ED15 AD9 AE9 ED14 AD10 AF9 NAME TYPE† DESCRIPTION EMIF – DATA ED13 AF9 AC11 ED12 AC11 AE10 ED11 AE10 AD11 ED10 AE11 AE11 ED9 AF11 AC12 ED8 AE14 AD12 I/O/Z External data ED7 AF15 AE12 ED6 AE15 AC13 ED5 AF16 AD14 ED4 AC15 AC14 ED3 AE17 AE15 ED2 AF18 AD15 ED1 AF19 AE16 ED0 AC17 AD16 ARE Y24 V23 O/Z Asynchronous memory read enable AOE AC24 AB25 O/Z Asynchronous memory output enable AWE AD23 AE22 O/Z Asynchronous memory write enable EMIF – ASYNCHRONOUS MEMORY CONTROL ARDY W23 Y26 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL TYPE† DESCRIPTION GGP, GJC PIN NO. GJL PIN NO. SSADS AC20 AD19 O/Z SBSRAM address strobe SSOE AF21 AD18 O/Z SBSRAM output enable SSWE AD19 AF18 O/Z SBSRAM write enable SSCLK AD17 AC15 O SDA10 AD21 AC19 O/Z SDRAM address 10 (separate for deactivate command) SDRAS AF24 AD21 O/Z SDRAM row-address strobe SDCAS AD22 AC20 O/Z SDRAM column-address strobe SDWE AF23 AE21 O/Z SDRAM write enable SDCLK AE20 AC17 O SDRAM clock HOLD AA25 Y25 I Hold request from the host A7 C9 O Hold-request acknowledge to the host NAME EMIF – SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SBSRAM clock EMIF – SYNCHRONOUS DRAM (SDRAM) CONTROL EMIF – BUS ARBITRATION HOLDA TIMERS TOUT1 H24 K23 O Timer 1 or general-purpose output TINP1 K24 L23 I Timer 1 or general-purpose input TOUT0 M4 M4 O Timer 0 or general-purpose output TINP0 K4 H2 I Timer 0 or general-purpose input DMA ACTION COMPLETE STATUS DMAC3 D2 E1 DMAC2 F4 F2 DMAC1 D1 G3 DMAC0 E2 H4 CLKS1 E25 F26 I CLKR1 H23 H25 I/O/Z Receive clock CLKX1 F26 J24 I/O/Z Transmit clock DR1 D26 H23 I Receive data DX1 G23 G25 O/Z Transmit data FSR1 E26 J23 I/O/Z Receive frame sync O DMA action complete MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) External clock source (as opposed to internal) FSX1 F25 G26 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL TYPE† DESCRIPTION GGP, GJC PIN NO. GJL PIN NO. CLKS0 L4 L4 I CLKR0 M2 M2 I/O/Z Receive clock CLKX0 L1 M3 I/O/Z Transmit clock DR0 J1 J1 I Receive data DX0 R1 P4 O/Z Transmit data FSR0 P4 N3 I/O/Z Receive frame sync FSX0 P3 N4 I/O/Z Transmit frame sync RSV0 T2 T3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor NAME MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) External clock source (as opposed to internal) RESERVED FOR TEST RSV1 G2 F1 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 C11 C11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 B9 D10 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV4 A6 D9 I Reserved for testing, pulldown with a dedicated 20-kΩ resistor RSV5 C8 A7 O Reserved (leave unconnected, do not connect to power or ground) RSV6 C21 D18 I Reserved for testing, pullup with a dedicated 20-k RSV7 B22 C19 I Reserved for testing, pullup with a dedicated 20-k RSV8 A23 D19 I W resistor W resistor Reserved for testing, pullup with a dedicated 20-kW resistor RSV9 E4 F3 O Reserved (leave unconnected, do not connect to power or ground) A8 AF20 UNCONNECTED PINS NC B8 AE18 C9 AE17 D10 – D21 – G1 J4 H1 J3 H2 G1 J2 K4 K3 J2 R2 R2 Unconnected pins † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME GGP, GJC PIN NO. GJL PIN NO. A10 A5 A15 A11 A18 A16 A21 A22 A22 B7 TYPE† DESCRIPTION 3.3-V SUPPLY VOLTAGE PINS DVDD B7 B8 C1 B19 D17 B20 F3 C10 G24 C14 G25 C17 H25 G4 J25 G23 L25 H3 M3 H24 N3 K3 N23 K24 R26 L1 T24 L26 U24 N24 W24 P3 Y4 T1 AB3 T26 AB4 U3 AB26 U24 AC6 W3 AC10 W24 AC19 Y4 AC21 Y23 AC22 AD10 AC25 AD13 AD11 AD17 AD13 AE7 AD15 AE8 AD18 AE19 AE18 AE20 AE21 AF5 AF5 AF11 AF6 AF16 S 3 3 V supply voltage 3.3-V AF17 AF22 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME GGP, GJC PIN NO. GJL PIN NO. TYPE† DESCRIPTION 2.5-V SUPPLY VOLTAGE PINS FOR ’C6201 1.8-V SUPPLY VOLTAGE PINS FOR ’C6201B CVDD A5 A1 A12 A2 A16 A3 A20 A24 B2 A25 B6 A26 B11 B1 B12 B2 B25 B3 C3 B24 C15 B25 C20 B26 C24 C1 D4 C2 D6 C3 D7 C4 D9 C23 D14 C24 D18 C25 D20 C26 D23 D3 E1 D4 F1 D5 H4 D22 J4 D23 J23 D24 K1 E4 K23 E23 M1 AB4 M24 AB23 N4 AC3 N25 AC4 P2 AC5 P23 AC22 T3 AC23 T4 AC24 U1 AD1 S 2.5-V supply y voltage g for ’C6201 1.8-V supply voltage for ’C6201B V4 AD2 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME GGP, GJC PIN NO. GJL PIN NO. TYPE† DESCRIPTION 2.5-V SUPPLY VOLTAGE PINS FOR ’C6201 1.8-V SUPPLY VOLTAGE PINS FOR ’C6201B (CONTINUED) V23 CVDD AD3 AC4 AD4 AC9 AD23 AC12 AD24 AC13 AD25 AC18 AD26 AC23 AE1 AD3 AE2 AD8 AE3 AD14 AE24 AD24 AE25 AE2 AE26 AE8 AF1 AE12 AF2 AE25 AF3 AF12 AF24 – AF25 – AF26 S 2.5-V supplyy voltage g for ’C6201 1.8-V supply voltage for ’C6201B GROUND PINS VSS A1 A4 A2 A6 A4 A8 A13 A10 A14 A13 A25 A14 A26 A15 B1 A17 B3 A19 B5 A21 B24 A23 B26 B4 C2 B12 C7 B13 C13 B14 C16 B23 C17 C5 C25 C22 GND Ground pins D13 D1 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME GGP, GJC PIN NO. GJL PIN NO. D19 D2 E3 D6 E24 D21 F2 D25 F24 D26 TYPE† DESCRIPTION GROUND PINS (CONTINUED) VSS G3 E3 G4 E24 G26 F4 J3 F23 L23 H1 L26 H26 M23 K1 N1 K26 N2 M1 N24 M26 N26 N1 P1 N2 P26 N25 R24 N26 T25 P1 U2 P2 U23 P25 V1 P26 V3 R1 Y3 R26 Y25 U1 AA3 U26 AA23 W1 AB23 W26 AC2 AA4 AC5 AA23 AC7 AB3 AC14 AB24 AC16 AC1 AD2 AC2 AD12 AC6 AD16 AC21 GND Ground pins AD20 AC25 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME GGP, GJC PIN NO. GJL PIN NO. AD25 AC26 AE1 AD5 AE3 AD22 TYPE† DESCRIPTION GROUND PINS (CONTINUED) VSS AE7 AE4 AE9 AE13 AE13 AE14 AE16 AE23 AE19 AF4 AE23 AF6 AE24 AF8 AE26 AF10 AF1 AF12 AF2 AF13 AF8 AF14 AF10 AF15 AF13 AF17 AF14 AF19 AF25 AF21 GND Ground pins AF26 AF23 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 development support Texas Instruments offers an extensive line of development tools for the ’C6000 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of ’C6000-based applications: Software Development Tools: Assembly optimizer Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler Hardware Development Tools: Extended development system (XDS) emulator (supports ’C6000 multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-related products from other companies in the industry. To receive TMS320 literature, contact the Literature Response Center at 800/477-8924. See Table 2 for a complete listing of development-support tools for the ’C6000. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 2. TMS320C6000 Development-Support Tools DEVELOPMENT TOOL PLATFORM PART NUMBER Software C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07 C Compiler/Assembler/Linker/Assembly Optimizer SPARC Solaris TMDX324655-07 Win32 TMDS3246851-07 SPARC Solaris TMDS3246551-07 Win32, Windows NT TMDX324016X-07 Simulator Simulator XDS510 Debugger/Emulation Software Hardware XDS510 Emulator† PC XDS510WS Emulator‡ SCSI TMDS00510 TMDS00510WS Software/Hardware EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201 EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201 † Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included. ‡ Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable. XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). This development flow follows. Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GGP, GJC, or GJL), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -200 is 200 MHz). Figure 5 provides a legend for reading the complete device name for any TMS320 family member. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 device and development-support tool nomenclature (continued) TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = C 6201 GGP (A) –200 DEVICE SPEED RANGE –100 MHz –150 MHz –167 MHz –200 MHz –233 MHz –250 MHz –300 MHz Experimental device Prototype device Qualified device MIL-STD-883C High Rel (non-883C) DEVICE FAMILY 320 = TMS320 family TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperature A = –40°C to 105°C, extended temperature PACKAGE TYPE† N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU = 144-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM DEVICE ’1x DSP: 10 14 15 16 17 ’2x DSP: 25 26 ’2xx DSP: 203 204 206 209 240 ’3x DSP: 30 31 32 ’4x DSP: 40 44 ’5x DSP: 50 51 52 53 56 57 541 542 543 545 546 548 ’54x DSP: † DIP PGA CC QFP TQFP BGA = = = = = = ’6x DSP: Dual-In-Line Package Pin Grid Array Chip Carrier Quad Flat Package Thin Quad Flat Package Ball Grid Array 6201 6201B 6202 6203 6211 6701 6711 Figure 5. TMS320 Device Nomenclature (Including TMS320C6201/TMS320C6201B) 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the ’C6000 CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for ’C6x devices and includes application program examples. The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the ’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis. The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used. TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of devices. The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for installing and operating the ’C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software documentation, application programming interface references, and hardware descriptions for the ’C62x McEVM. TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools and APIs to analyze embedded real-time DSP applications. Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer development environment to build and debug embedded real-time DSP applications. Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated development environment and software tools. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 documentation support (continued) The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to information pertaining to the TMS320 family, including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 clock PLL All of the ’C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. Note that for ’C6201, the EMI filter must be powered by the core voltage (2.5 V), and for ’C6201B, it must be powered by the I/O voltage (3.3 V). To configure the ’C62x PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter, a single clean power supply should power both the ’C62x device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input clock timing requirements. ’C6201 CLKOUT1 Frequency Range 40 – 200 MHz – 0 1 0 – ’C6201B CLKOUT1 Frequency Range 130 – 233 MHz ’C6201 CLKOUT1 Frequency Range 35 – 160 MHz – 0 0 1 – ’C6201B CLKOUT1 Frequency Range 65 – 200 MHz ’C6201 CLKOUT1 Frequency Range 25 – 135 MHz – 0 0 0 – ’C6201B CLKOUT1 Frequency Range 50 – 140 MHz EMI Filter PLLV 1 IN PLLF R1 EMIF CLKOUT1 CLKOUT 2 GND ’320C6201/C6201B PLLFREQ3 PLLFREQ2 PLLFREQ1 3 OUT 10 µF 0.1 µF (Bypass) PLLG C1 C2 CLKIN CLKMODE0 CLKMODE1 3.3 V 2.5 V 1 1 – MULT × 4 CLKOUT2 SSCLK SDCLK f(CLKOUT) = f(CLKIN) × 4 0 1 – Reserved 1 0 – Reserved 0 0 – MULT × 1 f(CLKOUT) = f(CLKIN) NOTES: A. For the ’C6201 CLKMODE x4, values for C1, C2, and R1 depend on CLKIN and CLKOUT frequencies. For the ’C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT. B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean supply and the PLLG and PLLF terminals should be tied together. C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a PLLFREQ value of 000b should be used for both the ’C6201 and the ’C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 010b for the ’C6201 or 001b for the ’C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved. D. EMI filter manufacturer TDK part number ACF451832-153-T E. For the ’C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. PLL Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 clock PLL (continued) Table 3. TMS320C6201 PLL Component Selection Table CYCLE TIME (ns) CLKMODE CLKIN (MHz) CLKOUT1 (MHz) R1 (Ω) C1 (µF) C2 (pF) TYPICAL LOCK TIME (µs)† 5 x4 50 200 16.9 0.15 2 700 59 5.5 x4 45.5 181.8 13.7 0.18 3 900 49 6 x4 41.6 166.7 17.4 0.15 3 300 68 6.5 x4 38.5 153.8 16.2 0.18 3 900 70 7 x4 35.7 142.9 15 0.22 3 900 72 7.5 x4 33.3 133.3 16.2 0.22 3 900 84 8 x4 31.3 125 14 0.27 4 700 77 8.5 x4 29.4 117.7 11.8 0.33 6 800 67 9 x4 27.7 111.1 11 0.39 6 800 68 9.5 x4 26.3 105.3 10.5 0.39 8 200 65 10 x4 25 100 10 0.47 8 200 68 † Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. Table 4. TMS320C6201B PLL Component Selection Table CLKMODE CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 (Ω) C1 (nF) C2 (pF) TYPICAL LOCK TIME (µs)† x4 12.5–50 50–200 25–100 60.4 27 560 75 † Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. power supply sequencing For the ’C6201 device, the 2.5-V supply powers the core and the 3.3-V supply powers the I/O buffers. For the ’C6201B device, the 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) for ’C6201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3 V Supply voltage range, CVDD (see Note 1) for ’C6201B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Operating case temperature range TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions ’C6201 ’C6201B MIN NOM MAX MIN NOM MAX UNIT CVDD Supply voltage 2.38 2.50 2.62 1.71 1.8 1.89 V DVDD Supply voltage 3.14 3.30 3.46 3.14 3.30 3.46 V VSS VIH Supply ground 0 0 0 0 0 0 V VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –12 mA IOL Low-level output current 12 12 mA TC Operating temperature O erating case tem erature High-level input voltage 2.0 Default 0 A version POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 2.0 90 V 0 90 –40 105 _C 27 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage DVDD = MIN, IOH = MAX VOL Low-level output voltage DVDD = MIN, IOL = MAX II IOZ Input current† ’C6201 MIN TYP ’C6201B MAX 2.4 MIN TYP MAX 2.4 UNIT V 0.6 0.6 V ±10 ±10 uA ±10 ±10 uA Off-state output current VI = VSS to DVDD VO = DVDD or 0 V IDD2V Supply current, CPU + CPU memory access‡ CVDD = NOM, CPU clock = 167 MHz 1860 380 mA IDD2V Supply current, peripherals§ CVDD = NOM, CPU clock = 167 MHz 200 240 mA IDD3V Supply current, I/O pins¶ DVDD = NOM, CPU clock = 167 MHz 100 90 mA Ci Input capacitance 10 Co Output capacitance 10 † TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡ Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle § Measured with average peripheral activity: 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs ¶ Measured with average I/O activity (30-pF load): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 pF 10 pF TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vref Output Under Test CT = 30 pF† IOH † Typical distributed load circuit capacitance Figure 7. TTL-Level Outputs signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 8. Input and Output Voltage Reference Levels for AC Timing Measurements POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN† (see Figure 9) (’C6201) ’C6201-167 NO. 1 2 3 4 ’C6201-200 CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 MIN MIN MIN MIN MAX MAX MAX UNIT MAX tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 24 6 20 5 ns Pulse duration, CLKIN high 9.8 2.7 8 2.25 ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 9.8 2.7 Transition time, CLKIN 5 8 2.25 0.6 5 ns 0.6 ns † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. timing requirements for CLKIN (see Figure 9) (’C6201B) ’C6201B-200 NO. 1 2 3 4 ’C6201B-233 CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 MIN MIN MIN MIN MAX MAX MAX MAX tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 20 5 17.2 4.3 ns Pulse duration, CLKIN high 8 2.25 6.9 1.9 ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 8 2.25 6.9 1.9 ns Transition time, CLKIN 5 1 0.6 5 4 2 CLKIN 3 4 Figure 9. CLKIN Timings PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 30 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0.6 ns TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1†‡ (see Figure 10) (’C6201) ’C6201-167 ’C6201-200 NO NO. 1 2 3 4 PARAMETER tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) CLKMODE = x4 CLKMODE = x1 MIN MIN MAX UNIT MAX P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 )+ 0.5 PH – 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 )+ 0.5 PL – 0.5 PL + 0.5 ns 0.6 ns Transition time, CLKOUT1 0.6 † PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. ‡ P = 1/CPU clock frequency in nanoseconds (ns). switching characteristics for CLKOUT1†‡ (see Figure 10) (’C6201B) ’C6201B NO. PARAMETER CLKMODE = x4 MIN 1 2 3 tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) UNIT CLKMODE = x1 MAX MIN MAX P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 ) + 0.5 PH – 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 ) + 0.5 PL – 0.5 PL + 0.5 ns 0.6 ns 4 Transition time, CLKOUT1 † PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. ‡ P = 1/CPU clock frequency in nanoseconds (ns). 0.6 1 4 2 CLKOUT1 3 4 Figure 10. CLKOUT1 Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT2† (see Figure 11) NO. 1 2 3 ’C6201-167 ’C6201-200 PARAMETER ’C6201B UNIT MIN MAX MIN MAX tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 2P – 0.7 2P + 0.7 2P – 0.7 2P + 0.7 ns Pulse duration, CLKOUT2 high P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns 0.6 ns 4 Transition time, CLKOUT2 † P = 1/CPU clock frequency in ns. 0.6 1 4 2 CLKOUT2 3 4 Figure 11. CLKOUT2 Timings SDCLK, SSCLK timing parameters SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 12)† NO. 1 ’C6201-167 ’C6201-200 PARAMETER MAX MIN MAX UNIT td(CKO1-SSCLK) Delay time, CLKOUT1 edge to SSCLK edge –1.2 1.6 (P/2) + 0.2 (P/2) + 4.2 ns 2 td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) –1.0 2.4 (P/2) – 1 (P/2) + 2.4 ns 3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge –1.0 2.4 (P/2) – 1 (P/2) + 2.4 ns –1.0 2.4 (P/2) – 1 (P/2) + 2.4 ns 4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge † P = 1/CPU clock frequency in ns. 32 MIN ’C6201B POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 13 and Figure 14) ’C6201-167 ’C6201-200 NO. MIN 6 7 10 MAX ’C6201B MIN UNIT MAX tsu(EDV-CKO1H) th(CKO1H-EDV) Setup time, read EDx valid before CLKOUT1 high 5.0 4.0 ns Hold time, read EDx valid after CLKOUT1 high 0 0.8 ns tsu(ARDY-CKO1H) th(CKO1H-ARDY) Setup time, ARDY valid before CLKOUT1 high 5.0 3.0 ns 11 Hold time, ARDY valid after CLKOUT1 high 0 1.8 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 13 and Figure 14) NO. 1 2 3 4 5 8 9 12 13 ’C6201-167 ’C6201-200 PARAMETER UNIT MIN MAX MIN MAX –1.0 5.0 –0.2 4.0 ns 4.0 ns td(CKO1H-CEV) td(CKO1H-BEV) Delay time, CLKOUT1 high to CEx valid td(CKO1H-BEIV) td(CKO1H-EAV) Delay time, CLKOUT1 high to BEx invalid td(CKO1H-EAIV) td(CKO1H-AOEV) Delay time, CLKOUT1 high to EAx invalid –1.0 Delay time, CLKOUT1 high to AOE valid –1.0 5.0 –0.2 4.0 ns td(CKO1H-AREV) td(CKO1H-EDV) Delay time, CLKOUT1 high to ARE valid –1.0 5.0 –0.2 4.0 ns 4.0 ns td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to EDx invalid Delay time, CLKOUT1 high to BEx valid 5.0 –1.0 Delay time, CLKOUT1 high to EAx valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 –0.2 5.0 Delay time, CLKOUT1 high to EDx valid 14 Delay time, CLKOUT1 high to AWE valid ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. 34 ’C6201B 4.0 –0.2 5.0 –1.0 –1.0 ns ns –0.2 5.0 –0.2 ns ns 4.0 ns TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 13. Asynchronous Memory Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 10 11 10 ARDY Figure 14. Asynchronous Memory Write Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15) ’C6201-167 ’C6201-200 NO. MIN 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) MAX ’C6201B MIN UNIT MAX Setup time, read EDx valid before SSCLK high 1.5 1.5 ns Hold time, read EDx valid after SSCLK high 1.2 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 15 and Figure 16) NO. ’C6201-167 ’C6201-200 PARAMETER MIN 1 tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 14 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 2 3 4 5 6 9 10 11 12 13 Output hold time, CEx valid after SSCLK high Output hold time, BEx invalid after SSCLK high Output hold time, EAx invalid after SSCLK high Output hold time, SSADS valid after SSCLK high Output hold time, SSOE valid after SSCLK high Output hold time, EDx invalid after SSCLK high MAX ’C6201B MIN UNIT MAX P–4 0.5P – 1.3 ns 0 0.5P – 2.3 ns P–4 0.5P – 1.3 ns 1 0.5P – 2.3 ns P–4 0.5P – 1.3 ns 1 0.5P – 2.3 ns P–3 0.5P – 1.3 ns 0 0.5P – 2.3 ns P–4 0.5P – 1.3 ns 0 0.5P – 2.3 ns P–4 0.5P – 1.3 ns 1 0.5P – 2.3 ns P–3 0.5P – 1.3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0 0.5P – 2.3 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times. 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 5 EA[21:2] 8 7 Q1 ED[31:0] 9 Q2 Q3 Q4 10 SSADS 11 12 SSOE SSWE Figure 15. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 D3 14 D4 5 EA[21:2] 13 ED[31:0] D1 D2 9 10 15 16 SSADS SSOE SSWE Figure 16. SBSRAM Write Timing (Full-Rate SSCLK) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17) (’C6201) NO NO. 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) ’C6201-167 ’C6201-200 MIN MIN MAX MAX UNIT Setup time, read EDx valid before SSCLK high 3.6 3.6 ns Hold time, read EDx valid after SSCLK high 1.2 1.2 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 17 and Figure 18) (’C6201) NO NO. 1 ’C6201-167 PARAMETER MIN tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 14 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 2 3 4 5 6 9 10 11 12 13 Output hold time, CEx valid after SSCLK high Output hold time, BEx invalid after SSCLK high Output hold time, EAx invalid after SSCLK high Output hold time, SSADS valid after SSCLK high Output hold time, SSOE valid after SSCLK high Output hold time, EDx invalid after SSCLK high 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MAX ’C6201-200 MIN MAX UNIT P – 3.4 P – 3.4 ns P–5 P–4 ns P – 3.3 P – 2.3 ns P–5 P–4 ns P – 3.3 P – 2.3 ns P–5 P–4 ns P – 3.3 P – 2.3 ns P–5 P–4 ns P – 3.3 P – 3.1 ns P–5 P–4 ns P – 3.3 P – 2.3 ns P–5 P–4 ns P – 3.3 P – 2.3 ns P–5 P–4 ns TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17) (’C6201B) ’C6201B-200 NO NO. 7 8 MIN tsu(EDV-SSCLKH) th(SSCLKH-EDV) MAX ’C6201B-233 MIN MAX UNIT Setup time, read EDx valid before SSCLK high 2.5 1.1 ns Hold time, read EDx valid after SSCLK high 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 17 and Figure 18) (’C6201B) NO NO. 1 2 3 4 5 6 PARAMETER tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high Output hold time, CEx valid after SSCLK high ’C6201B-200 ’C6201B-233 MIN MIN MAX MAX UNIT 1.5P – 3 1.5P – 2.2 ns 0.5P – 1.5 0.5P – 1.1 ns 1.5P – 3 1.5P – 2.2 ns 0.5P – 1.5 0.5P – 1.1 ns 1.5P – 3 1.5P – 2.2 ns Output hold time, EAx invalid after SSCLK high 0.5P – 1.5 0.5P – 1.1 ns 1.5P – 3 1.5P – 2.2 ns 0.5P – 1.5 0.5P – 1.1 ns 1.5P – 3 1.5P – 2.2 ns 0.5P – 1.5 0.5P – 1.1 ns 1.5P – 3 1.5P – 2.2 ns 0.5P – 1.5 0.5P – 1.1 ns 1.5P – 3 1.5P – 2.2 ns Output hold time, BEx invalid after SSCLK high 9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 12 toh(SSCLKH-OEV) tosu(EDV-SSCLKH) Output hold time, SSOE valid after SSCLK high 13 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high Output setup time, EDx valid before SSCLK high 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 1.5 0.5P – 1.1 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 Q3 9 Q4 10 SSADS 11 12 SSOE SSWE Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 Q1 Q2 Q3 Q4 6 13 14 ED[31:0] 9 10 15 16 SSADS SSOE SSWE Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK) 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201) NO NO. 7 8 tsu(EDV-SDCLKH) th(SDCLKH-EDV) ’C6201-167 ’C6201-200 MIN MIN MAX MAX UNIT Setup time, read EDx valid before SDCLK high 3.5 1.5 ns Hold time, read EDx valid after SDCLK high 1.2 1.2 ns switching characteristics for synchronous DRAM cycles† (see Figure 19–Figure 24) (’C6201) NO NO. 1 PARAMETER ’C6201-167 ’C6201-200 MIN MIN MAX MAX UNIT tosu(CEV-SDCLKH) toh(SDCLKH-CEV) Output setup time, CEx valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, CEx valid after SDCLK high P – 4.5 P – 3.5 ns tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) Output setup time, BEx valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, BEx invalid after SDCLK high P – 4.5 P – 3.5 ns tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) Output setup time, EAx valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, EAx invalid after SDCLK high P – 4.5 P – 3.5 ns tosu(SDCAS-SDCLKH) toh(SDCLKH-SDCAS) Output setup time, SDCAS valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, SDCAS valid after SDCLK high P – 4.5 P – 3.5 ns tosu(EDV-SDCLKH) toh(SDCLKH-EDIV) Output setup time, EDx valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, EDx invalid after SDCLK high P – 4.5 P – 3.5 ns tosu(SDWE-SDCLKH) toh(SDCLKH-SDWE) Output setup time, SDWE valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, SDWE valid after SDCLK high P – 4.5 P – 3.5 ns tosu(SDA10V-SDCLKH) toh(SDCLKH-SDA10IV) Output setup time, SDA10 valid before SDCLK high P – 3.5 P – 2.5 ns Output hold time, SDA10 invalid after SDCLK high P – 4.5 P – 3.5 ns tosu(SDRAS-SDCLKH) toh(SDCLKH-SDRAS) Output setup time, SDRAS valid before SDCLK high P – 3.5 P – 2.5 ns 18 Output hold time, SDRAS valid after SDCLK high P – 4.5 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. P – 3.5 ns 2 3 4 5 6 9 10 11 12 13 14 15 16 17 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201B) ’C6201B-200 NO NO. 7 8 MIN tsu(EDV-SDCLKH) th(SDCLKH-EDV) Setup time, read EDx valid before SDCLK high Hold time, read EDx valid after SDCLK high MAX ’C6201B-233 MIN MAX UNIT 0.5 0.5 ns 3 3 ns switching characteristics for synchronous DRAM cycles† (see Figure 19–Figure 24) (’C6201B) NO NO. 1 2 3 4 5 6 PARAMETER tosu(CEV-SDCLKH) toh(SDCLKH-CEV) Output setup time, CEx valid before SDCLK high tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) Output setup time, BEx valid before SDCLK high tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) Output setup time, EAx valid before SDCLK high ’C6201B-200 ’C6201B-233 MIN MIN MAX MAX UNIT 1.5P – 3.5 1.5P – 2.4 ns 0.5P – 1 0.5P – 0.6 ns 1.5P – 3.5 1.5P – 2.4 ns 0.5P – 1 0.5P – 0.6 ns 1.5P – 3.5 1.5P – 2.4 ns Output hold time, EAx invalid after SDCLK high 0.5P – 1 0.5P – 0.6 ns Output setup time, SDCAS valid before SDCLK high 1.5P – 3.5 1.5P – 2.4 ns Output hold time, CEx valid after SDCLK high Output hold time, BEx invalid after SDCLK high 9 tosu(SDCAS-SDCLKH) 10 Output hold time, SDCAS valid after SDCLK high 0.5P – 1 0.5P – 0.6 ns 11 toh(SDCLKH-SDCAS) tosu(EDV-SDCLKH) Output setup time, EDx valid before SDCLK high 1.5P – 3.5 1.5P – 2.4 ns 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high 0.5P – 1 0.5P – 0.6 ns 13 tosu(SDWE-SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P – 3.5 1.5P – 2.4 ns 14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high 0.5P – 1 0.5P – 0.6 ns 15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P – 3.5 1.5P – 2.4 ns 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P – 1 0.5P – 0.6 ns 17 tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P – 3.5 1.5P – 2.4 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P – 1 0.5P – 0.6 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ SDCLK 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 SDA10 SDRAS SDCAS SDWE Figure 19. Three SDRAM Read Commands WRITE WRITE WRITE SDCLK 1 2 CEx 3 BE[3:0] 4 BE1 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS SDCAS SDWE Figure 20. Three SDRAM WRT Commands POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 18 SDRAS SDCAS SDWE Figure 21. SDRAM ACTV Command DCAB SDCLK 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS 13 SDWE Figure 22. SDRAM DCAB Command 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 14 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS 9 10 SDCAS SDWE Figure 23. SDRAM REFR Command MRS SDCLK 1 2 5 6 CEx BE[3:0] EA[15:2] MRS Value ED[31:0] SDA10 17 18 9 10 13 14 SDRAS SDCAS SDWE Figure 24. SDRAM MRS Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles† (see Figure 25) ’C6201-167 ’C6201-200 NO. MIN 1 2 tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) ’C6201B MAX MIN Setup time, HOLD high before CLKOUT1 high 5 1 Hold time, HOLD low after CLKOUT1 high 2 4 UNIT MAX ns ns † HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. switching characteristics for the HOLD/HOLDA cycles‡ (see Figure 25) NO. ’C6201-167 ’C6201-200 PARAMETER MIN 3 4 5 6 7 8 tR(HOLDL-BHZ) tR(BHZ-HOLDAL) Response time, HOLD low to EMIF Bus high impedance Response time, EMIF Bus high impedance to HOLDA low tR(HOLDH-HOLDAH) Response time, HOLD high to HOLDA high td(CKO1H-HOLDAL) Delay time, CLKOUT1 high to HOLDA valid td(CKO1H-BHZ) td(CKO1H-BLZ) Delay time, CLKOUT1 high to EMIF Bus high impedance¶ Delay time, CLKOUT1 high to EMIF Bus low impedance¶ ’C6201B MIN 4P MAX § P 2P 4P UNIT 4P MAX § ns P 2P ns 6P 4P 7P ns –1 5 1 8 ns –1 5 3 11 ns –1 5 3 11 ns 9 tR(HOLDH-BLZ) Response time, HOLD high to EMIF Bus low impedance 3P 5P 3P 6P ns ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. ¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. DSP Owns Bus External Requester DSP Owns Bus 5 9 4 3 CLKOUT1 2 2 1 1 HOLD 6 6 HOLDA 7 8 EMIF Bus† ’C62x Ext Req ’C62x † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 25. HOLD/HOLDA Timing 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 RESET TIMING timing requirements for reset (see Figure 26) ’C6201-167 ’C6201-200 NO. MIN 1 tw(RST) Width of the RESET pulse (PLL stable)† MAX 10 ’C6201B MIN UNIT MAX CLKOUT1 cycles 10 Width of the RESET pulse (PLL needs to sync up)‡ 250 250 µs † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. ‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. switching characteristics during reset§¶ (see Figure 26) NO. ’C6201-167 ’C6201-200 PARAMETER MIN 2 tR(RST) Response time to change of value in RESET signal 3 td(CKO1H-CKO2IV) td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 invalid td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK invalid td(CKO1H-SSCKIV) td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK invalid td(CKO1H-LOWIV) td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group invalid td(CKO1H-HIGHIV) td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group invalid td(CKO1H-ZHZ) td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group high impedance 4 5 6 7 8 9 10 11 12 13 14 § Low group consists of: High group consists of: Z group consists of: 2 MIN –1 –1 –1 –1 –1 10 Delay time, CLKOUT1 high to high group valid 10 10 ns ns 10 –1 10 ns ns –1 –1 ns ns 10 –1 –1 ns ns 10 10 Delay time, CLKOUT1 high to low group valid ns 10 10 Delay time, CLKOUT1 high to SSCLK valid CLKOUT1 cycles –1 10 Delay time, CLKOUT1 high to SDCLK valid UNIT MAX 2 –1 Delay time, CLKOUT1 high to CLKOUT2 valid Delay time, CLKOUT1 high to Z group valid MAX ’C6201B ns ns 10 ns IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 HINT EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ¶ HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 CLKOUT2 SDCLK SSCLK LOW GROUP†‡ HIGH GROUP†‡ Z GROUP†‡ † Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 HINT EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ‡ HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. Figure 26. Reset Timing 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles†‡ (see Figure 27) ’C6201-167 ’C6201-200 NO. MIN 2 3 tw(ILOW) tw(IHIGH) MAX ’C6201B MIN Width of the interrupt pulse low 2P 2P Width of the interrupt pulse high 2P 2P UNIT MAX ns ns † Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. switching characteristics during interrupt response cycles§ (see Figure 27) NO. 1 PARAMETER tR(EINTH-IACKH) td(CKO2L-IACKV) Response time, EXT_INTx high to IACK high 4 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid ’C6201-167 ’C6201-200 ’C6201B MIN MAX MIN 10 –4 – 0.5P 9P Delay time, CLKOUT2 low to IACK valid 0 9P 10 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid 0 § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. UNIT MAX ns 6 – 0.5P ns 6 – 0.5P ns –4 – 0.5P ns 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 Interrupt Number INUMx Figure 27. Interrupt Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30, and Figure 31) ’C6201-167 ’C6201-200 NO. MIN 1 2 3 4 10 11 12 tsu(SEL-HSTBL) th(HSTBL-SEL) Setup time, select signals§ valid before HSTROBE low Hold time, select signals§ valid after HSTROBE low tw(HSTBL) tw(HSTBH) Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals§ valid before HAS low tsu(SEL-HASL) th(HASL-SEL) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) 19 MAX 1 ’C6201B MIN UNIT MAX 4 ns 2 2 ns 2P 2P ns 2P 2P ns 1 4 ns Hold time, select signals§ valid after HAS low 2 2 ns Setup time, host data valid before HSTROBE high 1 3 ns Hold time, host data valid after HSTROBE high 1 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE shoul not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 1 1 ns Setup time, HAS low before HSTROBE low 2 2 ns Hold time, HAS low after HSTROBE low 2 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics during host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30, and Figure 31) NO. ’C6201-167 ’C6201-200 PARAMETER MIN 5 MAX ’C6201B MIN UNIT MAX Delay time, HCS to HRDY¶ 1 7 1 9 ns Delay time, HSTROBE low to HRDY high# 3 12 3 12 ns Output hold time, HD low impedance after HSTROBE low for an HPI read 4 6 td(HCS-HRDY) td(HSTBL-HRDYH) 7 toh(HSTBL-HDLZ) 8 td(HDV-HRDYL) toh(HSTBH-HDV) Delay time, HD valid to HRDY low P–2 P P–3 P+3 ns 9 Output hold time, HD valid after HSTROBE high 3 12 2 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 12 3 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12 2 12 ns 4 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 12 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st Half-Word 5 2nd Half-Word 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 28. HPI Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE† 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 6 8 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Read Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 12 12 13 13 HBE[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 14 HSTROBE† HCS 12 12 13 13 HD[15:0] (input) 1st Half-Word 5 17 2nd Half-Word 5 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Write Timing (HAS Not Used, Tied High) HAS 12 19 13 12 19 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE† 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 31. HPI Write Timing (HAS Used) 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡(see Figure 32) ’C6201-167 ’C6201-200 NO. MIN 2 3 tc(CKRX) tw(CKRX) MAX ’C6201B MIN UNIT MAX Cycle time, CLKR/X CLKR/X ext 2P 2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext ns 5 tsu(FRH-CKRL) (FRH CKRL) Setup time, time external FSR high before CLKR low 6 th(CKRL-FRH) h(CKRL FRH) Hold time, time external FSR high after CLKR low 7 tsu(DRV-CKRL) (DRV CKRL) Setup time, time DR valid before CLKR low 8 th(CKRL-DRV) h(CKRL DRV) Hold time time, DR valid after CLKR low 10 tsu(FXH-CKXL) (FXH CKXL) Setup time, time external FSX high before CLKX low 11 th(CKXL-FXH) h(CKXL FXH) Hold time, time external FSX high after CLKX low P–1 P–1 CLKR int 13 9 CLKR ext 4 2 CLKR int 7 6 CLKR ext 3 3 CLKR int 10 8 CLKR ext 1 0 CLKR int 4 3 CLKR ext 4 4 CLKX int 13 9 CLKX ext 4 2 CLKX int 7 6 CLKX ext 3 3 ns ns ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡§ (see Figure 32) NO. PARAMETER ’C6201-167 ’C6201-200 ’C6201B MIN MAX MIN MAX 4 15 3 10 UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶ C + 1¶ C – 1.3¶ C + 1¶ ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2 4 –2 3 ns 9 td(CKXH-FXV) d(CKXH FXV) Delay y time,, CLKX high g to internal FSX valid 12 tdis(CKXH-DXHZ) di (CKXH DXHZ) Disable time,, DX high g impedance following last data bit from CLKX high 13 td(CKXH-DXV) d(CKXH DXV) Delay time, time CLKX high to DX valid 14 td(FXH-DXV) d(FXH DXV) 2P ns ns CLKX int 0 4 –2 3 CLKX ext 3 16 3 9 CLKX int 0 4 –1 4 CLKX ext 3 16 3 9 CLKX int 0 4 –1 4 CLKX ext 3 16 3 9 Delay time, FSX high to DX valid FSX int –2 4 –1 3 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 3 16 3 9 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 32. McBSP Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 33) ’C6201-167 ’C6201-200 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) MIN UNIT MAX Setup time, FSR high before CLKS high 4 4 ns Hold time, FSR high after CLKS high 4 4 ns CLKS 1 2 FSR External CLKR/X (no need to resync) CLKR/X (needs resync) Figure 33. FSR Timing When GSYNC = 1 56 MAX ’C6201B POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201) ’C6201-167 ’C6201-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low UNIT SLAVE MAX MIN MAX 12 2 – 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201) ’C6201-167 ’C6201-200 NO NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX MIN T–2 T+3 ns L–2 L+3 ns –2 4 L–2 L+3 3P + 4 MAX 5P + 17 ns ns P+4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 4 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201B) ’C6201B NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) (’C6201B) ’C6201B NO. MASTER§ PARAMETER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T–2 T+3 L–2 L+3 –2 4 L–2 L+3 MIN MAX ns ns 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201) ’C6201-167 ’C6201-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201) ’C6201-167 ’C6201-200 NO NO. PARAMETER MASTER§ MIN 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) tdis(CKXL-DXHZ) 1 6 UNIT SLAVE MAX MIN MAX L–2 L+3 ns T–2 T+3 ns Delay time, CLKX low to DX valid –2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from CLKX low –2 4 3P + 4 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H–2 H+4 2P + 4 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201B) ’C6201B NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35) (’C6201B) ’C6201B NO. MASTER§ PARAMETER UNIT SLAVE MIN MAX L–2 L+3 MIN MAX 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# T–2 T+3 3 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 4 3P + 4 5P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low –2 4 3P + 3 5P + 17 ns 1 ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H–2 H+4 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201) ’C6201-167 ’C6201-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201) ’C6201-167 ’C6201-200 NO NO. PARAMETER MASTER§ MIN 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MAX MIN MAX T–2 T+3 ns H–2 H+3 ns –2 4 H–2 H+3 3P + 4 5P + 17 ns ns P+4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 4 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201B) ’C6201B NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36) (’C6201B) ’C6201B NO. MASTER§ PARAMETER 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T–2 T+3 H–2 H+3 –2 4 H–2 H+3 MIN MAX ns ns 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201) ’C6201-167 ’C6201-200 NO NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low UNIT SLAVE MAX MIN MAX 12 2 – 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201) ’C6201-167 ’C6201-200 NO NO. PARAMETER MASTER§ UNIT SLAVE MIN MAX MIN MAX H–2 H+3 ns T–2 T+1 ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 4 3P + 4 5P + 17 ns tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high –2 4 3P + 4 5P + 17 ns 1 6 7 td(FXL-DXV) Delay time, FSX low to DX valid L–2 L+4 2P + 4 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201B) ’C6201B NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37) (’C6201B) ’C6201B NO. MASTER§ PARAMETER UNIT SLAVE MIN MAX H–2 H+3 MIN MAX 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# T–2 T+1 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 4 3P + 4 5P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high –2 4 3P + 3 5P + 17 ns 1 ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L–2 L+4 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 38) NO. 1 ’C6201-167 ’C6201-200 PARAMETER td(CKO1H-DMACV) ’C6201B UNIT MIN MAX MIN MAX 2 7 2 10 Delay time, CLKOUT1 high to DMAC valid ns CLKOUT1 1 1 DMAC[0:3] Figure 38. DMAC Timing timing requirements for timer inputs† (see Figure 39) ’C6201-167 ’C6201-200 NO. MIN 1 tw(TINP) Pulse duration, TINP high or low † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ’C6201B MAX 2P MIN UNIT MAX 2P ns switching characteristics for timer outputs (see Figure 39) NO. 2 ’C6201-167 ’C6201-200 PARAMETER td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid ’C6201B UNIT MIN MAX MIN MAX 3 9 2 9 ns CLKOUT1 1 TINP 2 2 TOUT Figure 39. Timer Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs (see Figure 40) NO. 1 ’C6201-167 ’C6201-200 PARAMETER td(CKO1H-PDV) MAX MIN MAX 3 5 2 9 CLKOUT1 1 1 Figure 40. Power-Down Timing 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT MIN Delay time, CLKOUT1 high to PD valid PD ’C6201B ns TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 41) ’C6201, ’C6201B NO. MIN 1 tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 3 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high UNIT MAX 50 Setup time, TDI/TMS/TRST valid before TCK high ns 10 ns 5 ns switching characteristics for JTAG test port (see Figure 41) NO. 2 ’C6201, ’C6201B PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MIN MAX 0 15 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 41. JTAG Test-Port Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MECHANICAL DATA GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) 31,75 TYP 35,20 SQ 34,80 1,27 0,635 0,635 1,27 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 Heat Slug 1,70 MAX 0,91 NOM Seating Plane 0,90 0,60 0,30 M 0,50 MIN 0,15 4073223/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Thermally enhanced plastic package with metal heat slug (HSL). thermal resistance characteristics (S-PBGA package) NO 1 °C/W Air Flow LFPM† N/A RΘJC RΘJA Junction-to-case 0.94 Junction-to-free air 11.11 0 RΘJA RΘJA Junction-to-free air 9.61 100 Junction-to-free air 8.24 250 RΘJA Junction-to-free air † LFPM = Linear Feet Per Minute 7.10 500 2 3 4 5 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MECHANICAL DATA GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY 35,20 SQ 34,80 33,20 SQ 32,80 31,75 TYP 1,27 21,00 NOM 0,635 1,27 0,635 21,00 NOM AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 Heat Slug 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 See Note E 3,50 MAX 1,00 NOM Seating Plane 0,90 0,60 ∅ 0,10 M 0,50 MIN 0,15 4173506-2/D 07/99 NOTES: A. B. C. D. E. F. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL). Flip chip application only Possible protrusion in this area, but within 3,50 max package height specification Falls within JEDEC MO-151/BAR-2 thermal resistance characteristics (S-PBGA package) NO 1 °C/W Air Flow LFPM† RΘJC RΘJA Junction-to-case 0.74 N/A Junction-to-free air 11.31 0 RΘJA RΘJA Junction-to-free air 9.60 100 Junction-to-free air 8.34 250 RΘJA Junction-to-free air † LFPM = Linear Feet Per Minute 7.30 500 2 3 4 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 TMS320C6201, TMS320C6201B DIGITAL SIGNAL PROCESSORS SPRS051F – JANUARY 1997 – REVISED AUGUST 1999 MECHANICAL DATA GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 25,20 SQ 24,80 25,00 TYP 1,00 16,30 NOM 0,50 AF AE AD AC AB AA Y 1,00 W V 16,30 NOM U T R P N M 0,50 L K J H G F E D C B A 1 3 2 Heat Slug 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 See Note E 3,50 MAX 1,00 NOM Seating Plane 0,70 0,50 ∅ 0,10 M 0,60 0,40 0,15 4173516-2/C 07/99 NOTES: A. B. C. D. E. F. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL). Flip chip application only Possible protrusion in this area, but within 3,50 max package height specification Falls within JEDEC MO-151/AAL-1 thermal resistance characteristics (S-PBGA package) NO 1 °C/W Air Flow LFPM† RΘJC RΘJA Junction-to-case 0.47 N/A Junction-to-free air 14.2 0 RΘJA RΘJA Junction-to-free air 12.3 100 Junction-to-free air 10.2 250 5 RΘJA Junction-to-free air † LFPM = Linear Feet Per Minute 8.6 500 2 3 4 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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