TMS320DM369 www.ti.com SPRT666 – APRIL 2013 TMS320DM369 Digital Media System-on-Chip (DMSoC) 1 TMS320DM369 Digital Media System-on-Chip (DMSoC) 1.1 Features 1 • Highlights – High-Performance Digital Media System-onChip (DMSoC) – 432-MHz ARM926EJ-S Clock Rate – Three Video Image Co-processors (Noise Filtering, CHDVICP, MJCP) Engines – Supports a Range of Encode, Decode, and Video Quality Operations – Video Processing Subsystem • HW Face Detect Engine • Resize Engine from 1/16x to 8x • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz • 4:2:2 (8-/16-bit) Interface • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output • 3 DACs for HD Analog Video Output • Hardware On-Screen Display (OSD) – Capable of 1080p 30fps H.264 video processing – Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan – 8 Different Boot Modes and Configurable Power-Saving Modes – Pin-to-pin and software compatible with DM365 – Extended temperature (-40ºC to 85ºC) available – 3.3-V and 1.8-V I/O, 1.35-V Core – 338-Pin Ball Grid Array at 65nm Process Technology • High-Performance Digital Media System-onChip (DMSoC) – 432-MHz ARM926EJ-S Clock Rate – 4:2:2 (8-/16-Bit) Interface – Capable of 1080p 30fps H.264 video processing – Pin compatible with DM365 processors – Fully Software-Compatible With ARM9™ – Extended temperature available for 432-MHz device • ARM926EJ-S™ Core – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – DSP Instruction Extensions and Single Cycle MAC – ARM® Jazelle® Technology – Embedded ICE-RT Logic for Real-Time Debug • ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache – 32K-Byte RAM – 16K-Byte ROM – Little Endian • Three Video Image Co-processors (Noise Filtering, HDVICP, MJCP) Engines – Support a Range of Encode and Decode Operations – H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1 – Noise Filtering Engine • Video Processing Subsystem – Front End Provides: • HW Face Detect Engine • Hardware IPIPE for Real-Time Image Processing – Resize Engine – Resize Images From 1/16x to 8x – Separate Horizontal/Vertical Control – Two Simultaneous Output Paths • IPIPE Interface (IPIPEIF) • Image Sensor Interface (ISIF) and CMOS Imager Interface • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz • Glueless Interface to Common Video Decoders • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface • Histogram Module • Lens distortion correction module (LDC) – Back End Provides: 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TMS320DM369 SPRT666 – APRIL 2013 • • • • • • • • • • • • • 2 Hardware On-Screen Display (OSD) Composite NTSC/PAL video encoder output • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output • 3 DACs for HD Analog Video Output • LCD Controller • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16Bit) Interface Analog-to-Digital Convertor (ADC) Power Management and Real Time Clock Subsystem (PRTCSS) – Real Time Clock 16-Bit Host-Port Interface (HPI) 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media – IEEE 802.3 Compliant – Supports Media Independent Interface (MII) – Management Data I/O (MDIO) Module Key Scan Voice Codec External Memory Interfaces (EMIFs) – DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O) – Asynchronous16-/8-bit Wide EMIF (AEMIF) • Flash Memory Interfaces – NAND (8-/16-bit Wide Data) – 16 MB NOR Flash, SRAM – OneNAND(16-bit Wide Data) Flash Card Interfaces – Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) – SmartMedia/xD Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2.0 High-Speed PHY that Supports – USB 2.0 High-Speed Device – USB 2.0 High-Speed Host (mini-host, supporting one external device) – USB On The Go (HS-USB OTG) Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) www.ti.com • One 64-Bit Watch Dog Timer • Two UARTs (One fast UART with RTS and CTS Flow Control) • Five Serial Port Interfaces (SPI) each with two Chip-Selects • One Master/Slave Inter-Integrated Circuit (I2C) Bus™ • One Multi-Channel Buffered Serial Port (McBSP) – I2S – AC97 Audio Codec Interface – S/PDIF via Software – Standard Voice Codec Interface (AIC12) – SPI Protocol (Master Mode Only) – Direct Interface to T1/E1 Framers – Time Division Multiplexed Mode (TDM) – 128 Channel Mode • Four Pulse Width Modulator (PWM) Outputs • Four RTO (Real Time Out) Outputs • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) • Boot Modes – On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI – AEMIF (NOR and OneNAND) • Configurable Power-Saving Modes • Crystal or External Clock Input (typically 19.2 MHz, 24 MHz, 27 MHz or 36 MHz) • Flexible PLL Clock Generators • Debug Interface Support – IEEE-1149.1 (JTAG™) Boundary-ScanCompatible – ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory – Device Revision ID Readable by ARM • 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch • 65nm Process Technology • 3.3-V and 1.8-V I/O, 1.35-V Internal • Community Resources – TI E2E Community – TI Embedded Processors Wiki TMS320DM369 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TMS320DM369 www.ti.com 1.2 SPRT666 – APRIL 2013 Description Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM369 DaVinci™ video processors from Texas Instruments Incorporated (TI). The DM369 is uniquely capable of running TI’s 3rd Generation Noise Filtering technology while achieving low light HD H.264 720p30 video compression and is pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM369 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs. Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM369. Along with multi-format HD video, the DM369 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM369 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design. Copyright © 2013, Texas Instruments Incorporated TMS320DM369 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback 3 TMS320DM369 SPRT666 – APRIL 2013 1.3 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the TMS320DM369 device. 16 Bit ISIF IPIPE Resizer 3A Face Det Lens Dist Video FE SDTV Analog Video 3Ch DAC EDMA DDR2 Controller Buffer Camera AFE NAND/SM Memory I/F Video OSD Encoder Digital RGB/YUV 8/16 Bit 16 Bit HPI Video BE VPSS 16-Bit DDR2 NAND/ OneNAND/ NOR Flash, SmartMedia/ xD Host CPU DMA/Data and Configuration Bus ARM INTC HDVICP MJCP ARM926EJ-S I-Cache RAM 16 KB 32 KB D-Cache ROM 8 KB 16 KB NOISE FILTERING ENGINE JTAG I/F CLOCK Ctrl PLL PRTCSS 19.2 MHz, 24 MHz 32.768 27 MHz or 36 MHz kHz USB2.0 HS w/OTG MMC/SD (x2) SPI (x5) UART (x2) I2C Timer (x4-64b) WDT (x1-64b) GIO PWM (x4) RTO McBSP EMAC ADC Key Scan Voice Codec System I/O Interface PMIC/ SW Figure 1-1. Functional Block Diagram 4 TMS320DM369 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TMS320DM369ZCE ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM369ZCE 570 TMS320DM369ZCED ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 85 DM369ZCED 570 TMS320DM369ZCEDF ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 85 DM369ZCEDF 570 TMS320DM369ZCEF ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM369ZCEF 570 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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