TN2425TG Low Threshold Dual N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► The Supertex TN2425TG is a dual low threshold enhancement mode (normally off) transistor utilizing a vertical DMOS structure and Supertex’s well proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Dual N-channel device Low threshold – 2.0V max. High input impedance Low input capacitance – 200pF Fast switching speeds Low caps ON resistance Free from secondary breakdown Low input and output leakage Applications ► ► ► ► ► ► Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Logic level interfaces – ideal for TTL and CMOS Solid state relays Medical ultrasound pulsers Analog switches General purpose line drivers Telecom switches Ordering Information Device Package Option 8-Lead SOIC (Narrow Body) TN2425TG TN2425TG BVDSS/BVDGS RDS(ON) (max) VGS(th) (max) ID(ON) (min) 250V 3.5Ω 2.0V 1.8A Absolute Maximum Ratings Pin Configuration Parameter Value Drain to source voltage BVDSS Drain to gate voltage BVDGS Gate to source voltage ±20V Thermal resistance, Junction to drain lead Operating and storage temperature Soldering temperature1 1 8 D1 G1 2 7 D1 S2 3 6 D2 G2 4 5 D2 50°C/W -55°C to +150°C +300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note 1. Distance of 1.6mm from case for 10 seconds. S1 8-Lead SOIC (top view) TN2425TG Electrical Characteristics (each device, T =25°C unless otherwise specified) J Symbol Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 250 - - V VGS = 0V, ID = 250µA VGS(th) Gate threshold voltage 0.6 - 2.0 V ΔVMatch Change in VGS(th) with temperature - - 25 mV ΔVGS(th) VGS(th) change with temperature - - -5.0 mV/OC VGS = VDS, ID = 1mA VGS = VDS, ID = 1mA, TA = 10OC - 80OC VGS = VDS, ID = 1mA Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V - - 10 µA VDS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC 1.5 - - 1.8 - - IGSS IDSS Zero gate voltage drain current ID(ON) ON-state drain current A Conditions VGS = 6.0V, VDS = 25V VGS = 10V, VDS = 25V RDS(ON) Static drain-to-source ON-state resistance - - 5.0 - - 3.5 RMATCH Channel to channel RDS(ON) matching - - 20 % VGS = 10V, ID = 400mA O ΔRDS(ON) GFS Change in RDS(ON) with temperature Forward transconductance GFSMATCH Ω VGS = 4.5V, ID = 300mA VGS = 10V, ID = 400mA - - 1.4 %/ C VGS = 10V, ID = 400mA 300 - - mmho VDS = 15V, ID = 400mA - - 5 % VDS = 15V, ID = 50mA - - 5 % VGS = 15V, ID = 1.50A pF VGS = 0V, VDS = 25V, f = 1MHz % VGS = 0V, VDS = 25V, f = 1MHz ns VDD = 25V, ID = 500mA, RGEN = 25Ω Channel to channel GFS matching CISS Input capacitance - 115 200 COSS Common source output capacitance - 30 100 CRSS Reverse transfer capacitance - 10 40 CISSMATCH Channel to channel CISS matching - - 25 COSSMATCH Channel to channel COSS matching - - 25 CRSSMATCH Channel to channel CRSS matching - - 25 Turn-ON delay time - 5 15 Rise time - 10 25 Turn-OFF delay time - 25 35 Fall time - 5 15 Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA td(ON) tr td(OFF) tf VSD trr Notes: 1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V PULSE GENERATOR 10% t(ON) td(ON) VDD t(OFF) tr 10% td(OFF) RGEN D.U.T. 10% INPUT 90% OUTP tF OUTPUT 0V RL 90% 2 TN2425TG Typical Performance Curves Output Characteristics Saturation Characteristics 2.5 4 VGS = 10V 8V 6V 3 ID (Amperes) ID (Amperes) VGS = 10V 8V 6V 5V 3.0 5 5V 2 4V 2.0 4V 1.5 1.0 3V 1 0.5 3V 2.5V 2.5V 0.0 0 0 10 20 30 40 0 50 2 4 VDS (Volts) 8 10 VDS (Volts) BVDSS Variation with Temperature Transconductance vs. Drain Current 1.2 1.0 V DS =15V BV @ 250A BVDSS (Normalized) T A =-55 OC 0.8 GFS (siemens) 6 T A =25 OC 0.6 T A =125 OC 0.4 1.1 1.0 0.9 0.2 0.0 0.0 0.5 1.0 1.5 0.8 -50 2.0 0 50 100 150 TJ ( C) O ID (Amperes) On Resistance vs. Drain Current Transfer Characteristics 10 3.0 TA = 25OC ID (Amperes) RDS(ON) (ohms) 2.5 VGS = 4.5V 8 6 4 TA = 125OC 2.0 TA = -55OC 1.5 1.0 VGS = 10V 2 VDS = 25V 0.5 0 0 1 2 3 4 0.0 5 0 2 4 6 VGS (Volts) ID (Amperes) 3 8 10 TN2425TG Typical Performance Curves (cont.) Capacitance vs. Drain Source Voltage VGS(TH) and RDS(ON) w/ Temperature 2.0 f = 1MHz 1.4 1.2 1.2 1.0 0.8 VGS(th) @ 1mA 150 C (picofarads) 1.5 1.6 RDS(ON) (normalized) RDS(ON) @ 10V, 0.5A 1.8 VGS(th) (normalized) 200 1.8 CISS 100 50 0.9 COSS 0.6 CRSS 0.4 -50 0 50 100 0.6 150 0 0 Gate Drive Dynamic Characteristics 10 ID = 480mA 8 VGS (volts) VDS=10V 6 VDS=40V 453pF 4 2 128pF 0 1.0 2.0 20 30 VDS (Volts) TJ (OC) 0.0 10 3.0 4.0 5.0 QG (nanocoulombs) 4 40 50 TN2425TG 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90 ± 0.10 8 6.00 ± 0.20 Note 2 3.90 ± 0.10 1 5° - 15° (4 PLCS) Top View 0.17 - 0.25 0.25 - 0.50 45° Note 2 1.25 MIN 1.75 MAX 0° - 8° 0.40 - 1.27 0.10 - 0.25 1.27BSC 0.31 - 0.51 End View Side View Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN2425TG NR111506 5