TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 Supply Current of 40 µA (Max) Battery Supply Current of 100 nA (Max) Supply Voltage Supervision Range: typical applications – Adjustable – Other Versions Available on Request Backup-Battery Voltage Can Exceed VDD Power-On Reset Generator With Fixed 100-ms Reset Delay Time Active-High and Active-Low Reset Output Chip-Enable Gating . . . 3 ns (at VDD = 5 V) Max Propagation Delay 10-Pin MSOP Package Temperature Range . . . –40°C to 85°C Fax Machines Set-Top Boxes Advanced Voice Mail Systems Portable Battery Powered Equipment Computer Equipment Advanced Modems Automotive Systems Portable Long-Time Monitoring Equipment Point of Sale Equipment DGS PACKAGE (TOP VIEW) description VOUT VDD GND MR CEIN The TPS3613-01 supervisory circuit monitors and controls processor activity by providing backupbattery switchover for data retention of CMOS RAM. 1 10 2 9 3 8 4 7 5 6 VBAT RESET SENSE RESET CEOUT ACTUAL SIZE 3,05 mm x 4,98 mm typical operating circuit Address Decoder Power Supply 0.1 µF Monitored Voltage CEIN Rx CEOUT VDD VBAT TPS3613 SENSE uC 8 RESET RESET Ry CE CMOS RAM VCC Address Bus Backup Battery CE CMOS RAM VCC RealTime Clock VCC 8 Data Bus 16 MR Switchover Capacitor Manual Reset VOUT GND 0.1 µF VCC GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 description (continued) During power on, RESET is asserted when the supply voltage (VDD or VBat) becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. The TPS3613-01 is available in a 10-pin MSOP package and is characterized for operation over a temperature range of –40°C to 85°C. PACKAGE INFORMATION TA –40°C to 85°C DEVICE NAME TPS3613–01DGSR† TPS3613–01DGST‡ MARKING AFK † The DGSR passive indicates tape and reel of 2500 parts. ordering information application specific versions TPS361 3 – 01 DGS R NOMINAL VOLTAGE, VNOM Adjustable DEVICE NAME TPS3613x01 DGS TPS3613x18 DGS‡ Reel Package Nominal Supply Voltage Functionality Family 1.8 V TPS3613x25 DGS‡ TPS3613x30 DGS‡ 2.5 V TPS3613x33 DGS‡ TPS3613x50 DGS‡ 3.3 V 3.0 V 5.0 V ‡ For the application specific versions please contact the local TI sales office for availability and lead-time. FUNCTION TABLE VDD > VBAT 0 MR CEIN 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 SENSE > VIT VOUT VBAT RESET RESET 0 1 DIS VBAT VBAT 0 1 DIS 0 1 DIS VBAT VDD 0 1 DIS 0 1 DIS VDD VDD 0 1 DIS 0 1 DIS VDD VDD 0 1 DIS 0 1 DIS VDD VDD 0 1 DIS 1 0 0 VDD VDD 1 0 1 0 1 DIS 0 1 DIS 0 VDD VDD 1 0 0 1 VDD 1 0 1 functional schematic 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CEOUT TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 TPS3613 VBAT + _ Switch Control VOUT VDD R RESET Logic + Timer MR + _ SENSE Reference Voltage or 1.15 V RESET RESET VOUT CEOUT CEIN timing diagram VDD VBAT VIT t CEIN CEOUT RESET td 15 µs 15 µs td td t t t Undefined Behavior Terminal Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 TERMINAL NAME I/O DESCRIPTION NO. CEIN 5 I Chip-enable input CEOUT 6 O Chip-enable output GND 3 I Ground MR 4 I Manual reset input RESET 7 O Active-high reset output RESET 9 O Active-low reset output SENSE 8 I Adjustable sense input VBAT 10 I Backup-battery input VDD VOUT 2 I Input supply voltage 1 O Supply output detailed description backup-battery switchover VDD – Normal Supply Voltage In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In order to allow the backup battery (e.g., 3.6-V lithium cells) to have a higher voltage than VDD, these supervisors will not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until VDD crosses VBAT, or when VDD rises above the reset threshold VIT. VOUT will connect to VDD through a 1-Ω (max) PMOS switch when VDD crosses the reset threshold. VDD>VBAT 1 VDD>VIT 1 VOUT VDD 1 0 0 1 VDD VDD 0 0 VBAT VDD – Mode VIT Hysteresis VBAT – Mode VBSW Hysteresis Undefined VBAT – Backup-Battery Supply Voltage Figure 1. VDD – VBAT Switchover 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 detailed description (continued) chip-enable signal gating The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during an under-voltage condition. The TPS3613 use a series transmission gate from CEIN to CEOUT. During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CEIN to CEOUT enables the TPS3613 device to be used with most processors. chip-enable signal gating (continued) The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted. During a power-down sequence when VDD crosses the reset threshold, the CE transmission gate will be disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low when reset is asserted, the CE transmission gate will be disabled same time when CEIN goes high, or 10 µs after reset asserts, whichever occurs first. This will allow the current write cycle to complete during power down. When the CE transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device propagation delay through the CE transmission gate depends on VOUT, the source impedance of the drive connected to CEIN, and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a low-output-impedance driver is used. In the disabled mode, the transmission gate is off and an active pullup connects CEOUT to VOUT. This pullup turns off when the transmission gate is enabled. VDD VBAT VIT t CEIN t VBAT CEOUT RESET td td t t Figure 2. Chip-Enable Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 detailed description (continued) VDD VDD VBAT SENSE 3.6 V SENSE TPS3613 50-Ω Cable 50 Ω CEIN CEOUT CL† 50 pF 50 Ω GND CL Includes load capacitance and scope probe capacitance. Figure 3. CE Propagation Delay Test Circuit absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Continuous output current at VOUT, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Continuous output current (all other pins), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h continuously. DISSIPATION RATING TABLE 6 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGS 424 mW 3.4 mW/°C 271 mW 220 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 recommended operating conditions Supply voltage, VDD Battery supply voltage, VBAT MIN MAX UNIT 1.65 5.5 V 5.5 V VDD + 0.3 V 1.5 Input voltage, VI 0 High-level input voltage, VIH 0.7 x VDD Low-level input voltage, VIL V 0.3 x VDD V Continuous output current at VOUT, IO 300 mA Input transition rise and fall rate at MR, ∆t/∆V 100 ns/V 1 V/µs 85 °C Slew rate at VDD or Vbat Operating free-air temperature range, TA –40 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 1.8 V IOH = –400 µA VDD = 3.3 V, IOH = –2 mA VDD = 5 V, IOH = –3 mA VDD = 1.8 V, IOH = –20 µA RESET RESET VOH Enable mode CEIN = VOUT VOUT = 3.3 V, IOH = –2.0 mA VOUT = 5 V, IOH = –5.0 mA VOUT – 0.3 V CEOUT Disable mode VOUT = 3.3 V, IOH = –0.5 mA VOUT – 0.4 V VDD = 1.8 V, VDD = 3.3 V, VDD = 5 V, VOUT = 1.8 V, RESET Low level output voltage Low-level CEOUT Enable mode CEIN = 0 V Vres Power-up reset voltage (see Note 2) Normal mode VOUT Battery backup mode Battery-backup VDD – 0.4 V IOUT = –7.5 mA VBAT = 3.3 V, VDD = 0 V NOTE 2: The lowest supply voltage at which RESET becomes active. tr,(VDD) ≥ 15 µs/V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 0.2 0.4 0.2 VOUT = 3.3 V, IOL = 2 mA VOUT = 5 V, IOL = 5 mA VDD > 1.1 V or VBAT > 1.1 V, IOL = 20 µA IOUT = –125 mA VDD = 3.3 V, VBAT = 0 V IOUT = –200 mA VDD = 5 V, VBAT = 0 V IOUT = –0.5 mA VBAT = 1.5 V, VDD = 0 V UNIT VOUT – 0.2 V IOL = 400 µA IOL = 2.0 mA IOL = 3.0 mA IOL = 1.0 mA IOUT = –8.5 mA, VDD = 1.8 V, VBAT = 0 V MAX VDD – 0.3 V CEOUT High-level High level out output ut voltage TYP VDD – 0.4 V VDD = 3.3 V, VDD = 5 V, VOUT = 1.8 V, RESET VOL IOH = –80 µA IOH = –120 µA IOH = –1 mA MIN VDD – 0.2 V V 0.3 0.4 V VDD – 50 mV VDD – 150 mV VDD – 200 mV V VBAT – 20 mV VBAT – 113 mV 7 TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS RDS(on) DS( ) VDD to VOUT on-resistance VBAT to VOUT on-resistance VIT Negative-going input threshold voltage (see Note 3) Vhys h Hysteresis IIH IIL High-level input current II Input current Low-level input current VDD supply current IBAT VBAT supply current Ilkg Ci CEIN leakage current TYP 1.13 1 8 15 1.15 1.17 1.1 V < VIT < 1.65 V 12 VBSW (see Note 4) VDD = 1.8 V 55 MR = 0.7 x VDD, VDD = 5.0 V MR MR = 0 V, VDD = 5.0 V VDD = 1.15 V VOUT = VDD VOUT = VBAT VOUT = VDD MAX 0.6 Sense SENSE IDD MIN VDD = 5 V VBAT = 3.3 V UNIT Ω V mV –33 –76 –110 –255 –25 25 nA 40 µA 40 –0.1 0.1 VOUT = VBAT Disable mode, VI < VDD 0.5 ±1 µA µA µA Input capacitance VI = 0 V to 5 V 5 pF NOTES: 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals. 4. For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT timing requirements at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C PARAMETER TEST CONDITIONS SENSE tw Pulse width MR VIH = VIT + 0.2 V, VSENSE > VIT + 0.2 V VIL = VIT – 0.2 V VIL = 0.3 x VDD, VIH = 0.7 x VDD MIN TYP MAX UNIT 6 µs 100 ns switching characteristics at RL = 1 MΩ, CL= 50 pF, TA = –40°C to 85°C PARAMETER td TEST CONDITIONS VSENSE ≥ VIT + 0.2 V, MR ≥ 0.7 x VDD, See timing diagram Delay time 50% RESET to 50% CEOUT tPLH Propagation g ((delay) y) time,, low-to-high-level output Propagation g ((delay) y) time, hi h t l high-to-low-level l l output t t Transition time 100 MAX 140 15 2 5 VSENSE ≥ VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD 0.1 1 VDD = 1.8 V 5 15 VDD = 3.3 V 1.6 5 VDD = 5 V 1 3 SENSE to RESET VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 2 5 VSENSE ≥ VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD 0.1 1 MR to RESET VDD to VBAT VIH = VBAT + 0.2 V, VIL = VBAT – 0.2 V, VBAT < VIT SENSE to RESET 50% CEIN to 50% CEOUT, CL = 50 pF F only (see Figure 3) (see Note 5) 50% CEIN to 50% CEOUT, CL = 50 pF only (see Figure 3) (see Note 5) NOTE 5: Assured by design 8 60 TYP VOUT = VIT VIL = VIT – 0.2 V, VIH = VIT + 0.2 V MR to RESET tPHL MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ms µs ns µs µs 3 µs TPS3613-01 ADJUSTABLE BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION SLVS340 – DECEMBER 2000 MECHANICAL DATA DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE 0,27 0,17 0,50 10 0,25 M 6 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°–6° 5 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073272/A 03/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated