TI TPS51220RHBT

TPS51220
www.ti.com
SLVS785 – OCTOBER 2007
Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller
FEATURES
1
• Input Voltage Range: 4.5V to 28V
• Output Voltage Range: 1V to 12V
• Selectable Light Load Operation
(Continuous / Auto Skip / Out-Of-Audio™ Skip)
• Programmable Droop Compensation
• Voltage Servo Adjustable Soft Start
• 200kHz to 1MHz Fixed Frequency PWM
• Selectable Current/D-CAP™ Mode Architecture
• 180° Phase Shift Between Channels
• Resistor or Inductor DCR Current Sensing
•
•
2
•
•
•
•
Powergood Output for Each Channel
OCL/OVP/UVP/UVLO Protections
(OVP Disable Option)
Thermal Shutdown (Non-Latch)
Output Discharge Function (Disable Option)
Integrated Boot Strap MOSFET Switch
QFN32 (RHB)
APPLICATIONS
•
•
Notebook Computer System and I/O Bus
Point of Load in LCD TV, MFP
DESCRIPTION
The TPS51220 is a dual synchronous buck regulator controller with 2 LDOs. It is optimized for 5V/3.3V system
controller, enabling designers to cost effectively complete 2-cells to 4-cells notebook system power supply. The
TPS51220 supports high efficiency, fast transient response and 99% duty cycle operation. It supports supply
input voltages ranging from 4.5V to 28V, and output voltages from 1V to 12V. Two types of control schemes can
be chosen depending on the application. Peak current mode supports stability operation with lower ESR
capacitor and output accuracy. The D-CAP mode supports fast transient response. The high duty (99%)
operation and the wide input/output voltage range supports flexible design for small mobile PCs and a wide
variety of other applications. The fixed frequency can be adjusted from 200kHz to 1MHz by a resistor, and each
channel runs 180° out of phase. The TPS51220 can also synchronize to the external clock, and the interleaving
ratio can be adjusted by its duty. The TPS51220 is available in the 32 pin 5x5 QFN package and is specified
from –40°C to 85°C.
TYPICAL APPLICATION CIRCUIT
VBAT
VBAT
C14
PGND
C24
Q12
PGND
VO1
2
V5SW
3
RF
4
EN1
5
PGOOD1
6
SKIPSEL1
7
CSP1
30
29
28
27
26
DRVL1
GND
DRVL2
VBST2
DRVH1
L2
C21
Q22
VREG5
31
SW1
1
32
VBST1
PGND
C22
PGND
GND
PGND
C11
PGND
Q21
C01
PGND
DRVH2
PGND
24
VIN 23
VBAT
R01
VREG3 22
C03
GND EN1
PGOOD1
SKIPSEL1
PGOOD2
VO1
12
13
14
15
CSN2 17
16
VREG5
GND
R23
R13
C02
R21
VO2
R12
GND
C23
VFB2
11
COMP2
10
TRIP
VREF2
9
EN
CSN1
FUNC
GND
GND
SKIPSEL2
R24
COMP1
8
R11
PGOOD2 20
SKIPSEL2 19
CSP2 18
VFB1
C13
VREG3
3.3V/10mA
EN2
PowerPAD
R14
EN
EN2 21
TPS51220RHB
(QFN32)
VO2
3.3 V
25
SW2
L1
VO1
5.0 V
VREG5
5V/100mA
Q11
C12
R22
GND
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Out-Of-Audio, D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS51220
www.ti.com
SLVS785 – OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
V5SW
+
4.7V/ 4.5V
+
1.25V
+
+
VREG5
4.7V/ 4.5V
VREG3
GND
V5OK
+
4.2V/ 3.8V
Ready
GND
+
THOK
150/ 140
Deg-C
VREF2
1.25V
GND
GND
CLK2
OSC
RF
CLK1
GND
1V +5%/ 10%
+
PGOOD1
Delay
+
1V -30%
1V - 5%/ 10%
+
GND
UVP
CLK1
Ready
+
FUNC
Fault2
OVP
SDN2
1V +15%
Fault1
COMP1
Ramp
Comp
CUR
VFB1
SDN1
+
+ PWM
VREG5
1V
+
Enable/
Soft-start
+
D-CAP
VFB-AMP
EN1
VREF2
VBST1
Ramp
Comp
+
Skip
DRVH1
CS-AMP
CSN1
SW1
+
OCP
+
CSP1
Control
Logic
XCON
VREG5
100mV
DRVL1
TRIP
Discharge
Control
GND
GND
100mV
VREF2
N-OCP
+
GND
OOA
Ctrl
GND
SKIPSEL1
Channel-1 Switcher shown
2
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SLVS785 – OCTOBER 2007
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VIN
–0.3 to 30
V
VBST1, VBST2
–0.3 to 35
V
–0.3 to 7
V
–2 to 30
V
CSP1, CSP2, CSN1, CSN2
–1 to 13.5
V
EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2, FUNC
–0.3 to 7
V
V5SW
–0.3 to 7
V
–7 to 7
V
DRVH1, DRVH2
–2 to 35
V
DRVH1, DRVH2 (3)
–0.3 to 7
V
DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2,
PGOOD1, PGOOD2
–0.3 to 7
V
VBST1, VBST2
VI
Input voltage range
(3)
SW1, SW2
(2)
V5SW (to VREG5) (4)
VO
Output voltage range (2)
–0.3 to 3.6
V
TJ
Operating junction temperature range
–40 to 125
°C
Tstg
Storage temperature
–55 to 150
°C
VREG3
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the corresponding SW terminal.
When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.
DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
32 pin RHB
2.2 W
23 mW/°C
0.9 W
RECOMMENDED OPERATING CONDITIONS
MIN
VSS
VI
VO
TA
Supply voltage
I/O voltage
VIN
TYP
MAX
4.5
28
V5SW
–0.8
6
VBST1, VBST2, DRVH1, DRVH2
–0.1
33
DRVH1, DRVH2 (wrt SW1, 2)
–0.1
6
SW1, SW2
–1.6
28
CSP1, CSP2, CSN1, CSN2
–0.8
13
EN, EN1, EN2, VFB1, VFB2, TRIP, DRVL1, DRVL2, COMP1, COMP2,
VREG5, RF, VREF2, PGOOD1, PGOOD2, SKIPSEL1, SKIPSEL2,
FUNC
–0.1
6
VREG3
–0.1
3.5
–40
85
Operating free-air temperature
UNIT
V
V
°C
ORDERING INFORMATION
(1)
TA
PACKAGE (1)
-40°C to 85°C
Plastic Quad Flat Pack
(32 Pin QFN)
ORDERABLE PART
NUMBER
TRANSPORT MEDIA
TPS51220RHBT
Tape and Reel
250
TPS51220RHBR
Tape and Reel
3000
QUANTITY
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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SLVS785 – OCTOBER 2007
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
7
15
μA
80
120
μA
SUPPLY CURRENT
I(VINSDN)
VIN shutdown current
VIN shutdown current, TA = 25°C,
No Load, EN = 0V, V5SW = 0 V
I(VINSTBY)
VIN Standby Current
VIN shutdown current, TA = 25°C, No Load,
EN1 = EN2 = V5SW = 0 V
I(VBATSTBY)
Vbat Standby Current
Vbat standby current, TA = 25°C, No Load
SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V (1)
I(V5SW)
V5SW Supply Current
V5SW current, TA = 25°C, No Load,
ENx = 5V, VFBx = 1.05 V
500
μA
TRIP = 5 V
1.2
mA
TRIP = 0 V
1.4
mA
VREF2 OUTPUT
V(VREF2)
VREF2 Output Voltage
I(VREF2) < ±10 μA, TA = 25°C
1.98
2.00
2.02
I(VREF2) < ±100 μA, 4.5V < VIN < 25 V
1.97
2.00
2.03
V
VREG3 OUTPUT
V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C
3.279
3.313
3.347
V(VREG3)
VREG3 Output Voltage
V5SW = 0 V, 0 mA < I(VREG3) < 10 mA,
5.5 V < VIN < 25 V
3.135
3.300
3.400
I(VREG3)
VREG3 Output Current
VREG3 = 3 V
10
15
20
V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C
4.99
5.04
5.09
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
6 V < VIN < 25 V
4.90
5.03
5.15
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
5.5 V < VIN < 25 V
4.50
5.03
5.15
V5SW = 0 V, VREG5 = 4.5 V
100
150
200
V5SW = 5 V, VREG5 = 4.5 V
200
300
400
Turning on
4.55
4.7
4.8
Hysteresis
0.15
0.20
0.25
V
mA
VREG5 OUTPUT
V(VREG5)
VREG5 Output Voltage
V
V
I(VREG5)
VREG5 Output Current
mA
V(THV5SW)
Switchover Threshold
td(V5SW)
Switchover Delay
Turning on
7.7
ms
R(V5SW)
5V SW Ron
I(VREG5) = 100 mA
0.5
Ω
V(VFB)
VFB Regulation Voltage
Tolerance
TA = 25°C, No Load
I(VFB)
VFB Input Current
VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C
R(Dischg)
CSNx Discharge
Resistance
ENx = 0 V, CSNx = 0.5 V, TA = 25°C
V
OUTPUT
TA = –40°C to 85°C , No Load
0.9925
1.000
1.0075
0.990
1.000
1.010
–50
20
V
50
nA
40
Ω
VOLTAGE TRANSCONDUCTANCE AMPLIFIER
Gain
VID
Differential Input Voltage
Range
I(COMPSINK)
COMP Maximum Sink
Current
COMPx = 1.8 V
33
μA
I(COMPSRC)
COMP Maximum Source
Current
COMPx = 1.8 V
–33
μA
(1)
4
TA = 25°C
μS
Gmv
500
–30
30
mV
Specified by design. Detail external condition follows application circuit of Figure 54.
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SLVS785 – OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT AMPLIFIER
GC
Gain
VIC
Common mode Input
Voltage Range
VID
Differential Input Voltage
Range
TRIP = 0V/2V, CSN = 5V, TA = 25°C (2)
3.333
TRIP = 3.3V/5V, CSN = 5V, TA = 25°C (2)
1.667
TA = 25°C
0
13
V
–75
75
mV
POWERGOOD
PG in from lower
92.5%
95%
97.5%
PG in from higher
102.5%
105%
107.5%
V(THPG)
PG threshold
I(PG)
PG sink Current
PGOOD = 0.5 V
t(PGDLY)
PGOOD Delay
Delay for PG in
t(SSDYL)
Soft Start Delay
Delay for Soft Start, ENx = Hi to SS-ramp starts
140
μs
t(SS)
Soft Start Time
Internal Soft Start
800
μs
PG hysteresis
5%
5
0.8
1
mA
1.2
ms
SOFTSTART
FREQUENCY AND DUTY CONTROL
f(SW)
Switching Frequency
Rf = 330 kΩ
273
303
333
Lo to Hi
0.7
1.3
2
V(THRF)
RF Threshold
f(SYNC)
Sync Input Frequency
Range (2)
tONmin
Minimum On Time
V(DRVH) = 90% to 10%, No Load
tOFFmin
Minimum Off Time
V(DRVH) = 10% to 90%, No Load
tD
Dead time
Hysteresis
0.2
200
kHz
V
V
1000
kHz
120
150
ns
290
440
ns
DRVH-off to DRVL-on
10
30
50
ns
DRVL-off to DRVH-on
30
40
70
ns
(2)
V(DTH)
DRVH-off threshold
DRVH to GND
V(DTL)
DRVL-off threshold
DRVL to GND (2)
1
V
1
V
OUTPUT DRIVERS
R(DRVH)
DRVH resistance
R(DRVL)
DRVL resistance
Source, V(VBST-DRVH) = 0.1 V
1.7
5
1
3
Source, V(VREG5-DRVL) = 0.1 V
1.3
4
Sink, V(DRVL-GND) = 0.1 V
0.7
2
Sink, V(DRVH-SW) = 0.1 V
Ω
Ω
CURRENT SENSE
V(OCL-ULV)
Current limit threshold
(ultra-low voltage)
TRIP = 0V/2V, TA = 25°C
27
31
35
TRIP = 0V/2V
25
31
37
V(OCL-LV)
Current limit threshold
(low voltage)
TRIP = 3.3V/5V, TA = 25°C
56
60
64
TRIP = 3.3V/5V
54
60
66
V(ZC)
Zero cross detection
comparator Offset
0.95V < CSNx < 12.6V
–4
0
4
Negative current limit
threshold
(ultra-low voltage)
TRIP = 0V/2V, TA = 25°C
–24
–31
–38
V(OCLN-ULV)
TRIP = 0V/2V
–22
–31
–40
TRIP = 3.3V/5V, TA = 25°C
–51
–60
–69
V(OCLN-LV)
Negative current limit
threshold
(low voltage)
TRIP = 3.3V/5V
–49
–60
–71
(2)
mV
mV
mV
Specified by design.
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SLVS785 – OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
110%
115%
120%
UNIT
UVP, OVP AND UVLO
V(OVP)
OVP Trip Threshold
t(OVPDLY)
OVP Prop Delay
V(UVP)
UVP Trip Threshold
t(UVPDLY)
UVP Delay
V(UVREF2)
VREF2 UVLO Threshold
V(UVREG3)
VREG3 UVLO Threshold
V(UVREG5)
VREG5 UVLO Threshold
OVP detect
μs
1.5
UVP detect
65%
70%
73%
0.8
1
1.2
ms
Wake up
1.7
1.8
1.9
V
Hysteresis
75
100
125
mV
3
3.1
3.2
0.10
0.15
0.20
Wake up
Hysteresis
Wake up
V
4.1
4.2
4.3
V
0.35
0.40
0.44
V
Wake up
0.8
1
1.2
Hysteresis
0.1
0.2
0.3
0.45
0.50
0.55
0.1
0.2
0.3
Hysteresis
INTERFACE AND LOGIC THRESHOLD
V(EN)
EN Threshold
V(EN12)
EN1/EN2 Threshold
V(EN12SS)
EN1/EN2 SS Start
Threshold
SS-ramp start threshold at external soft start
V(EN12SSEND)
EN1/EN2 SS End
Threshold
SS-End threshold at external soft start
I(EN12)
EN1/EN2 Source Current
VEN1/EN2 = 0V
Wake up
Hysteresis
(3)
1.5
SKIPSEL1/SKIPSEL2
Setting Voltage
V
2
V
2
TRIP Setting Voltage
Auto Skip
1.9
2.1
OOA Skip (min 1/8 Fsw)
3.2
3.4
OOA Skip (min 1/16 Fsw)
3.8
FUNC Setting Voltage
I(TRIP)
TRIP Input Current
I(SKIPSEL)
SKIPSEL Input Current
μA
V
1.5
V(OCL-ULV), Discharge OFF
1.9
2.1
V(OCL-LV), Discharge OFF
3.2
3.4
V(OCL-LV), Discharge ON
3.8
Current mode, OVP enable
V(FUNC)
2.6
1.5
V(OCL-ULV), Discharge ON
V(TRIP)
V
1
Continuous
V(SKIPSEL)
V
V
1.5
D-CAP mode, OVP disable
1.9
2.1
D-CAP mode, OVP enable
3.2
3.4
Current mode, OVP disable
3.8
TRIP = 0 V
–1
1
TRIP =5 V
–1
1
SKIPSELx = 0 V
–1
1
SKIPSELx = 5 V
–1
1
V
μA
μA
BOOT STRAP SW
V(FBST)
Forward Voltage
VVREG5-VBST, IF = 10 mA, TA = 25°C
0.10
0.20
V
I(BSTLK)
VBST Leakage Current
VBST = 30 V, SW = 25 V
0.01
1.5
μA
Shutdown temperature (3)
150
THERMAL SHUTDOWN
T(SDN)
(3)
6
Thermal SDN Threshold
Hysteresis (3)
10
°C
Specified by design.
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SLVS785 – OCTOBER 2007
DEVICE INFORMATION
PINOUT
VBST2
SW2
25
GND
DRVL2
27
26
30
5
6
20
19
7
8
18
17
PGOOD2
SKIPSEL2
CSP2
CSN2
VFB1
COMP1
FUNC
VREG3
EN2
15
16
9
10
CSN1
DRVH2
VIN
3
4
24
23
22
21
VREF2
TRIP
COMP2
VFB2
SKIPSEL1
CSP1
1
2
11
12
13
14
V5SW
RF
EN1
PGOOD1
EN
DRVH1
29
28
32
31
SW1
VBST1
DRVL1
VREG5
RHB PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DRVH1
1
DRVH2
24
SW2
25
SW1
32
VREG3
22
EN1
4
EN2
21
PGOOD1
5
PGOOD2
20
SKIPSEL1
6
SKIPSEL2
19
CSP1
7
CSP2
18
CSN1
8
CSN2
17
VFB1
9
VFB2
16
COMP1
10
COMP2
15
RF
3
I/O
DESCRIPTION
O
High-side MOSFET gate driver outputs. Source 1.7Ω, sink 1.0Ω, SW-node referenced floating driver. Drive
voltage corresponds to VBST to SW voltage.
I/O
High-side MOSFET gate driver returns.
O
Always alive 3.3V, 10mA Low Dropout Linear Regulator Output. Bypass to (signal) GND with more than 1μF
ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
I
Channel 1 and Channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55V and less than 6V.
Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
O
Power Good window comparator outputs for channel 1 and 2. The applied voltage should be less than 6V,
and the recommended pull-up resistance value is from 100kΩ to 1MΩ.
Skip Mode Selection pin.
I
GND: Continuous Conduction Mode
VREF2: Auto Skip
VREG3: OOA Auto Skip, max 7 skips (suitable for fsw < 400kHz)
VREG5: OOA Auto Skip, max 15 skips (suitable for equal to or greater than 400kHz)
I/O
Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
be used to extract voltage drop across DCR. 0.1μF is a good value to start the design. See the current
sensing scheme section for more details.
I
Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the
current sense circuit for 5V or higher output voltage setting. Also, used for output discharge terminal.
I
SMPS Voltage Feedback Inputs. Connect the feedback resistors divider, and should be referred to (signal)
GND.
I
Loop Compensation Pin for current mode (Error Amplifier Output). Connect R (and C if required) from this
pin to VREF2 for proper loop compensation with current mode operation. Ramp compensation adjustable pin
for D-CAP mode, connect R from this pin to VREF2. 10kΩ is a good value to start the design. 6kΩ to 20kΩ
can be chosen. See the D-CAP MODE section for more details.
I/O
Frequency Setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock
for synchronization.
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SLVS785 – OCTOBER 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Control architecture and OVP function Selection Pin.
FUNC
11
I
VREF2
13
O
GND: Current mode, OVP enable
VREF2: D-CAP mode, OVP disable
VREG3: D-CAP mode, OVP enable
VREG5: Current mode, OVP disable
2V Reference Output. Bypass to (signal) GND by 0.22μF ceramic capacitor.
Overcurrent trip level and discharge mode selection pin.
GND: V(OCL-ULV) , Discharge on
VREF2: V(OCL-ULV), Discharge off
VREG3: V(OCL-LV), Discharge off
VREG5: V(OCL-LV), Discharge on
TRIP
14
I
EN
12
I
VREF2 and VREG5 Linear Regulators Enable Pin. When turning on, apply greater than 1.2V and less than
6V. Connect to GND to Disable.
VBST1
31
I
Supply inputs for high-side NFET driver (boot strap Terminal). Connect a capacitor (0.1μF or greater is
recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this pin is an
optional.
O
Low-side MOSFET gate driver outputs. Source 1.3Ω, sink 0.7Ω, GND referenced driver.
VBST2
26
DRVL1
30
DRVL2
27
V5SW
2
I
VREG5 switchover power supply input pin.
VREG5
29
O
5V, 100mA Low Dropout Linear Regulator Output. Bypass to (power) GND using a 10μF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
when 4.8V or above is provided.
VIN
23
I
Supply Input for 5V and 3.3V Linear Regulator. Typically connected to VBAT.
GND
28
--
Ground
8
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TYPICAL CHARACTERISTICS
VIN SHUTDOWN CURRENT
vs
INPUT VOLTAGE
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
15
15
I(VINSDN) - Shutdown Current - μA
I(VINSDN) - Shutdown Current - μA
VIN = 12V
12
9
6
3
12
9
6
3
RT
0
-50
0
10
15
20
25
30
50
100
150
VI - VIN Input Voltage - V
Figure 1.
Figure 2.
VIN STANDBY CURRENT
vs
JUNCTION TEMPERATURE
VIN STANDBY CURRENT
vs
INPUT VOLTAGE
120
120
100
100
80
60
40
80
60
40
20
20
0
-50
0
TJ - Junction Temperature - °C
I(VINSTBY) - Standby Current - mA
I(VINSTBY) - Standby Current - mA
5
0
0
50
100
TJ - Junction Temperature - °C
150
5
Figure 3.
10
15
20
VI - VIN Input Voltage - V
25
30
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
NO LOAD BATTERY CURRENT
vs
INPUT VOLTAGE
NO LOAD BATTERY CURRENT
vs
INPUT VOLTAGE
1.0
1.0
EN = on, EN1 = on, EN2 = on
0.9
0.9
0.8
0.8
I(VBAT) - Battery Current - mA
I(VBAT) - Battery Current - mA
EN = on, EN1 = off, EN2 = on
0.7
0.6
0.5
0.4
0.3
0.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.1
0.0
5
10
15
20
0.0
25
5
VI - VIN Input Voltage - V
10
15
20
VI - VIN Input Voltage - V
Figure 5.
Figure 6.
BATTERY CURRENT
vs
INPUT VOLTAGE
VREF2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
25
2.02
1.0
EN = on, EN1 = on, EN2 = off
VIN = 12V
0.9
VO(VREF2) - Output Voltage - V
I(VBAT) - Battery Current - mA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
2.01
2.00
1.99
0.1
0.0
5
10
15
20
VI - VIN Input Voltage - V
25
1.98
-100
Figure 7.
10
-50
0
50
100
IO(VREF2) - Output Current - μA
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VREG3 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VREG5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
5.10
VIN = 12V
VO(VREG5) - Output Voltage - V
VO(VREG3) - Output Voltage - V
VIN = 12V
3.35
3.30
3.25
5.05
5.00
4.95
4.90
3.20
0
2
4
6
8
0
10
20
40
60
80
100
IO(VREG5) - Output Current - mA
IO(VREG3) - Output Current - mA
Figure 9.
Figure 10.
SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
FORWARD VOLTAGE OF BOOST SW
vs
JUNCTION TEMPERATURE
0.25
330
320
0.20
V(FBST) - Forward Voltage - V
f(SW) - Switching Frequency - kHz
RF = 330kΩ
310
300
290
0.10
0.05
280
270
-50
0.15
0
50
100
150
0.00
-50
TJ - Junction Temperature - °C
Figure 11.
0
50
100
150
TJ - Junction Temperature - °C
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
VBST LEAKAGE CURRENT
vs
JUNCTION TEMPERATURE
150
1.5
130
1.2
Ilkg - VBST Leakage Current - μA
OVP/UVP Threshold - %
OVP/UVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
OVP
110
90
70
0.9
0.6
0.3
UVP
50
-50
0
50
100
0.0
-50
150
TJ - Junction Temperature - °C
Figure 13.
Figure 14.
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
150
66
V(OCL-LV) - Current Limit Threshold - mV
V(OCL-ULV) - Current Limit Threshold - mV
37
35
CSN = 1V
CSN = 5V
33
31
CSN = 12V
29
27
25
-50
12
0
50
100
TJ - Junction Temperature - °C
0
50
100
150
64
CSN = 1V
CSN = 5V
62
60
CSN = 12V
58
56
54
-50
0
50
100
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.3-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.40
5.10
CCM
VO2 - 3.3-V Output Voltage - V
VO1 - 5-V Output Voltage - V
CCM
5.05
IO = 0A
5.00
IO = 3A
4.95
IO = 6A
4.90
5
10
15
20
3.35
IO = 0A
IO = 3A
3.30
IO = 6A
3.25
3.20
25
5
VI - VIN Input Voltage - V
10
15
25
VI - VIN Input Voltage - V
Figure 17.
Figure 18.
5-V EFFICIENCY
vs
OUTPUT CURRENT
5-V EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 7 V
Auto-skip
90
80
OOA
VIN = 12 V
h - Efficiency - %
h - Efficiency - %
20
60
40
80
VIN = 21 V
70
60
20
CCM
Auto-skip
VIN = 12V
0
0.001
0.01
0.1
1
IO1 - 5-V Output Current - A
10
50
0.001
0.01
0.1
1
10
IO1 - 5-V Output Current - A
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 7 V
Auto-skip
90
80
h - Efficiency - %
h - Efficiency - %
VIN = 12 V
OOA
60
40
5-V Switcher ON
(Auto-skip)
20
CCM
80
VIN = 21 V
70
Auto-skip
60
50
5-V Switcher ON
(Auto-skip)
VIN = 12V
0
0.001
0.01
0.1
1
40
0.001
10
0.01
0.1
1
IO2 - 3.3-V Output Current - A
IO2 - 3.3-V Output Current - A
Figure 21.
Figure 22.
5-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
3.3-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
400
400
VIN = 12V
VIN = 12V
350
f(SW) - Swithching Frequency - kHz
f(SW) - Swithching Frequency - kHz
350
CCM
300
250
200
OOA
150
100
CCM
300
250
200
OOA
150
100
50
50
Auto-skip
Auto-skip
0
0
0
0.5
1
1.5
IO1 - 5-V Output Current - A
2
0
Figure 23.
14
10
0.5
1
1.5
IO2 - 3.3-V Output Current - A
2
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
5.10
Current Mode
Rgv = 10k
VIN = 12V
OOA
5.05
VO2 - 3.3-V Output Voltage - V
VO1 - 5-V Output Voltage - V
Current Mode
Rgv = 10k
VIN = 12V
Auto-skip
5.00
CCM
4.95
4.90
Auto-skip
3.30
CCM
3.25
3.20
0
1
2
3
4
IO1 - 5-V Output Current - A
5
OOA
3.35
6
0
1
2
3
4
IO2 - 3.3-V Output Current - A
Figure 25.
Figure 26.
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
6
3.40
5.10
Current Mode
(No Droop)
Rgv + C = 15K + 10nF
VIN = 12V
VO2 - 3.3-V Output Voltage - V
Current Mode
(No Droop)
Rgv + C = 15K + 10nF
VIN = 12V
VO1 - 5-V Output Voltage - V
5
5.05
OOA
Auto-skip
5.00
CCM
4.95
4.90
3.35
OOA
3.30
CCM
3.25
3.20
0
1
2
3
4
IO1 - 5-V Output Current - A
5
6
Auto-skip
0
Figure 27.
1
2
3
4
IO2 - 3.3-V Output Current - A
5
6
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
5.10
D-CAP mode
Rgv = 10k
Cout-ESR = 18mW
VIN = 12V
OOA
5.05
VO2 - 3.3-V Output Voltage - V
VO1 - 5-V Output Voltage - V
D-CAP mode
Rgv = 10k
Cout-ESR = 40mW
VIN = 12V
Auto-skip
5.00
CCM
4.95
4.90
3.35
OOA
Auto-skip
3.30
CCM
3.25
3.20
0
1
2
3
4
IO1 - 5-V Output Current - A
5
6
0
1
2
3
4
IO2 - 3.3-V Output Current - A
Figure 29.
Figure 30.
5.0-V START-UP WAVEFORMS
3.3-V START-UP WAVEFORMS
EN1 (5V/div)
EN2 (5V/div)
VO1 (2V/div)
VO2 (2V/div)
PGOOD1 (5V/div)
6
PGOOD2 (5V/div)
VIN=12V
Iout=6A
VIN=12V
Iout=6A
t - Time - 1ms/div
Figure 31.
16
5
t - Time - 1ms/div
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
5.0-V SOFT-STOP WAVEFORMS
3.3-V SOFT-STOP WAVEFORMS
EN1 (5V/div)
EN2 (5V/div)
VO1 (5V/div)
VO2 (5V/div)
PGOOD1 (5V/div)
PGOOD2 (5V/div)
DRVL1 (5V/div)
DRVL2 (5V/div)
t - Time - 1ms/div
Figure 33.
t - Time - 1ms/div
Figure 34.
5.0-V LOAD TRANSIENT RESPONSE
3.3-V LOAD TRANSIENT RESPONSE
VO2 (100mV/div)
VO1 (100mV/div)
IIND(5A/div)
VIN=12V, Auto-skip
IO1 (5A/div)
IIND(5A/div)
IO2 (5A/div)
VIN=12V, Auto-skip
t - Time - 100 ms/div
t - Time - 100 ms/div
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
5.0-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
3.3-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
Phase
40
Gain - dB
20
Gain
0
80
135
60
90
40
45
20
0
180
135
Phase
90
Gain
45
0
0
-20
-45
-20
-45
-40
-90
-40
-90
-135
-60
-180
-80
100
-60
VIN = 12V
Current mode
-80
100
1K
10K
100K
1M
VIN = 12V
Current Mode
f - Frequency - kHz
Phase - °
60
180
Phase - °
Gain - dB
80
-135
-180
1K
10K
f - Frequency - kHz
Figure 37.
100K
1M
Figure 38.
5.0-V SWITCH-OVER WAVEFORMS
VREG5 (100mV/div)
VO1 (100mV/div)
t - Time - 2ms/div
Figure 39.
18
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DETAILED DESCRIPTION
ENABLE AND SOFT START
When EN is Low, the TPS51220 is in the shutdown state. The 3.3V LDO only stays alive, and consumes 7μA
(typically). When EN becomes High, the TPS51220 is in the standby state. The 2V reference and the 5V LDO
become enable, and consume about 80μA with no load condition, and are ready to turn on SMPS channels.
Each SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51220 begins
softstart, and ramps up the output voltage from zero to the target voltage with 0.8 ms. However, if a slower
soft-start is required, an external capacitor can be tied from the ENx pin to GND. In this case, the TPS51220
charges the external capacitor with the integrated 2-μA current source. An approximate external soft-start time
would be tEX-SS = CEX / IEN12, which means the time from ENx = 1V to ENx = 2V. The recommend capacitance is
more than 2.2nF.
1) Internal
Soft-start
EN1
Vout1
800ms
140ms
EN1<2V
EN1>1V
2) External
Soft-start
EN1
External
Soft-start
time
Vout1
Figure 40. Enable and Soft-start Timing
Table 1. Enable Logic States
EN
EN1
EN2
VREG3
VREF2
VREG5
CH1
CH2
GND
Don’t Care
Don’t Care
ON
Off
Off
Off
Off
Hi
Lo
Lo
ON
ON
ON
Off
Off
Hi
Hi
Lo
ON
ON
ON
ON
Off
Hi
Lo
Hi
ON
ON
ON
Off
ON
Hi
Hi
Hi
ON
ON
ON
ON
ON
3.3V, 10mA LDO (VREG3)
A 3.3-V, 10mA, linear regulator is integrated in the TPS51220. This LDO services the some of the analog supply
rail for IC and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-μF (at least 1-μF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the
IC.
2V, 100μA Sink/ Source Reference (VREF2)
This voltage is used for the reference of the loop compensation network. Apply a 0.22-μF (at least 0.1-μF), high
quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND in adjacent to the IC.
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5.0V, 100mA LDO (VREG5)
A 5.0-V, 100mA, linear regulator is integrated in the TPS51220. This LDO services the main analog supply rail
for IC and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-μF (at least
4.7-μF), high quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the IC.
VREG5 SWITCHOVER
If the V5SW voltage becomes higher than 4.7V, the internal 5V-LDO is shut off and the VREG5 is shorted to
V5SW by an internal MOSFET after an 7.7ms delay. When the V5SW voltage becomes lower than 4.5V, the
internal switch is turned off and the internal 5V-LDO resumes immediately.
BASIC PWM OPERATIONS
The main control loop of the SMPS is designed as a fixed frequency, pulse width modulation (PWM) controller. It
supports two control schemes; a peak current mode and a proprietary D-CAP mode. Current mode achieves
stable operation in any type of capacitors including low ESR capacitor(s) such as ceramic or specialty polymer
capacitors. D-CAP mode does not require an external compensation circuit, and is suitable for relatively larger
ESR capacitor(s) configuration. These control schemes are selected with FUNC-pin; see Table 4.
CURRENT MODE
The current mode scheme uses the output voltage information and the inductor current information to regulate
the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the
internal 1V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The
inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage goes down, the TPS51220 increases the target inductor current to raise the output voltage, on
the other hand, if the output voltage goes up the TPS51220 decreases the target inductor current to reduce the
output voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The
high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the
controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each
OFF state to keep the conduction loss minimum.
D-CAP™ MODE
With the D-CAP mode operation, the PWM comparator compares VREF2 with the combination value of the
COMP voltage, VFB-AMP output, and the ramp compensation signal. When the both signals are equal at the
peak of the voltage sense signal, the comparator provides the OFF signal to the high-side MOSFET driver.
Because the compensation network is implemented on the part and the output waveform itself is used as the
error signal, external circuit is simplified. Another advantage is its inherent fast transient response. A trade-off is
a sufficient amount of ESR required in the output capacitor. The D-CAP™ mode is suitable for relatively larger
output ripple voltage application. The inductor current information is used for the overcurrent protection and light
load operation.
20
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PWM FREQUENCY CONTROL
The TPS51220 has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1.
1 × 105
fsw éëkHz ùû =
RF éëkΩ ùû
(1)
TPS51220 can also synchronize to more than 2.5V amplitude external clock by applying the signal to the RF pin.
The set timing of channel-1 initiates at the raising edge (1.3V typ) of the clock and channel-2 initiates at the
falling edge (1.1V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
1000
900
fSW - Frequency - kHz
800
700
600
500
400
300
200
100
0
100
200
300
400
500
RF - Resistance - kW
Figure 41. Switching Frequency vs RF
LIGHT LOAD OPERATION
The TPS51220 automatically reduces switching frequency at light load condition to maintain high efficiency if
Auto Skip or OOA™ mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping pulses.
As the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to the point that its peak touches a predetermined current, ILL(PEAK), which indicates the boundary between
heavy load conduction and light load condition. Once the top MOSFET is turned on, the TPS51220 does not
allow it to be turned off until it touches ILL(PEAK). This eventually causes an overvoltage condition to the output and
pulse skipping. From the next pulse after zero-crossing is detected, ILL(PEAK) is limited by the ramp down signal
which starts from 25% of the overcurrent limit setting (IOCL(PEAK): see the current protection session) toward 5% of
IOCL(PEAK) over one switching cycle to prevent causing large ripple. The transition load point to the light load
operation ILL(DC) can be calculated as follows;
I LL(DC) + I LL(PEAK) * 0.5 I IND(RIPPLE)
(2)
(V - VOUT ) × VOUT
1
IIND(RIPPLE) =
× IN
L × fSW
VIN
(3)
where fSW is the PWM switching frequency which is determined by RF resistor setting or external clock.
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportional to the output current from the ILL(DC) given above; however, as the switching is
synchronized with clock. Due to the synchronization, the switching waveform in boundary load condition (close to
ILL(DC)) appears as a sub-harmonic oscillation; however, it is the intended operation.
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If SKIPSELx is tied to GND, the TPS51220 works on a constant frequency of fSW regardless its load current.
Inductor
Current
ILL(PEAK)
ILL(DC)
IIND(RIPPLE)
0
Time
Figure 42. Boundary Between Pulse Skipping and CCM
ILL(PEAK)Ramp = (0.25-0.2 ×
VOUT
) × IOCL(PEAK)
VIN
(4)
Inductor
Current
25% of IOCL(PEAK)
ILL(PEAK) Ramp signal
ILL(PEAK)
5% of IOCL(PEAK)
0
Time
ton
1/fSW
Figure 43. Inductor Current Limit at Pulse Skipping
Table 2. Skip Mode Selection
SKIPSELx
GND
VREF2
VREG3
VREG5
OPERATING MODE
Continuous Conduction
Auto Skip
OOA Skip (max 7 skips,
for <400 kHz)
OOA Skip (max 15 skips, for equal
to or greater than 400kHz)
OUT OF AUDIO SKIP OPERATION
Out-Of-Audio™ (OOA) light load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion
efficiency. When OOA is selected, the switching frequency is kept higher than audible frequency range in any
load condition. The TPS51220 automatically reduce switching frequency at a light load condition. OOA control
circuit monitors the states of both MOSFETs and forces ON state if predetermined number of pulses are skipped.
This means that the high-side MOSFET is turned on before the output voltage declines down to the target value,
so that eventually an overvoltage condition is caused. The OOA control circuit detects this overvoltage condition
and begins modulating the skip-mode on time to keep the output voltage.
TPS51220 supports wide switching frequency range; therefore, the OOA skip mode has two selections, see
Table 2. When 300kHz switching frequency is selected, max 7 skip (SKIPSEL=3.3V) makes the lowest frequency
at 37.5kHz. If max 15 skip is chosen, it becomes 18.8kHz, hence max 7 skip is suitable for less than 400kHz,
and max 15 skip is for equal to or greater than 400kHz.
22
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99% DUTY CYCLE OPERATION
In a low dropout condition such as 5V input to 5V output, the basic control loop tries to keep the high-side
MOSFET 100% ON as a nature. However, with N-MOSFET used for the top switch, it is not possible to use the
100% on cycle to charge the boot strap capacitor. TPS51220 detects the 100% ON condition and inserts the
OFF state at the appropriate time.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low rDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 1.7Ω for VBSTx to DRVHx, and 1Ω for DRVHx to SWx. When
configured as a floating driver, 5V bias voltage is delivered from VREG5 supply. The instantaneous drive current
is supplied by the flying capacitor between VBSTx and SWx pins. The average drive current is equal to the gate
charge at Vgs = 5V times switching frequency. This gate drive current as well as the low-side gate drive current
times 5V makes the driving power which needs to be dissipated from TPS51220 package. A dead time to
prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and
low-side MOSFET off to high-side MOSFET on.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current low rDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which are 1.3Ω for VREG5 to DRVLx and 0.7Ω for DRVLx to GND. The 5V
bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor
connected between VREG5 and GND. The average drive current is also calculated by the gate charge at
Vgs = 5V times switching frequency.
CURRENT SENSING SCHEME
In order to provide both good accuracy and cost effective solution, the TPS51220 supports external resistor
sensing and inductor DCR sensing. An RC network with high quality X5R or X7R ceramic capacitor should be
used to extract voltage drop across DCR. 0.1μF is a good value to start the design. CSPx and CSNx should be
connected to positive and negative terminal of the sensing device respectively. TPS51220 has an internal current
amplifier. The gain of the current amplifier, Gc, is selected by TRIP terminal. In any setting, the output signal of
the current amplifier becomes 100mV at the OCL setting point. This means that the current sensing amplifier
normalize the current information signal based on the OCL setting. Attaching a RC network recommended even
with a resistor sensing scheme to get an accurate current sensing; see the external parts selection session for
detailed configurations.
CURRENT PROTECTION
TPS51220 has cycle-by-cycle overcurrent limiting control. If the inductor current becomes larger than the
overcurrent trip level, TPS51220 turns off high-side MOSFET, turns on low-side MOSFET and waits for the next
clock cycle.
IOCL(PEAK) sets peak level of the inductor current. Thus, the dc load current at overcurrent threshold, IOCL(DC), can
be calculated as follows;
I OCL(DC) + I OCL(PEAK) * 0.5 I IND(RIPPLE)
(5)
VOCL
I OCL(PEAK) +
RSENSE
(6)
where RSENSE is resistance of current sensing device and V(OCL) is overcurrent trip threshold voltage which is
determined by TRIP pin voltages as shown in Table 3.
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down, and it will end up with crossing the undervoltage protection threshold and shutdown.
Table 3. OCL Trip and Discharge Selection
TRIP
V(OCL) (OCL Trip voltage)
Discharge
GND
VREF2
V(OCL-ULV) (Ultra Low Voltage)
Enable
Disable
VREG3
VREG5
V(OCL-LV) (Low Voltage)
Disable
Enable
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POWERGOOD
The TPS51220 has powergood output for both switcher channels. The powergood function is activated after
softstart has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the powergood signal becomes high after 1ms internal delay. If the output voltage goes
outside of ±10% of the target value, the powergood signal becomes low after 1.5μs internal delay. Apply voltage
should be less than 6V and the recommended pull-up resistance value is from 100kΩ to 1MΩ.
OUTPUT DISCHARGE CONTROL
The TPS51220 discharges output when ENx is low. The TPS51220 discharges outputs using an internal
MOSFET which is connected to CSNx and GND. The current capability of these MOSFETs is limited to
discharge the output capacitor slowly. If ENx becomes high during discharge, MOSFETs are turning on, and
some output voltage remains. SMPS changes over to soft-start. PWM will begin after the target voltage
overtakes the remaining output voltage. This function can be disabled as shown in Table 3.
OVER/UNDERVOLTAGE PROTECTION
TPS51220 monitors the output voltage to detect over and undervoltage. When the output voltage becomes 15%
higher than the target value, the OVP comparator output goes high and the circuit latches as the high-side
MOSFET driver OFF and the low-side MOSFET driver ON, and shuts off another channel.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1ms, TPS51220 latches OFF both high-side and
low-side MOSFETs, and shuts off another channel. This UVP function is enabled after soft start has completed.
OVP function can be disabled as Table 4. The procedures for restarting from these protection states are:
1. toggle EN
2. toggle EN1 and EN2 or
3. once hit UVLO
Table 4. FUNC Logic States
FUNC
GND
VREF2
VREG3
VREG5
OVP
Enable
Disable
Enable
Disable
Control Scheme
Current mode
D-CAP mode
D-CAP mode
Current mode
UVLO PROTECTION
TPS51220 has undervoltage lock out protections (UVLO) for VREG5, VREG3 and VREF2. When the voltage is
lower than UVLO threshold voltage, TPS51220 shuts off each output as Table 5. This is non-latch protection.
Table 5. UVLO Protection
CH1/ CH2
VREG5
VREG3
VREF2
VREG5 UVLO
Off
—
On
On
VREG3 UVLO
Off
Off
—
Off
VREF2 UVLO
Off
Off
On
—
THERMAL SHUTDOWN
TPS51220 monitors the temperature of itself. If the temperature exceeds the threshold value, TPS51220 shuts
off both SMPS and 5V-LDO, and deceases the VREG3 current limitation to 5mA (typically). This is non-latch
protection.
24
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APPLICATION INFORMATION
EXTERNAL PARTS SELECTION
A buck converter using TPS51220 consists of linear circuits and a switching modulator. Figure 44 and Figure 45
show basic scheme.
Voltage divider
VFB
Gmv
DRVH
PWM
Control
logic
&
Driver
+
+
R2
VIN
Switching Modulator
Ramp
comp.
R1
+
+
1.0V
Lx
Rs
DRVL
ESR
RL
Co
COMP
Cc
Rgv
Gmc
Rgc
VREF
CSP
+
+
CSN
2.0V
Error Amplifier
Figure 44. Simplified Current Mode Functional Blocks
Voltage divider
VFB
Gmv
DRVH
PWM
+
+
R2
+
+
1.0V
VIN
Switching Modulator
Ramp
comp.
R1
Control
logic
&
Driver
Lx
Rs
DRVL
ESR
RL
Co
COMP
Rgv
VREF
+
2.0V
Figure 45. Simplified D-CAP Mode Functional Blocks
The external components can be selected by following manner.
1. Determine output voltage dividing resistors (R1 and R2: shown in Figure 44) using the next equation
R1 + ǒV OUT * 1.0Ǔ
R2
(7)
For D-CAP mode, recommended R2 value is from 10kΩ to 20kΩ.
2. Determine switching frequency. Higher frequency allows smaller output capacitances, however, degrade
efficiency due to increase of switching loss. Frequency setting resistor for RF-pin can be calculated by;
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5
RF[kW] + 1 10
ƒ sw [kHz]
(8)
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
(VIN(TYP) - VOUT ) × VOUT
1
L=
×
0.33 x IOUT(MAX) x fSW
VIN(TYP)
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the OCL trip voltage threshold, V(OCL), and select the sensing resistor.
The OCL trip voltage threshold is determined by TRIP pin setting. To use smaller value improves S/N ratio.
Determine the sensing resistor using next equation. IOCL(PEAK) should be approximately 1.5 × IOUT(MAX) to
1.7 × IOUT(MAX).
VOCL
R SENSE +
I OCL(PEAK)
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500μS.
I OUT(MAX)
1
Rgv + 0.1
VOUT
I OCL(PEAK)
Gmv Vdroop
(11)
Rgv[kW] + 200
I OUT(MAX)
I OCL(PEAK)
V OUT[V]
Vdroop[mV]
(12)
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 13. Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of fo. For D-CAP mode, Rgv is used for adjusting ramp compensation. 10kΩ is
a good value to start design with. 6kΩ to 20kΩ can be chosen.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
fo, should be kept under 1/3 of the switching frequency.
Gmv Rgv
ƒsw
1
ƒ0 + 5
t
p I OCL(PEAK) V
3
Co
OUT
(13)
Co u 15
p
I OCL(PEAK)
1
VOUT
Gmv Rgv
ƒsw
(14)
For D-CAP mode, fo is determined by the output capacitor’s characteristics as below.
ƒsw
1
ƒ0 +
t
3
2p ESR Co
3
Co u
2p ESR ƒsw
(15)
(16)
For better jitter performance, a sufficient amount of feedback signal is required at VFBx pin. The
recommended signal level is approximately 30mV per tsw (switching period) of the ramping up rate, and more
than 4mV of peak-to-peak voltage.
26
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VFB
signal
30mV
VFBRIPPLE =VoRIPPLE x 1/Vout
Time
tSW = 1/fSW
Figure 46. Required voltage feedback ramp signal
7. Calculate Cc. The purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. If
ceramic capacitor(s) is used, there is no need for Cc. If a combination of different capacitors is used, attach a
RC network circuit instead of single capacitance to cancel zeros and poles caused by the output capacitors.
With single capacitance, Cc is given in Equation 17.
Cc + Co ESR
Rgv
(17)
For D-CAP mode, basically Cc is not needed.
8. Choose MOSFETs Generally, the on resistance affects efficiency at high load conditions as conduction loss.
For a low output voltage application, the duty ratio is not high enough so that the on resistance of high-side
MOSFET does not affect efficiency; however, switching speed (tr and tf) affects efficiency as switching loss.
As for low-side MOSFET, the switching loss is usually not a main portion of the total loss.
RESISTOR CURRENT SENSING
For more accurate current sensing with an external resistor, the following technique is recommended. Adding an
RC filter to cancel the parasitic inductance of resistor, this filter value is calculated using Equation 18.
Cx Rx + Lx
Rs
(18)
This equation means time-constant of Cx and Rx should match the one of Lx (ESL) and Rs.
VIN
Ex-resistor
DRVH
Control
logic
&
Driver
L
Rs
Lx(ESL)
DRVL
Co
CSP
+
Cx
Rx
CSN
Figure 47. External Resistor Current Sensing
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INDUCTOR DCR CURRENT SENSING
To use inductor DCR as current sensing resistor (Rs), the configuration needs to change as below. However, the
equation must be satisfied is the same as the one of resistor sensing.
VIN
Inductor
DRVH
Control
logic
&
Driver
Lx
Rs(DCR)
DRVL
Co
Rx
CSP
+
Cx
CSN
Figure 48. Inductor DCR Current Sensing
VIN
Inductor
DRVH
Control
logic
&
Driver
Lx
Rs(DCR)
DRVL
Co
Rx
CSP
+
Cx
Rc
CSN
Figure 49. Inductor DCR Current Sensing With Voltage Divider
TPS51220 has fixed V(OCL) point (60 mV or 30 mV). In order to adjust for DCR, a voltage divider can be
configured as Figure 49.
For Rx, Rc and Cx can be calculated as shown below, and overcurrent limitation value can be calculated as
follows:
Lx
Cx × (Rx//Rc ) =
Rs
(19)
Rx
)
Rc
1
I OCL(PEAK) + VOCL
Rs
Rc
(20)
Figure 50 shows the compensation technique for the temperature drifts of the inductor DCR value. This scheme
assumes the temperature rise at the thermistor (RNTC) is directly proportional to the temperature rise at the
inductor.
28
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Inductor
Lx
Rx
Rs(DCR)
RNTC
Rc1
Rc2
CO
CSP
+
Cx
CSN
Figure 50. Inductor DCR Current Sensing With Temperature Compensate
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a PCB layout work using the TPS51220.
Placement
• Place RC network for CSP1 and CSP2 close to the IC pins.
• Place bypass capacitors for VREG5, VREG3 and VREF2 close to the IC pins.
• Place frequency-setting resistor close to the IC pin.
• Place the compensation circuits for COMP1 and COMP2 close to the IC pins.
• Place the voltage setting resistors close to the IC pins, especially when D-CAP mode is chosen.
Routing (sensitive analog portion)
• Use separate traces for; see Figure 51
– Output voltage sensing from current sensing (negative-side)
– Output voltage sensing from V5SW input (when VOUT = 5V)
– Current sensing (positive-side) from switch-node
V5SW
R1
VFB
R2
H-FET
Inductor
Vout
SW
L-FET
Cout
R
CSP
C
CSN
Figure 51. Sensing Trace Routings
•
Use Kelvin sensing traces from the solder pads of the current sensing device (inductor or resistor) to current
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sensing comparator inputs (CSPx and CSNx). (See Figure 52)
Current sensing
Device
RC network
next to IC
Figure 52. Current Sensing Traces
•
•
•
•
Use small copper space for VFBx. These are short and narrow traces to avoid noise coupling
Connect VFB resistor trace to the positive node of the output capacitor.
Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors, and the other sensitive analog
components. Placing a signal GND plane (underneath the IC, and fully covered peripheral components) on
the internal layer for shielding purpose is recommended. (See Figure 53)
Use a thermal land for PowerPAD™. Five or more vias, with 0.33-mm (13-mils) diameter connected from the
thermal land to the internal GND plane, should be used to help dissipation. Do NOT connect the GND-pin to
this thermal land on the surface layer, underneath the package.
Routing (power portion)
• Use wider/ shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
• Use the parallel traces of SW and DRVH for high-side MOSFET gate drive, and keep them away from DRVL.
• Connect SW trace to source terminal of the high-side MOSFET.
• Use power GND for VREG5, VIN and Vout capacitors and low-side MOSFETs. Power GND and signal GND
should be connected near the IC GND terminal. (See Figure 53)
TPS51220
0W resistor
GND
#28
GND-pin
To inner
Power-GND
layer
To inner
Signal-GND
plane
Inner Signal-GND plane
Figure 53. GND Layout Example
30
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APPLICATION CIRCUITS
VREG5
5V/100mA
VBAT
C12
2x10mF
L1
4mH
VBAT
Q11
C01
10mF
C14
0.1mF
C24
0.1mF
PGND
PGND
VO1
5V/6A
C22
2x10mF
Q21
Q12
L2
4mH
VO2
3.3V/6A
GND PGND
PGND
Q22
2
VO1
29
28
27
26
25
VREG5
GND
DRVL2
VBST2
SW2
1
30
DRVL1
PGND
31
VBST1
PGND
32
SW1
C11
2x120mF
DRVH1
PGND
DRVH2
V5SW
C21
2x220mF
VIN
PGND
24
23
VBAT
VREG3
22
VREG3
3.3V/10mA
EN2
21
EN2
PGOOD2
20
PGOOD2
SKIPSEL2
19
SKIPSEL2
CSP2
18
R01
330kW
3
RF
4
EN1
5
PGOOD1
6
SKIPSEL1
7
CSP1
C03
1mF
GND
EN1
PGOOD1
SKIPSEL1
R14
6.8kW
TPS51220RHB
(QFN32)
GND
R24
6.8kW
12
13
14
15
CSN2
VFB2
11
COMP2
10
TRIP
9
GND
VREF2
EN
EN
CSN1
FUNC
8
VFB1
C13
0.1mF
COMP1
PowerPAD
R15
56kW
C23
0.1mF
R25
56kW
17
16
VREG5
VREF2
GND
VO1
R11
120kW
R12
30kW
C15
100pF
R21
62kW
C02
0.22mF
R13
10kW
VO2
R23
10kW
VREF2
GND
C25
220pF
R22
27kW
VREF2
GND
GND
Figure 54. Current Mode, DCR Sensing, 5.0V/5A, 3.3V/5A, 300-kHz
Table 6. Current Mode, DCR Sensing, 5.0V/5A, 3.3V/5A, 300-kHz
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
C11
2 × 120 μF/ 6.3 V/15-mΩ
Panasonic
EEFCX0J121R
C12
2 × 10 μF/ 25 V
Murata
GRM32DR71E106K
C21
2 × 220 μF/ 4.0 V/15-mΩ
Panasonic
EEFCX0G221R
C22
2 × 10 μF/ 25 V
Murata
GRM32DR71E106K
L1
4.0 μH, 10.3 A, 6.6-mΩ
Sumida
CEP125-4R0MC-H
L2
4.0 μH, 10.3A, 6.6-mΩ
Sumida
CEP125-4R0MC-H
Q11, Q21
30-V, 13.6-A, 9.5-mΩ
IR
IRF7821
Q12, Q22
30-V, 13.8-A, 5.8-mΩ
IR
IRF8113
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VREG5
5V/100mA
VBAT
R15
6mW
VO1
5V/6A
L1
3.3mH
VBAT
Q11
C12
2x10mF
C01
10mF
C14
0.1mF
C22
2x10mF
Q21
C24
0.1mF
PGND
PGND
Q12
L2
3.3mH
R25
6mW
VO2
3.3V/6A
GND PGND
PGND
Q22
2
VO1
29
28
27
26
25
VREG5
GND
DRVL2
VBST2
SW2
1
30
DRVL1
PGND
31
VBST1
PGND
32
SW1
C11
2x220mF
DRVH1
PGND
DRVH2
V5SW
C21
2x220mF
VIN
PGND
24
23
VBAT
VREG3
22
VREG3
3.3V/10mA
EN2
21
EN2
PGOOD2
20
PGOOD2
SKIPSEL2
19
SKIPSEL2
CSP2
18
CSN2
17
R01
270kW
3
RF
4
EN1
5
PGOOD1
6
SKIPSEL1
7
CSP1
C03
1mF
GND
EN1
PGOOD1
SKIPSEL1
TPS51220RHB
(QFN32)
GND
12
13
14
15
VFB2
11
COMP2
10
TRIP
9
GND
VREF2
EN
EN
CSN1
FUNC
8
VFB1
C13
0.1mF
COMP1
PowerPAD
R14
1.2W
C23
0.1mF
16
VREF2
GND
R11
120kW
R12
30kW
C15
220pF
R21
62kW
C02
0.22mF
VO1
R13
10kW
VO2 GND
R23
10kW
VREF2
GND
R24
1.2W
C25
220pF
R22
27kW
VREF2
GND
GND
Figure 55. Current Mode, Ex-Resistor Sensing, 5.0V/5A, 3.3V/5A, 370-kHz
Table 7. Current Mode, Ex-Resistor Sensing, 5.0V/5A, 3.3V/5A, 370-kHz
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
C11
2 x 220 μF/ 6.3 V/12-mΩ
Panasonic
EEFUE0J221R
C12
2 x 10 μF/ 25 V
Murata
GRM32DR71E106K
C21
2 x 220 μF/ 4.0 V/12-mΩ
Panasonic
EEFUE0G221R
C22
2 x 10 μF/ 25 V
Murata
GRM32DR71E106K
L1
3.3 μH, 10.3 A, 5.9-mΩ
TOKO
FDA1055-3R3M
L2
3.3 μH, 10.3 A, 5.9-mΩ
TOKO
FDA1055-3R3M
Q11, Q21
30-V, 13.6-A, 9.5-mΩ
IR
IRF7821
Q12, Q22
30-V, 13.8-A, 5.8-mΩ
IR
IRF8113
32
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS51220RHBR
PREVIEW
QFN
RHB
32
3000
TBD
Call TI
Call TI
TPS51220RHBT
PREVIEW
QFN
RHB
32
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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