TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 4.5-V TO 20-V INPUT, 6-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET (SWIFT™) FEATURES • • • • • • • • • • • DESCRIPTION 40 mΩ MOSFET Switch for High Efficiency at 6-A (7.5 Peak) Output Current Uses External Lowside MOSFET Output Voltage Adjustable Down to 0.891 V With 1% Accuracy Synchronizes to External Clock 180° Out of Phase Synchronization Wide PWM Frequency– Fixed 250 kHz, 500 kHz or Adjustable 250 kHz to 700 kHz Adjustable Slow Start Adjustable Undervoltage Lockout Load Protected by Peak Current Limit and Thermal Shutdown 16-Pin TSSOP PowerPAD™ Package SWIFT Documentation Application Notes, and Design Software: www.ti.com/swift APPLICATIONS • • • • The TPS54550 is a medium output current synchronous buck PWM converter with an integrated high side MOSFET and a gate driver for an low side external MOSFET. Features include a high performance voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter inductors and capacitors. The TPS54550 has an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 4.5 V; a slow-start circuit to limit in-rush currents; and a power good output to indicate valid output conditions. The synchronization feature is configurable as either an input or an output for easy 180° out of phase synchronization. The TPS54550 device is available in a thermally enhanced 16-pin TSSOP (PWP) PowerPAD™ package. TI provides evaluation modules and the SWIFT™ Designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. Industrial and Commercial Low Power Systems LCD Monitors and TVs Computer Peripherals Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Simplified Schematic TPS54550 SYNC EFFICIENCY vs OUTPUT CURRENT Input Voltage 100 VIN 95 PWRGD 90 SS/ENA BOOT COMP PH LSG VSENSE PGND PWRPAD 85 Output Voltage Efficiency - % VBIAS 80 75 70 65 VI = 9 V, VO = 3.3 V, fsw = 700 kHz 60 55 50 0 1 2 3 4 IO - Output Current - A 5 6 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) Tj OUTPUT VOLTAGE PACKAGE PART NUMBER (1) -40°C to 125°C Adjustable to 0.891 V Plastic HTSSOP (PWP) TPS54550PWP (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54550PWPR). PACKAGE DISSIPATION RATINGS (1) (1) (2) 2 PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 16-Pin PWP with solder (2) 40.1°C/W 2.49 1.37 1.00 See Figure 22 for power dissipation curves. Test Board Conditions a. 3 inch x 3 inch b. Thickness: 0.062 inch c. 2 PCB layers d. 2 oz. Copper e. See Figure 26, Figure 27 and TPS54550 evaluation module user's guide for layout suggestions. Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VI VO IO Input voltage range Output voltage range Source current VIN -0.3 V to 21.5 V VSENSE -0.3 V to 8.0 V UVLO -0.3 V to 8.0 V SYNC -0.3 V to 4.0 V SSENA -0.3 V to 4.0 V BOOT VI(PH) + 8.0 V VBIAS -0.3 to 8.5 V LSG -0.3 to 8.5 V SYNC -0.3 to 4.0 V RT -0.3 to 4.0 V PWRGD -0.3 to 6.0 V COMP -0.3 to 4.0 V PH -1.5 V to 22 V PH Internally Limited (A) LSG (Steady State Current) 10 mA COMP, VBIAS 3 mA SYNC IS Sink current, Voltage differential 5 mA LSG (Steady State Current) 100 mA PH (Steady State Current) 500 mA COMP 3 mA SSENA, PWRGD 10 mA AGND to PGND ±0.3 V TJ Junction temperature +150°C Tstg Storage temperature -65°C to +150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE MIN TYP MAX UNIT Human Body Model HBM JESD22-A114 1.5 kV Charged Device Model CDM JESD22-C101 1.5 kV RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VI Input voltage range 4.5 20 V TJ Operating junction temperature -40 125 °C Submit Documentation Feedback 3 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS TJ = -40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIOINS MIN TYP MAX UNIT SUPPLY CURRENT IQ Operating Current, PH pin open, No external low side MOSFET, RT = Hi-Z Quiescent current 10.3 Shutdown, SSENA = 0 V 1.1 Start threshold voltage VIN 4.32 Stop threshold voltage mA 3.69 Hysteresis mA 4.49 V 3.97 V 350 mV UNDER VOLTAGE LOCK OUT (UVLO PIN) Start threshold voltage UVLO 1.20 Stop threshold voltage 1.02 Hysteresis 1.24 V 1.10 V 100 mV BIAS VOLTAGE (VBIAS PIN) VBIAS Output voltage IVBIAS = 1 mA, VIN ≥ 12 V 7.5 7.8 8.0 IVBIAS = 1 mA, VIN = 4.5 V 4.4 4.47 4.5 0.888 0.891 0.894 V 0.882 0.891 0.899 V RT Grounded 200 250 300 RT Open 400 500 600 RT = 100 kΩ (1% resistor to AGND) 425 500 575 kHz 25 pF to ground 200 500 ns 25 pF to ground 5 10 ns V REFERENCE SYSTEM ACCURACY TJ = 25°C Reference voltage OSCILLATOR (RT PIN) Internally set PWM switching frequency Externally set PWM switching frequency kHz FALLING EDGE TRIGGERED BIDIRECTIONAL SYNC SYSTEM (SYNC PIN) SYNC out low-to-high rise time (10%/90%) SYNC out high-to-low fall time (1) (90%/10%) (1) Falling edge delay time (1) Delay from rising edge to rising edge of PH pins 180 ° Minimum input pulsewidth (1) RT = 100 kΩ 100 ns Delay (falling edge SYNC to rising edge PH) (1) RT = 100 kΩ 360 ns SYNC out high level voltage 50 kΩ resistor to ground, No pullup resistor 2.5 V SYNC out low level voltage 0.6 SYNC in low level threshold 0.8 V SYNC in high level threshold 2.3 Percentage of programmed frequency SYNC in frequency range (1) V -10% 10% 225 770 V kHz FEED-FORWARD MODULATOR (INTERNAL SIGNAL) Modulator gain VIN = 12 V, TJ = 25°C Modulator gain variation 8 -25% Minimum controllable ON time (1) Maximum duty factor (1) V/V 25% 180 VIN = 4.5 V 80% 86% 60 80 1.0 2.8 ns ERROR AMPLIFIER (VSENSE and COMP PINS) Error amplifier open loop voltage gain (1) Error amplifier unity gain bandwidth (1) Input bias current, VSENSE pin COMP (1) 4 dB MHz 500 Output voltage slew rate (symmetric) (1) 1.5 Specified by design, not production tested. Submit Documentation Feedback nA V/µs TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS (continued) TJ = -40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIOINS MIN TYP MAX UNIT Slow Start/ENABLE (SSENA PIN) Disable low level input voltage Internal slow-start time (10% to 90%) 0.5 fs = 250 kHz, RT = ground (2) fs = 500 kHz, RT = Hi-Z (2) Pullup current source Pulldown MOSFET 4.6 ms 2.3 1.8 II(SSENA) = 1 mA 5 V 10 0.1 µA V POWER GOOD(PWRGD PIN) Power good threshold Rising edge delay (2) PWRGD Rising voltage 97% fs = 250 kHz 4 fs = 500 kHz 2 Output saturation voltage Isink = 1 mA, VIN > 4.5 V 0.05 Output saturation voltage Isink = 100 µA, VIN = 0 V 0.76 Open drain leakage current Voltage on PWRGD = 6 V ms V V 3 µA CURRENT LIMIT Current limit VIN = 12 V Current limit Hiccup Time (2) fs = 500 kHz 7.5 8.5 9.5 A 4.5 ms 165 °C 7 °C THERMAL SHUTDOWN Thermal shutdown trip point Thermal shutdown hysteresis (2) LOW SIDE MOSFET DRIVER (LSG PIN) Turn on rise time, (10%/90%) (2) Deadtime (2) Driver ON resistance VIN = 4.5 V, Capacitive load = 1000 pF 15 VIN = 8 V, Capacitive load = 1000 pF 12 VIN = 12 V 60 VIN = 4.5 V sink/source 7.5 VIN = 12 V sink/source 5 ns ns Ω OUTPUT POWER MOSFETS (PH PIN) Phase node voltage when disabled Voltage drop, low side FET and diode rDS(ON) (2) (3) High side power MOSFET switch (3) DC conditions and no load, SSENA = 0 V 0.5 V VIN = 4.5 V, Idc = 100 mA 1.13 1.42 VIN = 12 V, Idc = 100 mA 1.08 1.38 VIN = 4.5 V, BOOT-PH = 4.5 V, IO = 0.5 A 60 VIN = 12 V, BOOT-PH = 8 V, IO = 0.5 A 40 V mΩ Specified by design, not production tested. Resistance from VIN to PH pins. Submit Documentation Feedback 5 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 VIN VIN UVLO PWRGD RT SYNC SSENA COMP NOTE: THERMAL PAD (17) 16 15 14 13 12 11 10 9 BOOT PH PH LSG VBIAS PGND AGND VSENSE If there is not a Pin 1 indicator, turn device to enable reading the symbol from left to right. Pin 1 is at the lower left corner of the device. Terminal Functions TERMINAL NO. 1, 2 VIN Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor. 3 UVLO Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the internal default VIN start and stop thresholds. 4 PWRGD Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output voltage. There is an internal rising edge filter on the output of the PWRGD comparator. 5 RT Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin to ground or floating will set the frequency to an internally preselected frequency. 6 SYNC Bidirectional synchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The output is a falling edge signal out of phase with the rising edge of PH. SYNC may be used as an input to synchronize to a system clock by connecting to a falling edge signal when an RT resistor is used. See 180° Out of Phase Synchronization operation in the Application Information section. 7 SSENA Slow Start/Enable. The SSENA pin is a dual function pin which provides a logic enable/disable and a slow start time set. Below 0.5 V, the device stops switching. Float pin to enable. Capacitor to ground adjusts the slow start time. See Extending Slow Start Time section. 8 COMP Error amplifier output. Connect frequency compensation network from COMP to VSENSE pins. 9 VSENSE Inverting node error amplifier. 10 AGND Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD. 11 PGND Power Ground—Noisy internal ground—Return currents from the LSG driver output return through the PGND pin. Connect to AGND and PowerPAD. 12 VBIAS Internal 8.0 V bias voltage. A 1.0 µF ceramic bypass capacitance is required on the VBIAS pin. 13 LSG Gate drive for low side MOSFET. Connect gate of n-channel MOSFET. PH Phase node—Connect to external L-C filter. 16 BOOT Bootstrap for high side gate driver. Connect 24 Ohm and 0.1 µF ceramic capacitor from BOOT to PH pins. 17 PowerPAD PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 26 for an example PCB layout. 14, 15 6 DESCRIPTION NAME Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 FUNCTIONAL BLOCK DIAGRAM BOOT VIN PH 320 kΩ Hiccup UVLO UVLO 125 kΩ SYNC Current Limit OC 1.2V 2x Oscillator RT Bias + Drive Regulator PWM Ramp (Feed Forward) PWM Comparator COMP OC VBIAS VSENSE S Q Adaptive Deadtime and VBIAS Contol Logic R LSG Error Amplifier VBIAS2 Thermal Shutdown Reference System PWRGD UVLO 5 µA VSENSE 97% Ref UVLO SS/ENA Hiccup Timer Rising Edge Delay Hiccup TPS54550 POWERPAD VBIAS PGND Submit Documentation Feedback AGND 7 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 DETAILED DESCRIPTION Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) system has an internal voltage divider from VIN to AGND. The defaults for the start/stop values are labeled VIN and given in Table 1. The internal UVLO threshold can be overridden by placing an external resistor divider from VIN to ground. The internal divider values are approximately 320 kΩ for the high side resistor and 125 kΩ for the low side resistor. The divider ratio (and therefore the default start/stop values) is quite accurate, but the absolute values of the internal resistors may vary as much as 15%. If high accuracy is required for an externally adjusted UVLO threshold, select lower value external resistors to set the UVLO threshold. Using a 1-kΩ resistor for the low side resistor R2 (see Figure 1) is recommended. Under no circumstances should the UVLO pin be connected directly to VIN. Table 1. Start/Stop Voltage Threshold START VOLTAGE THRESHOLD STOP VOLTAGE THRESHOLD VIN (Default) 4.49 3.69 UVLO 1.24 1.02 Slow Start Enable (SSENA) and Internal Slow Start Once the SSENA pin voltage exceeds 0.5 V, the TPS54550 starts operation. The TPS54550 has an internal digital slow start that ramps the reference voltage to its final value in 1150 switching cycles. The internal slow start time (10% - 90%) is approximated by the following expression: T 1.15k SS_INTERNAL(ms) ƒ s(kHz) (3) Once the TPS54550 device is in normal regulation, the SSENA pin is high. If the SSENA pin is pulled below the stop threshold of 0.5 V, switching stops and the internal slow start resets. If an application requires the TPS54550 to be disabled, use open drain or open collector output logic to interface to the SSENA pin (see Figure 2). The SSENA pin has an internal pullup current source. Do not use external pullup resistors. Input Voltage Supply R2 5 µA 320 kΩ R1 1 kΩ 125 kΩ Disabled CSS Enabled Figure 2. Interfacing to the SSENA Pin Figure 1. Circuit Using External UVLO Function The equations for selecting the UVLO resistors are: VIN(start) 1 k R1 1k 1.24 V (1) (R1 1 k) 1.02 V VIN(stop) 1 k (2) For applications which require an undervoltage lock out (UVLO) threshold greater than 4.49 V, external resistors may be implemented, see Figure 1, to adjust the start voltage threshold. For example, an application needing an UVLO start voltage of approximately 7.8 V using the equation (1), R1 is calculated to the nearest standard resistor value of 5.36 kΩ. Using Equation 2, the input voltage stop threshold is calculated as 6.48 V. Extending Slow Start Time In applications that use large values of output capacitance there may be a need to extend the slow start time to prevent the startup current from tripping the current limit. The current limit circuit is designed to disable the high side MOSFET and reset the internal voltage reference for a short amount of time when the high side MOSFET current exceeds the current limit threshold. If the output capacitance and load current cause the startup current to exceed the current limit threshold, the power supply output will not reach the desired output voltage. To extend the slow start time and to reduce the startup current, an external capacitor can be added to the SSENA pin. The slow start capacitance is calculated using the following equation: CSS(µF) = 5.55x10-3 Tss(ms) 8 Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Switching Frequency (RT) RT(k) The TPS54550 has an internal oscillator that operates at twice the PWM switching frequency. The internal oscillator frequency is controlled by the RT pin. Grounding the RT pin sets the PWM switching frequency to a default frequency of 250 kHz. Floating the RT pin sets the PWM switching frequency to 500kHz. Connecting a resistor from RT to AGND sets the frequency according to Equation 4 (see Figure 13). ƒ 46000 s(kHz)–35.9 (4) The RT pin controls the SYNC pin functions. If the RT pin is floating or grounded, SYNC is an output. If the switching frequency has been programmed using a resistor from RT to AGND, then SYNC functions as an input. The internal voltage ramp charging current increases linearly with the set frequency and keeps the feed forward modulator constant (Km = 8) regardless of the frequency set point. Table 2. Switching Frequency, SYNC and RT Pins SWITCHING FREQUENCY SYNC PIN RT PIN 250 kHz, internally set Generates SYNC output signal AGND 500 kHz, internally set Generates SYNC output signal Float Externally set to 250 kHz to 700 kHz Externally synchronized frequency Terminate to quiet ground with 10-kΩ resistor. Synchronization Signal 180° Out of Phase Synchronization (SYNC) The SYNC pin is configurable as an input or as an output, per the description in the previous section. When operating as an input, the SYNC pin is a falling-edge triggered signal (see Figure 3 and Figure 4). When operating as an output, the signal's falling edge is approximately 180° out of phase with the rising edge of the PH pins. Thus, two TPS54550 devices operating in a system can share an input capacitor and draw ripple current at twice the frequency of a single unit. R = 215 kΩ to 69 kΩ Use 110 kΩ when RT floats and 237 kΩ when RT is grounded and using the sync out signal of another TPS54550. Set RT resistor equal to 90% to 110% of external synchronization frequency. When operating the two TPS54550 devices 180° out of phase, the total RMS input current is reduced. Thus reducing the amount of input capacitance needed and increasing efficiency. When synchronizing a TPS54550 to an external signal, the timing resistor on the RT pin must be set so that the oscillator is programmed to run at 90% to 110% of the synchronization frequency. NOTE: Do not use synchronization input for designs with output voltages > 10 V. VI(SYNC) VO(PH) Figure 3. SYNC Input Waveform Submit Documentation Feedback 9 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Internal Oscillator VO(PH) VO(SYNC) Figure 4. SYNC Output Waveform Power Good (PWRGD) The VSENSE pin is compared to an internal reference signal, if the VSENSE is greater than 97% and no other faults are present, the PWRGD pin presents a high impedance. A low on the PWRGD pin indicates a fault. The PWRGD pin has been designed to provide a weak pull-down and indicates a fault even when the device is unpowered. If the TPS54550 has power and has any fault flag set, the TPS54550 indicates the power is not good by driving the PWRGD pin low. The following events, singly or in combination, indicate power is not good: • VSENSE pin out of bounds • Overcurrent • Thermal shutdown • UVLO undervoltage • Input voltage not present (weak pull-down) • Slow-starting • VBIAS voltage is low Once the PWRGD pin presents a high impedance (i.e., power is good), a VSENSE pin out of bounds condition forces PWRGD pin low (i.e., power is bad) after a time delay. This time delay is a function of the switching frequency and is calculated using Equation 5: T 1000 ms delay ƒ s(kHz) (5) Bias Voltage (VBIAS) Up to 1 mA of current can be drawn for use in an external application circuit. The VBIAS pin must have a bypass capacitor value of 1.0 µF. X7R or X5R grade dielectric ceramic capacitors are recommended because of their stable characteristics over temperature. Bootstrap Voltage (BOOT) The BOOT capacitor obtains its charge cycle by cycle from the VBIAS capacitor. A capacitor and small value resistor from the BOOT pin to the PH pins is required for operation. The bootstrap connection for the high side driver must have a bypass capacitor of 0.1 µF and resistor 24 Ohm. Error Amplifier The VSENSE pin is the error amplifier inverting input. The error amplifier is a true voltage amplifier with 1.5 mA of drive capability with a minimum of 60 dB of open loop voltage gain and a unity gain bandwidth of 2 MHz. Voltage Reference The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. During production testing, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure improves the regulation, since it cancels offset errors in the scaling and error amplifier circuits. The VBIAS regulator provides a stable supply for the internal analog circuits and the low side gate driver. 10 Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 PWM Control and Feed Forward Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, PWM latch, and the adaptive dead-time control logic. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is reset, the low-side driver and integrated pull-down MOSFET remain on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to the valley voltage. When the ramp begins to charge back up, the low-side driver turns off and the high-side FET turns on. The peak PWM ramp voltage varies inversely with input voltage to maintain a constant modulator and power stage gain of 8 V/V. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side driver remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output can be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the internal low-side FET and driver on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set point, setting VSENSE to approximately the same voltage as the internal voltage reference. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The internal low-side FET and low side driver remain on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54550 is capable of sinking current through the external low side FET until the output voltage reaches the regulation set point. reference ramps from 0 V to 0.891 V. During the initial slow-start interval, the internal reference voltage is very small resulting in a couple of skipped pulses because the minimum on time causes the actual output voltage to be slightly greater than the preset output voltage until the internal reference ramps up. Deadtime Control Adaptive dead time control prevents shoot through current from flowing in the integrated high-side MOSFET and the external low-side MOSFET during the switching transitions by actively controlling the turn on times of the drivers. The high-side driver does not turn on until the voltage at the gate of the low-side MOSFET is below 1 V. The low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 1 V. Low Side Gate Driver (LSG) LSG is the output of the low-side gate driver. The 100-mA MOSFET driver is capable of providing gate drive for most popular MOSFETs suitable for this application. Use the SWIFT Designer Software Tool to find the most appropriate MOSFET for the application. Connect the LSG pin directly to the gate of the low-side MOSFET. Do not use a gate resistor as the resulting turn-on time may be too slow. Thermal Shutdown The device uses the thermal shutdown to turn off the MOSFET drivers and controller if the junction temperature exceeds 165°C. The device is restarted automatically when the junction temperature decreases to 7°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. The minimum on time is designed to be 180 ns. During the internal slow-start interval, the internal Submit Documentation Feedback 11 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Overcurrent Protection Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET and compared to a voltage level which represents the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit for more than 100 ns, the high-side MOSFET is disable, the SSENA pin is pulled low, and the internal digital slow-start is reset to 0 V. SSENA is held low for approximately the time that is calculated by Equation 6: T 2250 HICCUP(ms) ƒ s(kHz) (6) Once the hiccup time is complete, the SSENA pin is released and the converter initiates the internal slow-start. Setting the Output Voltage The output voltage of the TPS54550 can be set by feeding back a portion of the output to the VSENSE pin using a resistor divider network. In the application circuit of Figure 29, this divider network is comprised of resistors R1 and R2. To calculate the resistor values to generate the required output voltage use the following equation: R2 R1 0.891 V O 0.891 (7) Start with a fixed value of R1 and calculate the required R2 value. Assuming a fixed value of 10 kΩ for R1, the following table gives the appropriate R2 value for several common output voltages: 12 OUTPUT VOLTAGE (V) R2 VALUE (kΩ) 1.2 28.7 1.5 14.7 1.8 9.76 2.5 5.49 3.3 3.74 Output Voltage Limitations Due to the internal design of the TPS54550 there are both upper and lower output voltage limits for any given input voltage. Additionally, the lower boundary of the output voltage set point range is also dependent on operating frequency. The upper limit of the output voltage set point is constrained by the maximum duty cycle of the device and is shown in Figure 12. The lower limit is constrained by the minimum controllable on time which may be as high as 220 ns. The approximate minimum output voltage for a given input voltage and range of operating frequencies is shown in Figure 8 while the maximum operating frequency versus input voltage for some common output voltages is shown in Figure 10. The curves shown in these two figures are valid for output currents greater than 0.5 A. As output currents decrease towards no load (0 A), the minimum output voltage decreases. For applications where the load current is less than 100 mA, the curves shown in Figure 9 and Figure 11 are applicable. All of the data plotted in these curves are approximate and take into account a possible 20 percent deviation in actual operating frequency relative to the intended set point. Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 TYPICAL CHARACTERISTICS ON RESISTANCE vs JUNCTION TEMPERATURE CURRENT LIMIT vs INPUT VOLTAGE 0.8912 Vref − Internal Voltage Reference − V 8.50 90 TJ = 25°C 80 70 8.25 VIN = 4.5 V 60 Current Limit - A On Resistance - mW INTERNAL VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 50 40 VIN = 12 V 30 8 7.75 20 10 0 -50 7.50 0 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C 0.8900 0.8898 −50 −25 25 0 25 50 75 100 125 150 TJ − Junction Temperature − C MINIMUM OUTPUT VOLTAGE vs INPUT VOLTAGE MAXIMUM SWITCHING FREQUENCY vs INPUT VOLTAGE 800 5.5 IO = 0 A 5 700 kHz 4.5 700 kHz 3.5 600 kHz 500 kHz 3 400 kHz 2 1.5 1 300 kHz 600 kHz 4 500 kHz 3.5 400 kHz 3 300 kHz 2.5 2 1.5 1 0.5 200 kHz 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Maximum Switching Frequency − kHz IO > 0.5 A Minimum Output Voltage − V Minimum Output Voltage − V 0.8902 MINIMUM OUTPUT VOLTAGE vs INPUT VOLTAGE 0.5 200 kHz VO = 2.5 V VO = 3.3 V 700 600 500 400 VO = 1.8 V 300 VO = 1.5 V 200 VO = 0.9 V VO = 1.2 V 100 IO > 0.5 A 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI − Input Voltage − V 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI − Input Voltage − V VI − Input Voltage − V Figure 8. Figure 9. Figure 10. MAXIMUM SWITCHING FREQUENCY vs INPUT VOLTAGE MAXIMUM OUTPUT VOLTAGE vs INPUT VOLTAGE RT RESISTANCE vs SWITCHING FREQUENCY 800 VO = 1.8 V 14 225 12 200 10 175 VO = 2.5 V 700 500 400 300 200 VO = 0.9 V 100 VO = 1.2 V VO = 1.5 V IO < 0.1 A 0 RT Resistance − k VO = 3.3 V 600 V O − Output Voltage − V Maximum Switching Frequency − kHz 0.8904 Figure 7. 4 0 0.8906 Figure 6. 4.5 2.5 10 15 20 VI - Input Voltage - V 0.8908 Figure 5. 5.5 5 5 VIN = 12 V 0.8910 8 6 4 VI − Input Voltage − V Figure 11. 125 100 75 2 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 150 0 5 10 15 20 25 50 200 300 400 500 600 V I − Input Voltage − V Switching Frequency − kHz Figure 12. Figure 13. Submit Documentation Feedback 700 13 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 TYPICAL CHARACTERISTICS (continued) VIN (UVLO) START AND STOP vs FREE-AIR TEMPERATURE ENABLED SUPPLY CURRENT vs INPUT VOLTAGE 4.5 DISABLED SUPPLY CURRENT vs INPUT VOLTAGE 1.3 10 TJ = 25°C ICC - Supply Current - mA VI − Input Voltage − V Switching 8 Start 4.1 3.9 Stop 3.7 3.5 −50 −25 6 4 Non Switching 2 25 50 75 0 100 125 150 5 25 0 5 10 15 20 POWER GOOD THRESHOLD vs JUNCTION TEMPERATURE POWER GOOD DELAY vs SWITCHING FREQUENCY 4.5 98.0 6.5 6.0 5.5 5.0 4.5 4.0 5 10 15 20 4 Power Good Delay − ms 7.0 97.5 97.0 96.5 3.5 3 2.5 2 1.5 1 0.5 96.0 −50 −25 25 25 VI − Input Voltage − V BIAS VOLTAGE vs INPUT VOLTAGE PWRGD − Power Good Threshold − % VBIAS − Bias Voltage − V 10 15 20 VI - Input Voltage - V Figure 16. 7.5 VI − Input Voltage − V 0 0 25 50 75 250 100 125 150 350 450 550 650 750 Switching Frequency − kHz TJ − Junction Temperature − C Figure 17. Figure 18. Figure 19. PH VOLTAGE vs PH SINK CURRENT SLOW START CAPACITANCE vs TIME INTERNAL SLOW START TIME vs SWITCHING FREQUENCY 1.75 VI = 4.5 V 1.50 VI = 12 V 1.25 0.50 5 0.45 4.5 0.40 Slow Start Time − ms Slow Start Capacitance − mF 2 0.35 0.30 0.25 0.20 0.15 150 200 250 I CC − Supply Current − mA Figure 20. 300 3.5 3 2.5 2 1.5 0 1 4 0.10 0.05 14 1.0 Figure 15. TJ = 25°C 100 1.1 Figure 14. 8.0 0 1.2 0.9 0 0 TA − Free-Air Temperature − C PH Voltage − V Disabled Supply Current − mA TJ = 25°C 4.3 0 10 20 30 40 50 60 70 t − Time − ms Figure 21. Submit Documentation Feedback 80 1 250 350 450 550 650 Switching Frequency − kHz Figure 22. 750 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 TYPICAL CHARACTERISTICS (continued) HICCUP TIME vs SWITCHING FREQUENCY FREE-AIR TEMPERATURE vs MAXIMUM OUTPUT CURRENT 10 7 6 5 4 2.5 100 PD - Power Dissipation - W TA - Free-Air Temperature - °C 8 Hiccup Time − ms 3 125 9 75 50 VI = 12 V, VO = 3.3 V 25 3 2 250 POWER DISSIPATION vs FREE-AIR TEMPERATURE 0 350 450 550 650 Switching Frequency − kHz Figure 23. 750 2 1.5 1 qJA = 40.1 °C/W 0.5 0 0 1 2 3 4 5 IO - Output Current - A 6 Figure 24. Submit Documentation Feedback 7 25 50 75 100 TA - Free-Air Temperature - °C 125 Figure 25. 15 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 APPLICATION INFORMATION INPUT BULK FILTER Vin TOPSIDE GROUND AREA INPUT BYPASS CAPACITOR UNDER VOLTAGE LOCK OUT RESISTOR DIVIDER VIN BOOT VIN PH UVLO PH VOUT PH 3.3 OR 5 V PWRGD POWER GOOD PULLUP TERMINATION RES. (10 K) RT FREQUENCY SET RESISTOR OUTPUT FILTER CAPACITOR LOW SIDE FET BOOT CAPACITOR AND RESISTOR OUTPUT INDUCTOR LSG EXPOSED POWERPAD AREA VBIAS SYNC PGND SS/ENA AGND BIAS CAPACITOR VSENSE COMP SLOW START CAPACITOR COMPENSATION NETWORK ANALOG GROUND TRACE VIA BACKSIDE or INTERNAL LAYER TRACE Figure 26. TPS54550 PCB Layout PCB LAYOUT The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and source of the low side MOSFET. The minimum recommended bypass capacitance is 10-µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the low side MOSFET. See Figure 26 for an example of a board layout. The AGND and PGND pins should be tied to the PCB ground plane at the pins of the IC. The source of the low-side MOSFET should be connected directly to the PCB ground plane. The PH pins should be tied together and routed to the drain of the low-side MOSFET. Since the PH connection is the switching node, the MOSFET should be located very close to the PH pins, and the area of the PCB 16 conductor minimized to prevent excessive capacitive coupling. The recommended conductor width from pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce to 2-ounce copper. The length of the copper land pattern should be no more than 0.2 inch. For operation at full rated load, the analog ground plane must provide adequate heat dissipating area. A 3-inch by 3-inch plane of copper is recommended, though not mandatory, dependent on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the bottom or top layers also help dissipate heat, and any area available should be used when 5 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013-inch diameter vias to avoid solder wicking through the vias. Four vias should be in the PowerPAD area with four additional vias outside the pad area and underneath the package. Additional vias beyond those recommended to enhance thermal performance should be included in areas not under the device package. Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Minimum recommended exposed copper area for PowerPAD. Some stencils may require 10 percent larger area. 0.197 0.013 DIA 8 PL 0.015 x 16 Minimum recommended thermal vias: 4 x 0.013 dia. Inside exposed PowerPAD area and 4 x 0.013 dia. Under device as shown. Additional vias may be used if top side ground area is extended. 0.0256 0.050 0.040 0.120 0.050 0.040 Minimum recommended top side Analog Ground area. 0.230 Connect Pin 10 AGND and Pin 11 PGND to Analog Ground plane in this area for optimum performance. 0.134 0.080 Figure 27. Thermal Considerations for PowerPAD Layout MODEL FOR LOOP RESPONSE The Figure 28 shows an equivalent model for the TPS54550 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier in the TPS54550 is a voltage amplifier with 80 dB (10000 V/V) of open loop gain. The error amplifier can be modeled using an ideal voltage-controlled current source as shown in Figure 28 with a resistor and capacitor on the output. The TPS54550 device has an integrated feed forward compensation circuit which eliminates the impact of the input voltage changes to the overall loop transfer function. The feed forward gain is modeled as an ideal voltagecontrolled voltage source with a gain of 8 V/V. The 1-mV ac voltage between nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting b/c shows the small-signal response of the power stage. Plotting c/a shows the small-signal response of the frequency compensation. Plotting a/b shows the small-signal response of the overall loop. The dynamic load response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. Submit Documentation Feedback 17 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 LO Rdc a PH 1 mV R(switch) + + – 10 MΩ – ESR RL b CO 40 mΩ R5 R1 TPS54550 8 V/V C8 VSENSE + – 20 V/V – 10 MΩ + 10 MΩ – + 50 pF 50 µA/V R2 0.891 R3 REF C7 C6 COMP c Figure 28. Model of Control Loop + Figure 29. Application Circuit, 3.3 V Output Figure 29 shows the schematic for a typical TPS54550 application. The TPS54550 can provide up to 5-A output current at a nominal output voltage of 3.3 V. For proper thermal performance, the exposed PowerPAD underneath the device must be soldered down to the printed circuit board. DESIGN PROCEDURE The following design procedure can be used to select component values for the TPS54550. Alternately, the SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. To begin the design process a few parameters must be decided upon. The designer needs to know the following: 18 Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 • • • • • • Input voltage range Output voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency VIN I OUT(MAX) 0.25 C BULK ƒ sw I OUT(MAX) ESR MAX (9) Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the bulk capacitor value and ESRMAX is the maximum series resistance of the bulk capacitor. For this design example, use the following as the input parameters: DESIGN PARAMETER EXAMPLE VALUE Input voltage range 6 V to 17 V Output voltage 3.3 V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 5A Operating frequency 700 kHz NOTE: As an additional constraint, the design is set up to be small size and low component height. SWITCHING FREQUENCY The switching frequency is set using the RT pin. Grounding the RT pin sets the PWM switching frequency to a default frequency of 250 kHz. Floating the RT pin sets the PWM switching frequency to 500 kHz. By connecting a resistor from RT to AGND, any frequency in the range of 250 to 700 kHz can be set. Use Equation 8 to determine the proper value of RT. 46000 RT(k) ƒ s(kHz) 35.9 (8) In this example circuit, the desired frequency is 700 kHz and RT is 69.8 kΩ. switching INPUT CAPACITORS The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be approximated by Equation 10: I OUT(MAX) I CIN 2 (10) In this case the input ripple voltage would be 140 mV and the RMS ripple current would be 2.5 A. It is also important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in Figure 34 and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen bulk and bypass capacitors are each rated for 25 V and the combined ripple current capacity is greater than 3 A, both providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded under any circumstance. OUTPUT FILTER COMPONENTS Two components need to be selected for the output filter, L1 and C2. Since the TPS54550 is an externally compensated device, a wide range of filter component types and values can be supported. The TPS54550 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The minimum recommended value for the decoupling capacitor, C9, is 10 µF. A high quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be used so long as all other requirements are met, however 10 µF has been shown to work well in a wide variety of circuits. Additionally some bulk capacitance may be needed, especially if the TPS54550 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage is acceptable. Inductor Selection This input ripple voltage can be approximated by Equation 9: For this design example use KIND = 0.3 and the minimum inductor value is calculated to be 3 µH. For this design a large value was chosen, 6.8 µH. To calculate the minimum value of the output inductor, use Equation 11: V V V OUT(MAX) IN(MAX) OUT L MIN V K I F IN(max) IND OUT SW (11) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. I general this value is at the discretion of the designer, however the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher ESR output capacitors, KIND = 0.2 yields better results. Submit Documentation Feedback 19 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 12: 2 I L(RMS) 1 I2 OUT(MAX) 12 V V OUT V IN(MAX) V OUT IN(MAX) L OUT F SW 0.8 (12) and the peak inductor current can be determined with Equation 13: V I L(PK) I OUT(MAX) OUT V IN(MAX) V 1.6 V IN(MAX) L OUT SW (13) Capacitor Selection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With high switching frequencies such as the 700-kHz frequency of this design, internal circuit limitations of the TPS54550 limit the practical maximum crossover frequency to about 50 kHz. Additionally, to allow for adequate phase gain in the compensation network, the the closed loop crossover frequency should be at least 30 percent higher than the LC corner frequency. This limits the minimum capacitor value for the output filter to: K 2 C 1 OUT 2ƒCO LOUT ) (14) Where K is the frequency multiplier for the spread between fLC and fCO. K should be between 1.3 and 15, typically 10 for one decade difference.For a desired crossover of 13 kHz and a 6.8-µH inductor, the minimum value for the output capacitor is around 20 VOUT VIN(MAX) V OUT ICOUT(RMS) 1 12 V L F N IN(MAX) OUT SW C OUT F For this design, the RMS inductor current is 5.04 A and the peak inductor current is 5.35 A. The chosen inductor is a Sumida CDRH105-6R8 6.8 µH. It has a saturation current rating of 5.4 A and a RMS current rating of 5.4 A, meeting these requirements. A smaller value inductor could be used, however this value was chosen because it has the largest value in this style that met the current rating requirements. Larger value inductors will have lower ac current and result in lower output voltage ripple. In general, inductor values for use with the TPS54550 are in the range of 6.8 µH to 47µH. ( 39 µF. In this design a more consevative frequency multiplier of 3 is used resulting in a desired output capacitance of 200 µF. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the output capacitor is given by Equation 15: (15) where NC is the number of output capacitors in parallel. The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter so the maximum specified ESR as listed in the capacitor data sheet is given by Equation 16: ESR MAX N C V IN(MAX) L V OUT OUT F SW 0.8 V IN(MAX) V OUT V pp(MAX) (16) Where ∆Vp-p is the desired peak-to-peak output ripple. For this design example, two 100-µF ceramic output capacitors are chosen for C2 and C10. These are TDK C3225X5R0J107M, rated at 6.3 V with a maximum ESR of 2 mΩ and a ripple current rating in excess of 3 A. The calculated total RMS ripple current is 161 mA ( 80.6 mA each) and the maximum total ESR required is 43 mΩ. These output capacitors exceed the requirements by a wide margin and will result in a reliable, high performance design. it is important to note that the actual capacitance in circuit may be less than the catalog value when the output is operating at the desired output of 3.3 V. Other capacitor types work well with the TPS54550, depending on the needs of the application. COMPENSATION COMPONENTS The external compensation used with the TPS54550 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses type 3 compensation consisting of R1, R3, R5, C6, C7 and C8. Additionally, R2 along with R1 forms a voltage divider network that sets the output voltage. These component reference designators are the same as those used in the SWIFT Designer Software. There are a number of different ways to design a compensation network. This procedure outlines a relatively simple procedure that produces good results with most output filter combinations. Use Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 of the SWIFT Designer Software for designs with unusually high closed loop crossover frequencies, low value, low ESR output capacitors such as ceramics or if the designer is unsure about the design procedure is recommended. When designing compensation networks for the TPS54550, a number of factors need to be considered. The gain of the compensated error amplifier should not be limited by the open loop amplifier gain characteristics and should not produce excessive gain at the switching frequency. Also, the closed loop crossover frequency should be set less than one fifth of the switching frequency, and the phase margin at crossover must be greater than 45 degrees. The general procedure outlined here produces results consistent with these requirements without going into great detail about the theory of loop compensation. First calculate the output filter LC corner frequency using equation Equation 17: 1 ƒ LC 2 L C OUT OUT (17) For the design example, fLC = 4315 Hz. The closed loop crossover frequency should be greater than fLC and less than one fifth of the switching frequency. Also, the crossover frequency should not exceed 50 kHz, as the error amplifier may not provide the desired gain. For this design, a crossover frequency of 13 kHz was chosen. This value is chosen for comparatively wide loop bandwidth while still allowing for adequate phase boost to insure stability. Next calculate the R2 resistor value for the output voltage of 3.3 V using Equation 18: R1 0.891 R2 V 0.891 OUT (18) For any TPS54550 design, start with an R1 value of 1.0 kΩ. R2 is then 374 Ω. Now the values for the compensation components that set the poles and zeros of the compensation network can be calculated. Assuming that R1 > R5 and C6 > C7, the pole and zero locations are given by equations 19 through 22: 1 2R3C6 1 ƒ Z2 2R1C8 1 ƒ P1 2R5C8 1 ƒ P2 2R3C7 ƒ Z1 (19) (20) (21) (22) Additionally there is a pole at the origin, which has unity gain with the following frequency: 1 ƒ INT 2R1C6 (23) This pole is used to set the overall gain of the compensated error amplifier and determines the closed loop crossover frequency. There are a number of popular ways to design Type 3 compensation networks. The theory behind these calculations is beyond the scope of this document. It is always best to to use any calculated compensation values as the basis for an initial design, and then verify the actual closed loop response. The initial values may then be adjusted to suit the individual design requirements. The SWIFT software design tool can also be used to provide an intial circuit design. In this circuit, the first compensation zero was set at approximately one half the LC corner frequency, with the second zero slightly below that to increase the phase gain prior to the double pole of the LC output filter. At the LC corner frequency the overall phase response rapidly drops by 180 degrees, so it is imprtant to increase the initial phase of 90 degrees prior to the LC corner. The two compensation poles are set high enough to to not cause loss of phase margin at the closed loop cross over and low enough to not cause the error amplifier gain to exceed the unity gain bandwidth limit of the internal operational amplifier. The integrator frequency is then chasen to set the overall gain and crossover frequency. This results frequencies: in the following pole and zero fZ1 = 2340 Hz fZ2 = 1591 Hz fP1 = 120 kHz fP2 = 159 kHz fINT = 234 Hz Submit Documentation Feedback 21 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 The measured overall loop response for the circuit is given in Figure 5. Note that the actual closed loop crossover frequency is higher than intended at about 25 kHz. this is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feedforward gain circuitry. Overall the design has greater than 60 degrees of phase margin and will be completely stable over all combiations of line and load variability. C7 1 8R3ƒ CO (30) Note that capacitors are only available in a limited range of standard values, so the nearest standard value has been chosen for each capacitor. The measured closed loop response for this design is shown in Figure 30. BIAS AND BOOTSTRAP CAPACITORS Since R1 is given as 10 kΩ and the crossover frequency is selected as 13 kHz, the desired fINT can be calculated with Equation 24: 10–0.9 ƒ CO ƒ INT 2 (24) And the value for C6 is given by Equation 25: 1 C6 2R1ƒ INT (25) The first zero, fZ1, is located at one half the output filter LC corner frequency, so R3 can be calculated from Equation 26: 1 R3 C6ƒ LC (26) The second zero, fZ2, is located at the output filter LC corner frequency, so C8 can be calculated from Equation 27: 1 C8 2R1ƒ LC (27) The first pole, fP1, is located to coincide with the output filter ESR zero frequency. This frequency is given by Equation 28: 1 ƒ ESR 2R C ESR OUT (28) where RESR is the equivalent series resistance of the output capacitor. In this case, the ESR zero frequency is 35.4 kHz, and R5 can be calculated from Equation 29: 1 R5 2C8 ƒ ESR (29) The final pole is placed at a frequency above the closed loop crossover frequency high enough to not cause the phase to decrease too much at the crossover frequency while still providing enough attenuation so that there is little or no gain at the switching frequency. The fP2 pole location for this circuit is set to 4 times the closed loop crossover frequency and the last compensation component value C7 can be derived from Equation 30: Every TPS54550 design requires a bootstrap capacitor, C3 and a bias capacitor, C4. The bootstrap capacitor must be 0.1 µF. The bootstrap capacitor is located between the PH pins and BOOT pin. In addition, a 24 ohm resistor is placed in series with the bootstrap capacitor. This resistor is used to slow down the leading edge of the high side FET turn on waveform. Using this resistor will dramatically decrease the amplitude of the overshoot on the swtching node. The bias capacitor is connected between the VBIAS pin and AGND. The value should be 1.0 µF. Both capacitors should be high quality ceramic types with X7R or X5R grade dielectric for temperature stability. They should be placed as close to the device connection pins as possible. LOW-SIDE FET The TPS54550 is designed to operate using an external low-side FET, and the LSG pin provides the gate drive output. Connect the drain to the PH pin, the source to PGND, and the gate to LSG. The TPS54550 gate drive circuitry is designed to accommodate most common n-channel FETs that are suitable for this application. The SWIFT Designer Software can be used to calculate all the design parameters for low-side FET selection. There are some simplified guidelines that can be applied that produce an acceptable solution in most designs. The selected FET must meet the absolute maximum ratings for the application: Drain-source voltage (VDS) must be higher than the maximum voltage at the PH pin, which is VINMAX + 0.5 V. Gate-source voltage (VGS) must be greater than 8 V. Drain current (ID) must be greater than 1.1 x IOUTMAX. Drain-source on resistance (rDSON) should be as small as possible, less than 30 mΩ is desirable. Lower values for rDSON result in designs with higher efficiencies. It is important to note that the low-side FET on time is typically longer than the high-side FET on time, so attention paid to low-side FET parameters can make a marked improvement in overall efficiency. Total gate charge (Qg) must be less than 50 nC. Again, lower Qg characteristics result in higher efficiencies. 22 Submit Documentation Feedback TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Vishay Siliconix SI7110 20-V n-channel MOSFET is used as the low-side FET. This particular FET is specifically designed to be used as a low-side synchronous rectifier. POWER GOOD The TPS54550 is provided with a power good output pin PWRGD. This output is an open drain output and is intended to be pulled up to a 3.3-V or 5-V logic supply. A 10-kΩ, pull-up resistor works well in this application. The absolute maximum voltage is 6 V, so care must be taken not to connect this pull-up resistor to VIN if the maximum input voltage exceeds 6 V. Submit Documentation Feedback 23 TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 APPLICATION CURVES (see Figure 29) LOOP RESPONSE LOAD REGULATION 210 60 180 0.15 0.1 0.1 40 120 90 30 60 Gain 20 10 30 VI = 12 V, VO = 3.3 V, IO = 2.5 A, fS = 700 kHz 0 -10 -20 0 -30 Load Regulation - % 150 Phase - Degrees G - Gain - dB Phase 50 LINE REGULATION 0.15 VI = 9 V 0.05 Output Regulation - % 70 VI = 6 V VI = 15 V 0 VI = 17 V -0.05 IO = 2.5 A IO = 5 A 0.05 0 IO = 0 A -0.05 VI = 12 V -0.1 -0.1 -0.15 -0.15 -60 See Figure 17 -30 10 100 1k 10 k f - Frequency - Hz 100 k -90 1M 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 IO - Output Current - A 7 8 9 10 11 12 13 14 15 16 17 VI - Input Voltage - V Figure 30. Figure 31. Figure 32. EFFICIENCY vs OUTPUT CURRENT INPUT RIPPLE VOLTAGE OUTPUT RIPPLE VOLTAGE 100 VI(Ripple) = 100 mV/div (ac) coupled VI = 6 V VO = 10 mV/div (ac) coupled VI = 9 V Efficiency - % 95 90 See Figure 17 See Figure 17 V(PH) = 2 V/div V(PH) = 2 V/div VI = 12 V 85 VI = 15 V VI = 17 V 80 VO = 3.3 V, fS = 700 kHz VI = 7 V, VO = 3.3 V, IO = 5 A, fS = 700 kHz VI = 7 V, VO = 3.3 V, IO = 5 A, fS = 700 kHz Time - 500 ns/div Time - 500 ns/div 75 0 1 2 3 4 IO - Output Current - A 5 Figure 33. Figure 34. Figure 35. LOAD TRANSIENT RESPONSE VI = 12 V, VO = 3.3 V, fS = 700 kHz, See Figure 17 POWER UP VI = 5 V/div VO = 50 mV/div (ac) coupled VO = 2 V/div IO = 1 A/div, 1.25 A to 3.75 A Step Time - 5 ms/div Time - 200 ms/div Figure 36. 24 Submit Documentation Feedback Figure 37. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS54550PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54550PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54550PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54550PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated