TI TPS65030

TPS65030
www.ti.com
SLVS620 – FEBRUARY 2006
POWER MANAGEMENT IC for USB-OTG
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
4 Regulated Output Voltages with 3%
Tolerance
– Fractional Charge Pump for 5 V/100 mA
– Fractional Charge Pump for 1.5 V/200 mA
– Doubling Charge Pump With LDO Mode for
3.3 V/22 mA
– LDO for 1.8 V/60 mA
Switching Frequency 1 MHz
3 V to 5 V Operating Input Voltage Range at
VCC Pin
Sleep Mode Sets Vout2 and Vout3 Into LDO
Mode
Sleep Mode Reduces Quiescent Current of
Vout2, Vout3, and Vout4 to 8 µA Each
internal Bus Switch
Vbus Comparator
Internal Soft Start Limits Inrush Current
Low Input Current Ripple and Low EMI
Overcurrent and Overtemperature Protected
Undervoltage Lockout With Hysteresis
Ultra-Small 2,5 mm x 2,7 mm Chip Scale
Package Applications
DESCRIPTION
The TPS65030 contains three charge pumps and one
LDO to generate all supply voltages necessary for an
USB On-The-Go (OTG) implementation using
TUSB6010. The charge pumps are optimized for a
single Li-Ion cell input or for 5 V from the USB bus.
The input voltage range is 3 V to 5 V for the battery
voltage. High efficiency is achieved by using
fractional conversion techniques for the charge
pumps in combination with a power saving sleep
mode. The current controlled charge pumps in
addition ensure low input current ripple and low EMI.
Small size external ceramic capacitors are required to
build a complete power supply solution. To reduce
board space to a minimum, the device switches at
1-MHz operating frequency, and is available in a
small 25-ball lead free chip scale package (YZK).
TPS65030
3 V . . .4.2 V (5 V)
10 mF
VIN
Vbus
EN1 (5 V)
Charge CF1A+
Pump
CF1A−
EN2 (3.3 V
and 1.5 V)
CF1B+
1 mF
1 mF
CF1B−
EN3 (1.8 V)
Vout2
APPLICATIONS
Power Supply for USB OTG for:
– Cellular Phones
– Smart Phones
– PDAs
– Handheld PCs
– Digital Cameras
– Camcorders
5 V/100 mA
4.7 mF
VIN
SLEEP
•
C o1
3.3 V/22 mA
Co2
1 mF
PGood
Charge
Pump
SW_EN1
CF2+
100 nF
CF2−
SW_EN2
Vout3
Test SRP
Co3
1.5 V/200 mA
10 mF
Charge
Pump
PGND
CF3+
CF3−
1 mF
PGND
GND
1.8 V/60 mA
Vout4
LDO
C o4
1 mF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS65030
www.ti.com
SLVS620 – FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PACKAGED DEVICES (1)
PACKAGE
MARKING
TPS65030YZK
Chip scale
PJMI
The YZK package is available in tape and reel. Add R suffix (TPS65030YZKR) to order quantities of
3000 parts per reel. Add T suffix (TPS65030YZKT) to order quantities of 250 parts per reel.
PACKAGE DIMENSIONS
PACKAGED DEVICES
(1)
TPS65030YZK
(1)
D MAXIMUM
E MAXIMUM
2,708 mm
2,51 mm
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VS
(1)
Supply voltage at VIN, Vbus
Voltage at EN1, EN2, EN3, SLEEP, SW_EN1, SW_EN2, PG, Test SRP
IO
VALUE
UNIT
–0.3 to 7
V
–0.3 V to VIN
Output current at Vbus
200
mA
Output current at Vout2
40
mA
Output current at Vout3
300
mA
Output current at Vout4
100
mA
TJ
Maximum junction temperature,
150
°C
TA
Operating free-air temperature,
–40 to 85
°C
Tstg
Storage temperature,
-65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges; HBM according to EIA/JESD22-A114-B; MM
according EIA/JESD22-A115-A and CDM according EIA/JESD22C101C, however, it is advised that precautions should be taken to
avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the
device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be
connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type
are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available
from Texas Instruments.
2
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SLVS620 – FEBRUARY 2006
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
25-ball chip scale (YZK)
1.7 W
17 mW/°C
940 mW
680 mW
(1)
The thermal resistance junction to ambient of the 5 x 5 ball chip scal package is 58°C/W when soldered on a double sided board.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VS
IO
CI
CO1
Supply voltage at VIN
NOM
3
MAX
5
UNIT
V
Maximum output current at Vbus
100
mA
Maximum output current at Vout2
22
mA
Maximum output current at Vout3
200
mA
Maximum output current at Vout4
50
mA
Input capacitor at VIN
8
10
Output capacitance at Vbus
3
4.7
Output capacitance at Vbus required for stability, for VI ≤ 4.2 V
µF
6.5 (1)
µF
µF
2
CO2
Output capacitance at Vout2
0.8
1
µF
CO3
Output capacitance at Vout3
8
10
µF
CO4
Output capacitance at Vout4
0.8
1
µF
Capacitance for flying capacitor, CF1A, CF1B
0.8
1
µF
Capacitance for flying capacitor CF3
0.7
1
µF
Capacitance for flying capacitor CF2
0.077
0.1
µF
TJ
(1)
Operating junction temperature
–40
125
°C
Per USB spec
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ELECTRICAL CHARACTERISTICS
VIN = 3.6 V, CI = 10 µF, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT
VI
Input Voltage Range, VIN
UVLO
Undervoltage lockout threshold
IS
ISD
3
5
Input voltage at VCC rising
3
V
V
Undervoltage lockout hysteresis
80
Supply current in normal mode if EN1=1,
(Vbus)
55
80
µA
Supply current in normal mode if EN2=1,
(Vout2, Vout3)
70
95
µA
Supply current in normal mode if
EN2=EN3=1, (Vout2, Vout3, Vout4)
80
115
µA
110
145
µA
125
170
µA
Supply current in sleep mode if EN2=1,
(SLEEP, Vout2, Vout3)
25
30
µA
Supply current in sleep mode if
EN2=EN3=1, (SLEEP, Vout2, Vout3,
Vout4)
30
38
µA
0.12
1
µA
Supply current in normal mode if
EN1=EN2=1, (Vbus, Vout2, Vout3)
Supply current in normal mode if
EN1=EN2=EN3=1, (Vbus, Vout2, Vout3,
Vout4)
mV
VI = 4.2 V
Shutdown current
CHARGE PUMP STAGE FOR Vbus
VBUS Output voltage
VO
Output voltage tolerance
Output voltage ripple
IO
5
–4%
30
real cap including aging, dc bias
40
For Vbus > 2.5 V or SRP = high
Output current limit
For Vbus > 2.5 V, Vbus > VI– 0.5 V
Output current for Session Request
Protocol (SRP)
For Vbus < 2.5 V, SRP = low
Output current
Vbus shorted to GND, SRP = high
0.5
mA
160
325
mA
1.3
1.7
mA
325
mA
30
mA
Startup time
CO1 = 2 × 4.7 µF, IO = 100 mA (1), excluding
time for SRP (2)
500
µs
Startup time
CO1 = 106 µF, IO = 100 mA (1), excluding time
for SRP (2)
4.5
ms
f
Switching frequency
η
Efficiency
0.83
VIN = 3.6 V, IO1 = 100 mA
Output resistance when disabled
1
400
EN1 = 0
for Vbus >2.5 V, otherwise IO = 0 mA
Startup time is measured from ENx-pin going high to VO within nominal value
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1.17
MHz
650
mA
100
kR
85%
Input current limit
4
mVPP
100
Skip current limit
(1)
(2)
3%
CO1 = 4.7 µF, IO1 = 100 mA
Maximum output current
V
40
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SLVS620 – FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, CI = 10 µF, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE PUMP STAGE FOR Vout2
Output voltage, Vout2
Normal mode
3.3
Output voltage tolerance
VO
Output voltage ripple
IO
VO
–3%
15
real cap including aging, dc bias (0.58 µF)
30
Normal mode
Output current limit
Normal mode (1)
50
Output voltage, Vout2
Sleep mode (LDO mode only)
3.3
Output voltage tolerance in sleep mode
VO drops with the battery for an input voltage less
than 3.3 V
Maximum output current
Sleep mode
Voltage drop in sleep mode
Sleep mode, IO2 = 100 µA
Output current limit in sleep mode
Vout2 shorted to GND
mVPP
22
mA
– 10%
70
CO2 = 1 µF, IO2 = 22 mA (2)
f
Switching frequency
η
Efficiency
VIN = 3.6 V, IO2 = 22 mA , Vout2 = 3.3 V
0.83
Input current limit
LDO mode
Input current limit
Charge pump mode
Power good threshold
Based on the nominal output voltage (3.3 V) Vout2
increasing
mA
V
4%
µA
100
Skip current limit
V(PG2)
3%
CO2 = 1 µF, IO2 = 22 mA
Maximum output current
Startup time
V
25
150
mV
5
10
mA
5
mA
200
µs
1
1.17
MHz
50
70
mA
100
140
mA
90%
–15%
CHARGE PUMP STAGE FOR Vout3
Output voltage, Vout3
VO
Normal mode
1.5
Output voltage tolerance
IO
VO
–3%
Output voltage ripple
CO3 = 10 µF, IO3 = 200 mA
Maximum output current
Normal mode
Output current limit
Normal mode (3)
400
Output voltage
Sleep mode
1.5
30
Sleep mode
Vout3 shorted to GND
CO3 = 10 µF, IO3 = 200
Switching frequency
η
Efficiency
VIN = 3.6 V, Iout3 = 200 mA , Vout3 = 1.5 V
Input current limit
LDO mode
Input current limit
Charge pump mode
Power good threshold
Based on the nominal output voltage (1.5 V) Vout3
increasing
(1)
(2)
(3)
V
µA
10
20
mA(2)
1
mA
mA
µs
100
0.83
mA
4%
5
f
V(PG3)
600
100
Skip current limit
Startup time
mA
– 4%
Output current limit in sleep mode
mVPP
200
Output voltage tolerance in sleep mode
Maximum output current
V
3%
1.17
MHz
400
600
mA
200
300
mA
80%
–10%
Overload condition, current is approximately 25 mA if the output is shorted to GND.
Startup time is measured from ENx-pin going high to VO within nominal value.
Overload condition, current is lower if the output is shorted to GND.
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SLVS620 – FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, CI = 10 µF, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LDO FOR Vout4
Output voltage, Vout4
VO
IO
1.8
Output voltage tolerance
Normal mode
–3%
Maximum output current
Normal mode
60
Output current limit
Normal mode
Maximum output current
Sleep mode
3%
mA
110
160
–4%
Current limit in sleep mode
Vout4 shorted to GND
Startup time
CO4 = 1 µF, IO4 = 60
Power good threshold
Based on the nominal output voltage (1.8 V)
Vout4 increasing
4%
5
mA (1)
mA
µA
100
Output voltage tolerance in sleep mode
V(PG4)
V
10
mA
µs
100
–10%
Vbus SWITCH
Vbus comparator turn off threshold
SW_ENx = 1, Vbus voltage falling
Vbus comparator hysteresis
4.3
75
Turn on delay time
Switching from VI to Vbus
Turn off delay time
Switching from Vbus to VI
VIH
SW_EN1, SW_EN2, high level input voltage
VIL
SW_EN1, SW_EN2, low level input voltage
4.45
V
145
mV
5
µs
3
µs
1.2
V
0.3
SW_EN1, SW_EN2 trip point hysteresis
Iikg
110
50
SW_EN1, SW_EN2 input resistance
1
Quiescent current for Vbus comparator
SW_EN1 = 1 and/or SW_EN2 = 1
2.5
V
mV
MR
5
µA
Enable1, Enable2, Enable3, Sleep, SRP
VIH
EN1, EN2, EN3, Sleep, SRP high level input
voltage
VIL
EN1, EN2, EN3, Sleep, SRP low level input
voltage
1.2
0.435
EN1, EN2, EN3, Sleep, SRP trip point
hysteresis
Ilkg
V
50
EN1, EN2, Sleep, SRP input leakage current
0.01
EN3 input resistance to GND
V
mV
0.2
1
µA
MR
SLEEP exit time
8
µs
SLEEP entry time
8
µs
Thermal shutdown temperature
Temperature rising
Thermal shutdown hysteres
°C
155
°C
20
POWER GOOD
VOH
High level output voltage
(open drain output)
VOL
Low level output voltage
(open drain output); Io = 1 mA
Supply voltage at VIN for power good
circuit actively pulled low
(1)
6
5
V
0.3
V
2
Delay time
Low to high transition
Filter time
High to low transition
Startup time is measured from ENx-pin going high to VO within nominal value.
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V
3.1
6
25
ms
µs
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SLVS620 – FEBRUARY 2006
PIN ASSIGNMENT
CHIP SCALE PACKAGE
(BOTTOM VIEW)
E5
D5
C5
B5
A5
E4
D4
C4
B4
A4
E3
D3
C3
B3
A3
E2
D2
C2
B2
A2
E1
D1
C1
B1
A1
TERMINAL FUNCTIONS
TERMINAL
NAME
EN1
NO.
B3
I/O
LOGIC FUNCTION
DESCRIPTION
I
1 = Vbus converter
enabled
0 = Vbus converter
disabled
Enable input for 5-V charge pump. A logic low forces the charge pump into
shutdown mode reducing the supply current to less than 1 µA.
Enable input for 3.3-V and 1.5-V charge pump. Logic low forces both charge
pumps into shutdown mode reducing the supply current to less than 1 µA.
Enable input for 1.8V LDO. Logic low forces the LDO into shutdown mode reducing
the supply current to less than 1µA. To ensure that EN3 is pulled to GND when left
open, there is an internal pull-down resistor to GND.
EN2
B4
I
1 = Vout2 and Vout3
enabled
0 = Vout2 and Vout3
disabled
EN3
C4
I
1 = Vout4 enabled
0 = Vout4 disabled
Vbus
E3
I/O
—
Output for the 5-V charge pump. Connect the output capacitor directly to this pin.
This pin is also the input for the 5-V from the USB port, if the USB port powers the
3.3-V and 1.5-V charge pump as well as the 1.8-V LDO.
Vout2
C5
O
—
Output for the 3.3-V charge pump. Connect Cout2 directly to this pin.
Vout3
A4
O
—
Output for the 1.5-V charge pump. Connect Cout3 directly to this pin.
Vout4
E4
O
—
Output for the 1.8-V LDO. Connect Cout4 directly to this pin.
SLEEP
B2
I
1 = sleep mode
0 = normal mode
This pin is used to set the 3.3-V and 1.5-V charge pump as well as the 1.8-V LDO
into sleep mode. Logic low forces the charge pumps into normal operating mode if
they are enabled.
PGood
D3
O
1 = output voltage within
limits
0 = output voltage too low
Open drain power good output for Vout2,Vout3, and Vout4
SW_EN1
C3
I
1 = Vout3 switchover to
Vbus enabled
0 = Vout3 is battery
powered
Enable input 1 for internal USB switch. If this input is pulled high, the Vout3
converter is powered from Vbus. If SLEEP is pulled high, the converter is always
powered from the battery, independent from the state of SW_EN1.
SW_EN2
C2
I
1 = Vout2 switchover to
Vbus enabled
0 = Vout2 is battery
powered
Enable input 2 for internal USB switch. If this input is pulled high, the Vout2
converter is powered from Vbus. If SLEEP is pulled high, the converter is always
powered from the battery, independent from the state of SW_EN2.
VIN
A1, A2
I
—
Supply voltage input
CF1A+
C1
—
—
Connect to the flying capacitor CF1A
CF1A–
E1
—
—
Connect to the flying capacitor CF1A
CF1B+
B1
—
—
Connect to the flying capacitor CF1B
CF1B–
D1
—
—
Connect to the flying capacitor CF1B
CF2+
D5
—
—
Connect to the flying capacitor CF2
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
LOGIC FUNCTION
E5
—
—
Connect to the flying capacitor CF2
A3
—
—
Connect to the flying capacitor CF3
A5
—
—
Connect to the flying capacitor CF3
NAME
NO.
CF2–
CF3+
CF3Test SRP
PGND
GND
Input:
1 = IO at Vbus = 100 mA
0 = IO at Vbus = 1 mA
DESCRIPTION
Open drain output for connectivity test, input for current limit during startup for
Vbus voltage if the device is not in test mode. If Test SRP is pulled high, the Vbus
current during startup is > 100 mA. If pulled low, it is 1 mA.
D2
I/O
E2, B5
—
—
Power ground
D4
—
—
Analog Ground
FUNCTIONAL BLOCK DIAGRAM
TPS65030
3 V . . .4.2 V (5 V)
10 mF
VIN
Vbus
fixed 5 V/100 mA
4.7 mF
VIN
EN1 (5 V)
Co1
x1.5
x2
mode
EN2 (3.3 V
and 1.5 V)
CF1A+
1 mF
CF1A−
CF1B+
1 mF
CF1B−
EN3 (1.8 V)
Vout2
SLEEP
Co2
fixed 3.3 V/22 mA
(3 V/100 mA in sleep mode)
1 mF
PGood
SW_EN1
LDO
x2
mode
CF2+
100 nF
CF2−
SW_EN2
Vout3
Test SRP
step-down
CP
CF3+
LDO,
x1/2,
mode CF3−
Co3
fixed 1.5 V/200 mA
10 mF
1 mF
PGND
PGND
GND
8
fixed 1.8 V/60 mA
Vout4
LDO
Co4
1 mF
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INTERNAL BLOCK DIAGRAM
SW_EN1
SW_EN2
VIN
EN1
TPS65030
5V
CP
(100mA)
VBUS
+
−
Vbus−
comparator
SLEEP
EN2
EN3
1.5V
3.3V
1.8V
CP+LDO
CP+LDO
LDO
(200mA)
(22mA)
(60mA)
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
η
Efficiency
vs input voltage at Vbus
1
vs input voltage at Vout2
2
vs input voltage at Vout3
3
Power good timing at startup of Vout2 and
Vout3
VI = 3.7 V; IO2 = 20 mA; IO3 = 100 mA
4
Output voltage ripple Vout2, Vout3, Vout4 at no
load
VI = 3.7 V; no load
5
Output voltage ripple Vout2, Vout3, Vout4 at full
VI = 3.7 V; I(bus) = 100 mA; IO2 = 20 mA; IO3 = 100 mA, IO4 = 60mA
load
6
Vbus startup with SRP = 0
No load
7
Vbus startup with SRP = 1
50-mA load
8
Output voltage of Vout2,Vout3, and Vout4
during Vbus switching
VI = 3.1 V; IO2 = 20 mA; IO3 = 100 mA, IO4 = 60 mA
9
Load transient response of Vbus
VI = 3.1V and VI = 3.7 V, I(bus) = 10 mA to 90 mA to 10 mA
10
Load transient response of Vout2
VI = 3.1V, VI = 3.7 V, Vbus = 5 V, IO2 = 2 mA to 20 mA to 2 mA
11
Load transient response of Vout3
VI = 3.1V, VI = 3.7 V, Vbus=5 V, IO3 = 20 mA to 180 mA to 20 mA
12
Load transient response of Vout4
VI = 3.1V, VI = 3.7 V, Vbus=5 V, I(bus) =10 mA to 90 mA to 1 0mA
13
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EFFICIENCY
vs
INPUT VOLTAGE FOR Vbus
EFFICIENCY
vs
INPUT VOLTAGE FOR Vout2
100
100
IO = 100 mA
90
90
80
80
IO = 1 mA
70
Efficiency − %
Efficiency − %
70
IO = 80 mA
60
IO = 1 mA
50
40
VO = 5 V,
o
TA = 25 C
30
60
50
40
20
10
10
3
3.2
VO = 3.3 V,
o
TA = 25 C
30
20
0
IO = 20 mA
IO = 10 mA
3.4 3.6 3.8
4 4.2 4.4 4.6
VI − Input Voltage − V
4.8
0
5
3
3.2
3.4
3.6
4.2
Figure 2.
EFFICIENCY
vs
INPUT VOLTAGE FOR Vout3
100
VO = 1.5 V,
o
TA = 25 C
90
IO = 200 mA
80
70
Efficiency − %
4
IO = 10 mA
60
50
40
30
20
10
0
3
4.4
VI − Input Voltage − V
Figure 1.
3.2 3.4 3.6 3.8
4
4.2 4.4
VI − Input Voltage − V
Figure 3.
10
3.8
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4.6
4.8
5
4.6
4.8
5
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Power Good Timing at Startup of Vout2 and Vout3
TEST CONDITIONS
C4 High
3.0 V
C2 High
3.31 V
VI = 3.7 V
EN1 = low
EN2 = 0 V to 3.7 V
EN3 = low
I(bus) = no load
IO2 = 20 mA (165 W)
C3 High
1.53 V
C1 High
1.85 V
IO3 = 100 mA (15 W)
IO4 = no load
Sleep = low
Test/SRP = high
SW_EN1 = low
SW_EN2 = low
o
TA = 25 C
CH1: PGood (Black Curve)
CH2: Vout2 (Green Curve)
Ch3: Vout3 (Red Curve)
CH4: EN2 (Blue Curve)
t - Time = 500 ms/div
Figure 4.
Output Voltage Ripple for Vout2, Vout3, Vout4 at no Load
TEST CONDITIONS
C2 PK-PK
20.3 mV
VI = 3.7 V
EN1 = high
EN2 = high
EN3 = high
I(bus) = no load
IO2 = no load
IO3 = no load
IO4 = no load
C3 PK-PK
5.8 mV
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
TA = 25oC
C1 Pk-PK
14.6 mV
C4 PK-PK
4.3 mV
CH1: Vbus (Black Curve)
CH2: Vout2 (Green Curve)
Ch3: Vout3 (Red Curve)
CH4: Vout4 (Blue Curve)
t - Time = 4 ms/div
Figure 5.
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Output Voltage Ripple for Vout2, Vout3, Vout4 at Full Load
TEST CONDITIONS
C1 Pk-PK
23.3 mV
C2 PK-PK
8.9 mV
VI = 3.7 V
EN1 = high
EN2 = high
EN3 = high
I(bus) = 100 mA
IO2 = 20 mA
IO3 = 200 mA
IO4 = 60 mA
C3 PK-PK
11.5 mV
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
TA = 25oC
C4 PK-PK
5.0 mV
CH1: Vbus (Black Curve)
CH2: Vout2 (Green Curve)
Ch3: Vout3 (Red Curve)
CH4: Vout4 (Blue Curve)
t - Time = 500 ns/div
Figure 6.
Vbus Startup With SRP = 0
TEST CONDITIONS
C4 High
3.75 V
C4 Low
60 mV
C1 High
5.08 V
C1 Low
30 mV
VI = 3.7 V
EN1 = 0 V to 3.7 V
EN2 = low
EN3 = low
IO1 = no load
IO2 = no load
IO3 = no load
IO4 = no load
Sleep = low
Test SRP = low
SW_EN1 = low
SW_EN2 = low
TA = 25oC
CH1: Vout1 (Black Curve)
CH4: EN1 (Blue Curve)
t - Time = 2 ms/div
Figure 7.
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Vbus Startup With SRP = 1
TEST CONDITIONS
C4 High
3.76 V
C4 Low
50 mV
C1 High
5.05 V
C1 Low
10 mV
VI = 3.7 V
EN1 = 0 V to 3.7 V
EN2 = low
EN3 = low
IO1 = 50 mA
IO2 = no load
IO3 = no load
IO4 = no load
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
TA = 25oC
CH1: Vout1 (Black Curve)
CH4: EN1 (Blue Curve)
t - Time = 100 ms/div
Figure 8.
Output Voltage Ripple for Vout2, Vout3, Vout4 During Vbus Switching
TEST CONDITIONS
C1 High
4.972 V
VI = 3.1 V
EN1 = low
EN2 = high
EN3 = high
Vbus = 4 V to 5 V to 4 V
IO2 = 20 mA (165 W)
IO3 = 200 mA (7.5 W)
IO4 = 60 mA (30 W)
C2 High
3.2488 V
C3 High
1.4888 V
C4 High
1.8248 V
Sleep = low
Test SRP = high
SW_EN1 = high
SW_EN2 = high
o
TA = 25 C
CH1: Vbus (Black Curve)
CH2: Vout2 (Green Curve)
CH3: Vout3 (Red Curve)
CH4: Vout4 (Blue Curve)
t - Time = 10 ms/div
Figure 9.
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Output Voltage of Vout2, Vout3, Vout4 During VI to Vbus Switching
TEST CONDITIONS
C1 High
4.474 V
VI = 3.1 V
EN1 = low
EN2 = high
EN3 = high
V(bus) = 4 V to 5 V
IO2 = 20 mA (165 W)
C2 High
3.2486 V
C3 High
1.4872 V
C4 High
1.8278 V
Unstable
Histogram
t - Time = 40 ms/div
IO3 = 200 mA (7.5 W)
Io4 = 60 mA (30 W)
Sleep = low
Test SRP = high
SW_EN1 = high
SW_EN2 = high
TA = 25oC
CH1: V(bus) (Black Curve)
CH2: Vout2 (Green Curve)
CH3: Vout3 (Red Curve)
CH4: Vout4 (Blue Curve)
Figure 10.
Output Voltage of Vout2, Vout3, Vout4 During Vbus to VI Switching
TEST CONDITIONS
C1 High
4.378 V
Unstable
Histogram
C2 High
3.2530 V
C3 High
1.4872 V
C4 High
1.8258 V
Unstable
Histogram
t - Time = 100 ms/div
Figure 11.
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VI = 3.1 V
EN1 = low
EN2 = high
EN3 = high
V(bus) = 5 V to 4 V
IO2 = 20 mA (165 W)
IO3 = 200 mA (7.5 W)
Io4 = 60 mA (30 W)
Sleep = low
Test SRP = high
SW_EN1 = high
SW_EN2 = high
TA = 25oC
CH1: V(bus) (Black Curve)
CH2: Vout2 (Green Curve)
CH3: Vout3 (Red Curve)
CH4: Vout4 (Blue Curve)
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Load Transient Response for Vbus
TEST CONDITIONS
C2 Pk-PK
213 mV
C4 Max
90 mA
C4 Min
10 mA
VI = 3.1 V
EN1 = high
EN2 = low
EN3 = low
I(bus) = 10 mA to 90 mA
IO2 = no load
IO3 = no load
IO4 = no load
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
TA = 25oC
CH2: Vout1 (Green Curve)
CH4: IO1 (Blue Curve)
t - Time = 200 ms/div
Figure 12.
Load Transient Response for Vout2
TEST CONDITIONS
C2 Pk-PK
60.9 mV
C4 Max
19.6 mA
C4 Min
2.1 mA
VI = 3.1 V
EN1 = low
EN2 = high
EN3 = low
I(bus) = no load
IO2 = 2 mA to 20 mA
IO3 = no load
IO4 = no load
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
TA = 25oC
CH2: Vout2 (Green Curve)
CH4: IO2 (Blue Curve)
t - Time = 200 ms/div
Figure 13.
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Load Transient Response for Vout3
TEST CONDITIONS
C2 Pk-PK
57.2 mV
C4 Max
178 mA
C4 Min
20 mA
VI = 3.1 V
EN1 = low
EN2 = high
EN3 = low
Vbus = no load
Vout2 = no load
Vout3 = 20 mA to 180 mA
Vout4 = no load
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
o
TA = 25 C
CH2: Vout3 (Green Curve)
CH4: IO3 (Blue Curve)
t - Time = 200 ms/div
Figure 14.
Load Transient Response for Vout4
TEST CONDITIONS
C2 Pk-PK
129 mV
C4 Max
53.7 mA
C4 Min
6.1 mA
VI = 3.1 V
EN1 = low
EN2 = low
EN3 = high
I(bus) = no load
IO2 = no load
IO3 = no load
Io4 = 6 mA to 54 mA
Sleep = low
Test SRP = high
SW_EN1 = low
SW_EN2 = low
TA = 25oC
CH2: Vout4 (Green Curve)
CH4: IO4 (Blue Curve)
t - Time = 200 ms/div
Figure 15.
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DETAILED DESCRIPTION
Operation
The TPS65030 uses fractional conversion charge pumps to generate the supply voltage for an integrated USB
OTG chip (TUSB6010). Depending on the input voltage, output voltage, and output current, the charge pumps
operate in different conversion modes. By switching automatically between these different modes the circuit
optimizes the power conversion efficiency as well as extends operating.
Operating Modes
The TPS65030 contains three charge pumps and one LDO. The charge pumps for Vout2 and Vout3 as well as
the LDO, used to generate Vout4, can either operate in normal mode or in sleep mode. See the SLEEP
paragraph for details.
The charge pumps operate in the LinSkip mode. This mode allows to switch seamlessly from the power saving
pulse skip mode at light loads, to the low-noise, constant frequency linear-regulation mode, once the output
current exceeds the device-specific output current threshold. This output current at which the device switches
between these two operating modes is called skip current limit. In order to provide a good efficiency over a wide
load range, the skip current limit is set to approximately 25% of the nominal output current for each converter. If
the output current drops below the skip current threshold, the device begins to skip switching cycles which
reduces its switching frequency and associated switching losses.
Enable (EN1, EN2, EN3)
There are 3 different enable signals available. EN1 activates the 5-V converter associated with Vbus if it is pulled
high. EN2 is associated with the 3.3-V converter (Vout2) and the 1.5-V converter (Vout3). If EN2 is pulled high,
the 3.3-V ramps up first, followed by the 1.5-V converter, see Figure 16. EN3 enables the 1.8-V LDO (Vout4) if
pulled high. For EN3, there is an internal pull-down resistor to GND, disabling the Vout4-LDO if the EN3 pin is
left open.
EN3
EN2
3.3V
90%Vout,nominal
~60us
~200us
1.5V
90%Vout,nominal
~100us
1.8V
90%Vout,nominal
PGOOD
3.1ms min
~100us
3.1ms min
Figure 16. Timing Diagram
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DETAILED DESCRIPTION (continued)
Soft Start
The TPS65030 has an internal soft start circuit that limits the inrush current during start-up. This prevents
possible voltage drops of the input voltage if a high impedance power source is connected to the input of the
TPS65030. The input current for each converter is limited to about twice the nominal input current in normal
operating.
Switch_Enable (SW_EN1, SW_EN2)
The enable pins SW_EN1 and SW_EN2 are used to activate an internal switch that connects the input for the
3.3-V charge pump and the input of the 1.5-V charge pump with either the Li-ion battery or the USB bus voltage
of 5 V. SW_EN1 controls the bus switch for Vout3 (1.5 V), while SW_EN2 controls the bus switch for Vout2 (3.3
V). Vout1 and Vout4 are always battery powered. Both inputs are active high. The turnover from VI to Vbus is
handled in such a way that the SW_ENx signals are used as an enable signal to the bus switch. Switchover,
however, occurs based on the status of the Vbus comparator. The Vbus comparator senses the voltage at Vbus.
If the voltage is above the threshold, the power source for the converters, enabled by SW_ENx is switched from
the battery to the USB bus voltage. If the voltage at Vbus drops below the threshold, the power source is
switched back to the battery again. The internal Vbus comparator is disabled if both SW_EN1 and SW_EN2 are
low, to reduce the quiescent current of the device.
Sleep
The TPS65030 offers a power save mode (sleep mode), that reduces the maximum output current of the
converters for Vout2, Vout3 and Vout4. The Maximum output current for each converter is reduced to 100 µA. In
sleep mode, the quiescent supply current for each converter is reduced to 8 µA maximum. Sleep mode is
entered when the sleep pin is pulled high. In sleep mode, all converters are switched to battery power,
independent from the state of SW_EN1 and SW_EN2. In sleep mode, the charge pumps stop operation, and a
separate 100-µA LDO in each converter supplies the output voltage.
Power Good
The power good signal is provided by an open drain output. The status of this pin depends on the status of the
power good comparators for Vout2, Vout3 and Vout4. Only the converters that are enabled determine the status
of the power good signal. If the output voltage of all converter that are enabled, is within its limits, the power
good signal goes high. The open drain output is pulled high using an external resistor to 5.5-V maximum. If all
converters are disabled, power good is held low. There is a power good delay of 3.1ms minimum after the
voltage of all power rails that are enabled rose above their power good threshold.
Undervoltage Lockout
The undervoltage lockout circuit shuts down the device when the voltage on VIN drops below a typical threshold
of 2.9 V. This prevents the device and application from damage. The UVLO circuit allows the device to start up
again after the voltage on the VIN pin increased by about 80 mV.
Short Circuit and Overtemperature Protection
The current at the different outputs are limited. When the junction temperature exceeds 155°C, the device shuts
down to protect the device from damage. After the temperature decreased to about 135°C, the device starts up if
it is still enabled. In order to reduce the quiescent current, the overtemperature protection is disabled in
sleep-mode.
TEST Input SRP Enable
The TEST input SRP enable pin has two functions. It is an output when the device is in test mode or an input in
normal mode.
In order to test the electrical connections between the power supply chip (TPS65030) and the USB-OTG
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DETAILED DESCRIPTION (continued)
transceiver (TUSB6010), a test mode is available on TPS65030. The TEST pin is used as an output to
TUSB6010. This test mode is entered when EN_SW1 and EN_SW2 and SLEEP are high at the same time. In
this case the actual function of SLEEP is disabled and the output pin TEST is changed from high-impedance
state to low in case that EN1=1. For all other conditions of EN_SW1, EN_SW2, SLEEP, and EN1 it stays in high
impedance state, see Table 1.
The test mode should be entered with the following sequence:
• set SLEEP = 0
• set EN1 = 0
• make sure Vbus is not supplied from external source (Vbus < 4.3 V)
• set SW_EN1 = SW_EN2 = 1
• set SLEEP = 1 (this enters the test mode)
• toggle EN1 to switch between low and high impedance on TEST output pin
Table 1. Interconnection Test Mode
EN_SW1
EN_SW2
SLEEP
EN1
TEST
0
0
0
0
High impedance
0
0
0
1
High impedance
0
0
1
0
High impedance
0
0
1
1
High impedance
0
1
0
0
High impedance
0
1
0
1
High impedance
0
1
1
0
High impedance
0
1
1
1
High impedance
1
0
0
0
High impedance
1
0
0
1
High impedance
1
0
1
0
High impedance
1
0
1
1
High impedance
1
1
0
0
High impedance
1
1
0
1
High impedance
1
1
1
0
High impedance
1
1
1
1
0
The principle is also shown in Figure 17.
SLEEP_INT
SLEEP
EN_SW1
EN_SW2
TM2
TEST
EN1
Figure 17.
When the device is in normal mode (not in test mode), the pin is used as an input to enable or disable the SRP
feature of the Vbus charge pump. If the TEST SRP pin is held low, the SRP feature is enabled and the charge
pump starts up with a current limit of 1 mA until the voltage at Vbus reaches 2.5 V. If the voltage exceeds 2.5 V,
the current limit is increased to a higher value in order to provide 100 mA of output current. If SRP is pulled high,
the charge pump starts with a higher current limit even for Vbus < 2.5 V in order to provide enough output
current to start into a 100 mA load.
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Theory or Operation / Design Procedure
Charge Pump Operation (Based on Vout3 Step-Down Converter)
The description of how the charge pumps operate is based on the design of the step-down charge pump used for
Vout3. This converter either operates in a LDO mode for input voltages (battery voltage) lower than 3.5 V. If the
input voltage exceeds 3.5 V, the converter operates as a step-down charge pump. As the efficiency of a charge
pump mainly depends on the input, output voltage ratio and its operating mode (LDO or x1/2), the efficiency
graph shows a typical sawtooth waveform. This is caused by the fact that the charge pump can only increase
efficiency if it switches to a different operating mode but not by adjusting its duty cycle like in inductive
converters, where the efficiency curve is smooth
LDO Conversion Mode
In the LDO mode the flying capacitor is not used for transferring energy. The switches 3 and 4 are closed and
connect the input directly with the output. This mode is automatically selected if the input voltage is too low to
provide enough output voltage in x1/2 charge pump mode. In LDO mode the regulation is done by regulating the
current through switch 4. For an output current of less than 20 mA, the current through switch is turned on and
off like in SKIP mode regulation.
X1/2 Conversion Mode
This conversion mode is internally selected if the input to output voltage ratio is greater than 2. In the first
switching cycle, the flying capacitor is charged in series with the output capacitor. In the second cycle the flying
capacitor is connected in parallel with the output capacitor which discharges the flying capacitor and charges the
output. Regulation is done similar to LDO mode by regulating the current through switch 4. For an output current
less than the SKIP current threshold, switch 4 does not turn on each switching cycle unless energy is needed at
the output. The device now operates in skip mode with a lower switching frequency, depending on the load
current.
VO
VO
1
3
1
3
Cfly
Cfly
VI
VI
4
+
4
2
+
2
X2 Conversion Mode
This conversion mode applies to the converter used to generate Vout2. It is used to generate an output voltage
that is higher than the input voltage. In the first switching cycle, the flying capacitor is charged in parallel to the
input voltage. In the second switching cycle, the flying capacitor is connected in series with the input voltage,
charging the output capacitor to twice the input voltage. Regulation of the output voltage is done similar to the
other conversion modes.
Sleep-Mode LDO
In sleep mode, a separate LDO in the charge pump block, supplied from the battery, is used to provide the
output voltage.
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Theory or Operation / Design Procedure (continued)
Capacitor Selection
Ceramic capacitors such as X5R or X7R are recommended to be used with TPS65030. Low ESR capacitors on
VOUTx reduce the ripple voltage on the output of the supplies. Table 2 lists capacitor types that have been
tested with the TPS65030. For the flying capacitors, the value is not critical. For values lower than those listed in
the recommended table, the performance of the converter decreases with regard to maximum output current at
minimum input voltage. It also causes the converter to switch to its lower efficient mode at a higher input voltage.
The value of the output capacitors is critical for stability. A high dc-bias voltage at ceramic capacitors causes a
lower capacitance than expected. This effect is critical for Vbus with an output voltage of 5 V. The Vbus
converter is designed to operate with a minimum capacitance of 3 µF. In order to keep the minimum capacitance
at Vbus above 3 µF, a voltage rating for Cout1 of more than 6.3 V may be required, depending on the
specification given by its manufacturer.
Table 2. Capacitors
PART
VALUE
VOLTAGE
MANUFACTURER
SIZE
C1005X5R1A104K
100 nF
10 V
TDK
0402
C1608X5R1A105M
1 µF
10 V
TDK
0603
C2012X5R1A475M
4.7 µF
10 V
TDK
0805
C2012X5R0J106M
10 µF
6.3 V
TDK
0805
NOTES
For Vbus
The voltage rating on the flying capacitors is given in Table 3.
Table 3. Voltage Ratings
REFERENCE
VALUE
VOLTAGE ACROSS
FLYING CAPACITOR
RECOMMENDED
VOLTAGE RATING
CF1A, CF1B
1 µF
VIN
6.3 V
CF2
100 nF
Vout2
4V
CF3
1 µF
Vout3
4V
Due to aging and dc bias effect, the minimum value of real capacitors when these are minimum size, may be
lower than the initial design goals for TPS65030. Therefore TPS65030 has been verified by simulations to be
fully functional and stable with the worst case values for the capacitors given in the table below. Due to the low
capacitance, the output ripple voltage and transient voltage have a different value compared to the capacitors
listed in RECOMMENDED OPERATING CONDITIONS. These values are additionally given in the electrical
characteristics.
Minimum capacitor value for operation
MIN
NOM
MAX
UNIT
CI
Input capacitance
8
µF
CO1
Output capacitance at Vbus; for VI≤ 4.2 V
2
µF
CO2
Output capacitance at Vout2
0.58
µF
CO3
Output capacitance at Vout3
8
µF
CO4
Output capacitance at Vout4
0.8
µF
0.52
µF
Capacitance for flying capacitor CF3
0.7
µF
Capacitance for flying capacitor CF2
0.077
µF
Capacitance for flying capacitor, CF1A, CF1B, VI min > 3.05 V to support an output
current of 100 mA
Power Dissipation
In normal operation when the battery voltage is at its nominal value of 3.8 V, the TPS65030 has very low power
dissipation as it is optimized for operation with one Li-ion cell. If all outputs are fully loaded, the internal power
dissipation is about 300 mW at VI = 3.8 V. The measurements were taken with decreasing battery voltage similar
to a real battery powered system.
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0.8
4 Converters Running
PD − Power Dissipation − W
0.7
0.6
0.5
0.4
0.3
0.2
0.1
3 Converters Running
(Vout4 Disabled)
0
3
3.2
3.4
3.6
3.8
Battery Voltage − V
4
4.2
Figure 18. Power Dissipation vs Battery Voltage
Typically, the TUSB6010 requires less than the full supply current specified for the TPS65030. Figure 19 shows
the power dissipation with the typical current required by TUSB6010. Vbus is loaded with 100 mA, Vout2 is
loaded with 20 mA and Vout3 is loaded with 100 mA.
0.40
P D − Power Dissipation − W
0.35
3 Converters Running
(Vout4 Disabled)
0.30
0.25
0.20
0.15
0.10
0.05
0
3
3.2
3.4
3.6
3.8
4
4.2
Battery Voltage − V
Figure 19. Power Dissipation vs Battery Voltage
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APPLICATION INFORMATION
Typical Application
1.8 V
ON_OFF
MENELAUS1
RESPWRON
OMAP24xx
Interrupt
Wakeup1
(GPIO)
3.3V_1.5V_EN
(GPIO)
PWR_GOOD
(3.3 V and 1.5 V)
optional
VBAT
VBUS
TPS65030 (scapula)
10 mF
VIN
VIN
Vbus
CF1A+
EN1 (5 V)
EN2 (3.3 V ;1.5 V) CF1A−
EN3 (1.8 V)
CF1B+
SLEEP
CF1B−
SW_EN1
SW_EN2
1.8 V
4.7 mF
1 mF
1 mF
Vout2
1 mF
CF2−
Test SRP
3.3 V
VBUS
VANALOG
1.5 V
RESPWRON
CF2+
Vout4
VIO
PWR_GOOD
(3.3 V and 1.5 V)
Wakeup2
Wakeup1
100 nF
VCORE
USB2 OTG
(Fibula)
GPIO
EN1 (5 V)
Interrupt
SLEEP
SW_EN1
SW_EN2
TEST
GPIO
Vout3
10 mF
CF3+
PGND
PGND
GND
CF3−
1 mF
PGood
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APPLICATION INFORMATION (continued)
Layout and Board Space
All capacitors should be soldered as close as possible to the IC. A PCB layout proposal for a four-layer board is
shown in Figure 20 to Figure 23. Care has been taken to connect all capacitors as close as possible to the circuit
to achieve optimized output voltage ripple performance. All critical connections like power input / output pins and
the pins for the flying capacitors are located on the outside of the package. Signal connections like enable
signals are located in the inside and can be routed on the bottom layer or on a signal layer. Power connections
should be routed on the layer, the device is placed. A GND plane should be used for optimal performance of the
device.
Figure 20. EVM Top Layer
24
Figure 21. EVM Layer 2
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APPLICATION INFORMATION (continued)
Figure 22. EVM Layer 3
Figure 23. EVM Bottom Layer
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 3 V to 5 V and the output voltage range of
1.5 V to 5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM
output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 50°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
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PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
CHIP SCALE PACKAGE MARKINGS
(TOP VIEW)
E5
D5
C5
B5
A5
E4
D4
C4
B4
A4
PJMI
YMLLLLS
E
E3
D3
C3
B3
A3
E2
D2
C2
B2
A2
A2
E1
D1
C1
B1
A1
A1
D
Code:
•
PJMI - identifies the chip as
TPS65030
•
Y - year
•
M - month
•
L - lot trace code
•
S - site code
PACKAGE DIMENSIONS
The dimensions for the YZK package are shown in Table 4. See the package drawing at the end of this data
sheet.
Table 4. YZK Package Dimensions
26
Packaged Devices
D Maximum
E Maximum
TPS65030YZK
2,708 mm
2,51 mm
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS65030YZKR
ACTIVE
DSBGA
YZK
25
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS65030YZKT
ACTIVE
DSBGA
YZK
25
250
SNAGCU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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