TI TPS70402PWP

TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
D Dual Output Voltages for Split-Supply
D Ultralow 185 µA (typ) Quiescent Current
Applications
D 2 µA Input Current During Standby
Independent Enable Functions (See Part
D Low Noise: 78 µVRMS Without Bypass
Number TPS703xx for Sequenced Outputs)
Capacitor
Output Current Range of 1 A on
D Quick Output Capacitor Discharge Feature
Regulator 1 and 2 A on Regulator 2
D One Manual Reset Input
Fast Transient Response
D 2% Accuracy Over Load and Temperature
Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V,
D Undervoltage Lockout (UVLO) Feature
3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
D 24-Pin PowerPAD TSSOP Package
Outputs
D Thermal Shutdown Protection
Open Drain Power-On Reset With 120-ms
Delay
Open Drain Power Good for Regulator 1
1
24
GND/HEATSINK
GND/HEATSINK
and Regulator 2
2
23
V
V
D
D
D
D
D
D
IN1
description
The TPS704xx family of devices consists of
dual-output low-dropout voltage regulators with
integrated SVS (RESET, POR, or power on reset)
and power good (PG) functions. These devices
are capable of supplying 1 A and 2 A by regulator
1 and regulator 2 respectively. Quiescent current
is typically 185 µA at full load. Differentiated
features, such as accuracy, fast transient
response, SVS supervisory circuit (power on
reset), manual reset input, and independent
enable functions provide a complete system
solution.
OUT1
3
4
5
6
7
8
9
10
11
12
VIN1
NC
MR
EN1
EN2
RESET
GND
VIN2
VIN2
GND/HEATSINK
22
21
20
19
18
17
16
15
14
13
NC – No internal connection
TPS70451 PWP
5V
0.22 µF
22 µF
VSENSE1
250 kΩ
MR
250 kΩ
PG1
PG1
VIN2
MR
>2 V
250 kΩ
<0.7 V
0.22 µF
>2 V
EN1
<0.7 V
EN2
>2 V
RESET
RESET
EN1
PG2
EN2
VSENSE2
I/O
3.3 V
VOUT1
VIN1
VOUT1
VSENSE1/FB1
NC
PG1
PG2
NC
VSENSE2/FB2
VOUT2
VOUT2
GND/HEATSINK
PG2
<0.7 V
VOUT2
1.8 V
Core
47 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2000, – 2003 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
description (continued)
The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices
have extremely low noise output performance without using any added filter bypass capacitors and are
designed to have a fast transient response and be stable with 47 µF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.
Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the
designer to configure the source power.
Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160
mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element
is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
250 µA over the full range of output current and full range of temperature). This LDO family also features a sleep
mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When
a high signal is applied to both EN1 and EN2, both regulators are in sleep mode, thereby reducing the input
current to 2 µA at TJ = 25°C.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET,
POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions
at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator
2.
The TPS704xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output
and requires a pullup resistor for normal operation. When pulled up, RESET goes into a high impedance state
(i.e. logic high) after 120 ms delay when both of the following conditions are met. First, VIN1 must be above the
undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor
VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected
to MR. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be
left floating.
Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an
undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.
AVAILABLE OPTIONS
TJ
– 40°C to 125°C
REGULATOR 1
VO (V)
REGULATOR 2
VO (V)
TSSOP
(PWP)
3.3 V
1.2 V
TPS70445PWP
3.3 V
1.5 V
TPS70448PWP
3.3 V
1.8 V
TPS70451PWP
3.3 V
2.5 V
TPS70458PWP
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70402PWP
NOTE: The TPS70402 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70402PWPR).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
detailed block diagram – fixed voltage version
VIN1 (2 Pins)
VOUT1 (2 Pins)
Current
Sense
UVLO1
Shutdown
10 kΩ
ENA_1
2.5 V
–
GND
Reference
Thermal
Shutdown
VSENSE1
(see Note A)
ENA_1
+
Vref
FB1
Vref
VPGD1
VPGD2
UVLO1
PG1
VSENSE1
Rising Edge
Deglitch
VPGD_1
VIN1
MR
RESET
EN1
Falling Edge
Delay
UVLO1
ENA_1
UVLO2
PG2
VSENSE2
Shutdown
Rising Edge
Deglitch
VPGD_2
ENA_2
Vref
UVLO2
FB2
EN2
–
2.5 V
UVLO2
+
Current
Sense
ENA_2
VSENSE2
(see Note A)
ENA_2
10 kΩ
VOUT2 (2 Pins)
VIN2 (2 Pins)
NOTE A: For most applications, VSENSE1 and VSENSE2 should be connected to VOUT1 and VOUT2 respectively as close as possible to the device.
For other implementations, refer to SENSE terminal connection discussion in the application information section.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
detailed block diagram – adjustable voltage version
VIN1 (2 Pins)
VOUT1 (2 Pins)
Current
Sense
UVLO1
Shutdown
ENA_1
FB1
(see Note A)
2.5 V
–
GND
Reference
Thermal
Shutdown
ENA_1
+
Vref
Vref
VPGD1
VPGD2
UVOL1
PG1
VSENSE1
Rising Edge
Deglitch
VPGD_1
VIN1
MR
RESET
ENA_1
EN1
Falling Edge
Delay
UVLO1
UVOL2
PG2
VSENSE2
Shutdown
Rising Edge
Deglitch
VPGD_2
ENA_2
EN2
Vref
UVLO2
–
2.5 V
UVLO2
+
Current
Sense
ENA_2
ENA_2
FB2
(see Note A)
VOUT2 (2 Pins)
VIN2 (2 Pins)
NOTE A: For most applications, FB1 and FB2 should be connected to resistor dividers as close as possible to the device. For other
implementations, refer to FB terminals connection discussion in the application information section.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
RESET timing diagram
VIN1
VUVLO
VUVLO
VRES
t
VRES
MR Input
t
RESET Output
Output
Undefined
Î
Î
Î
120 ms
Delay
120 ms
Delay
ÎÎ
ÎÎ
ÎÎ
Output
Undefined
t
NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
PG1 timing diagram
VIN1
VUVLO
VUVLO
VPG
VPG1
t
VOUT1
VIT+
(see Note B)
Threshold
Voltage
VIT –
(see Note B)
t
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
PG1 Output
Output
Undefined
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
PG1
Output
Undefined
t
NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for
semiconductor symbology.
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
PG2 timing diagram (assuming VIN1 already powered up)
VIN2
t
VOUT2
VIT+
(see Note A)
Threshold
Voltage
VIT –
(see Note A)
t
PG2
Output
t
NOTES: A. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN1
6
I
Active low enable for VOUT1
EN2
7
I
Active low enable for VOUT2
GND
9
GND/HEATSINK
Ground
1, 12, 13, 24
Ground/heatsink
MR
5
NC
4, 17, 20
PG1
19
O
Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage
PG2
18
O
Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage
RESET
I
Manual reset input, active low, pulled up internally
No connection
8
O
Open drain output, SVS (power on reset) signal, active low
2, 3
I
Input voltage of regulator 1
10, 11
I
Input voltage of regulator 2
22, 23
O
Output voltage of regulator 1
14, 15
O
Output voltage of regulator 2
VSENSE1/FB1
21
I
Regulator 1 output voltage sense/ regulator 1 feedback for adjustable
VSENSE2/FB2
16
I
Regulator 2 output voltage sense/ regulator 2 feedback for adjustable
VIN1
VIN2
VOUT1
VOUT2
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
detailed description
The TPS704xx low dropout regulator family provides dual regulated output voltages with independent enable
functions. These devices provide fast transient response and high accuracy with small output capacitors, while
drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good
(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features
provide a complete power solution.
The TPS704xx, unlike many other LDOs, features very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). The TPS704xx uses a PMOS transistor
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
pin functions
enable (EN1 and EN2)
The EN terminals are inputs which enable or shut down each respective regulator. If EN is at a logic high, the
respective regulator will be in shutdown mode. When EN goes to voltage low, then the respective regulator is
enabled.
power good (PG1 and PG2)
The PG terminals are open drain, active high outputs which indicate the status of each respective regulator.
When the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. When the VOUT2
reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance
state when its respective output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage.
The open drain outputs of the PG terminals require a pullup resistor.
manual reset pin (MR)
MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR
(RESET) occurs. The terminal has a 6-µA pullup current to VIN1; however, it is recommended that the pin be
pulled high to VIN1 when it is not used.
sense (VSENSE1 , VSENSE2 )
The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection
should be as short as possible. Internally, the sense terminal connects to high-impedance wide-bandwidth
amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is
essential to route the sense connection in such a way as to minimize/avoid noise pickup. Adding RC networks
between sense terminals and VOUT terminals to filter noise is not recommended because it can cause the
regulators to oscillate.
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between FB terminals and VOUTS to filter
noise is not recommended because it can cause the regulators to oscillate.
RESET indicator
RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up,
RESET goes into a high impedance state (i.e. logic high) after a 120 ms delay when both of the following
conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin
must be in a high impedance state. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor
VOUT2, the PG2 output pin can be connected to MR. If RESET is not used, it can be left floating.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
detailed description (continued)
VIN1 and VIN2
VIN1 and VIN2 are inputs to each regulator. Internal bias voltages are powered by VIN1.
VOUT1 and VOUT2
VOUT1 and VOUT2 are output terminals of each regulator.
absolute maximum ratings over operating junction temperature (unless otherwise noted)†
Input voltage range‡: VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Voltage range at EN1, EN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range (VOUT1, VSENSE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (VOUT2, VSENSE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Maximum RESET, PG1, PG2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum MR voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are tied to network ground.
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
DISSIPATION RATING TABLE
PACKAGE
AIR FLOW
(CFM)
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
0
3.32 W
33.2 mW/°C
1.83 W
1.33 W
PWP§
250
4.58 W
2.52 W
1.83 W
45.87 mW/°C
§ This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 2 oz. copper traces on
4-in × 4-in ground layer. Simultaneous and continuous operation of both regulator outputs at full load may exceed the power
dissipation rating of the PWP package. For more information, refer to the power dissipation and thermal information section
at the end of this data sheet, and to TI technical brief SLMA002.
recommended operating conditions
MIN
MAX
2.7
6
V
Output current, IO (regulator 1)
0
1
A
Output current, IO (regulator 2)
0
2
A
1.22
5.5
V
Input voltage, VI†
Output voltage range (for adjustable option)
UNIT
Operating virtual junction temperature, TJ
–40
125
°C
† To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C)
VIN1 or VIN2= VOUTX(nom) + 1 V, IO = 1 mA, EN = 0, COUT1 = 22 µF, COUT2= 47 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Reference voltage
VO
Output voltage
(see Notes 1 and 3)
2.7 V < VI < 6 V
TJ = 25°C
FB connected to VO
2.7 V < VI < 6 V,
FB connected to VO
1.2 V output
out ut
(VOUT2)
2.7 V < VI < 6 V,
TJ = 25°C
1.5 V output
out ut
(VOUT2)
2.7 V < VI < 6 V,
1.8 V output
out ut
(VOUT2)
2.8 V < VI < 6 V,
2.5 V output
out ut
(VOUT2)
3.5 V < VI < 6 V,
3.3 V output
out ut
(VOUT2)
4.3 V < VI < 6 V,
2.7 V < VI < 6 V
1.8
TJ = 25°C
1.836
2.5
2.45
TJ = 25°C
2.55
3.3
3.234
TJ = 25°C
3.366
185
250
TJ = 25°C
TJ = 25°C, See Note 1
See Note 1
0.1%
1
Regulator 1
BW = 300 Hz to 50 kHz
kHz,
TJ = 25°C
Thermal shutdown junction temperature
1.75
2.2
3.8
4.5
II(standby)
(
) Standby current
EN1 = VI,
EN2 = VI,
EN1 = VI,
EN2 = VI
PSRR
Regulator 1
f = 1 kHz
Regulator 2
f = 1 kHz,
TJ = 25°C
1
2
10
TJ = 25°C, See Note 1
TJ = 25°C, See Note 1
A
°C
150
Regulator 1 and
Regulator 2
V
µVrms
77
VO = 0 V
Regulator 2
µA
mV
79
Regulator 2
V
0.01%
Regulator 1
Power su
supply
ly ri
ripple
le rejection
(TPS70451)
V
1.53
See Note 3
Load regulation for VOUT1 and VOUT2
Output current limit
1.224
1.764
See Note 3,
UNIT
1.244
1.5
TJ = 25°C
4.3 V < VI < 6 V
MAX
1.2
1.47
3.5 V < VI < 6 V
VO + 1 V < VI ≤ 6 V,
VO + 1 V < VI ≤ 6 V,
Output
Out
ut noise voltage
(TPS70451)
1.196
1.176
2.8 V < VI < 6 V
Out ut voltage line regulation (∆VO/VO) for
Output
regulator 1 and regulator 2 (see Note 2)
Vn
TYP
1.22
TJ = 25°C
2.7 V < VI < 6 V
Quiescent current (GND current) for regulator 1 and
regulator 2, EN1 = EN2 = 0 V, (see Note 1)
MIN
µA
65
dB
60
RESET terminal
I(RESET) = 300 µA,
V(RESET) ≤ 0.8 V
RESET pulse duration
Minimum input voltage for valid RESET
t(RESET)
Output low voltage
VI = 3.5 V,
V(RESET) = 6 V
Leakage current
I(RESET) = 1 mA
80
1.0
1.3
V
120
160
ms
0.15
0.4
V
1
µA
NOTES: 1. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output
current 1 mA.
2. If VO < 1.8 V then VImax = 6 V, VImin = 2.7 V:
Line regulation (mV) + ǒ%ńVǓ
V
O
ǒVImax * 2.7 VǓ
100
1000
If VO > 2.5 V then VImax = 6 V, VImin = VO + 1 V:
Line regulation (mV) + ǒ%ńVǓ
V
O
ǒVImax * ǒVO ) 1ǓǓ
100
3. IO = 1 mA to 1 A for regulator 1 and 1 mA to 2 A for regulator 2.
POST OFFICE BOX 655303
1000
• DALLAS, TEXAS 75265
9
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C)
VIN1 or VIN2= VOUTX(nom) + 1 V, IO = 1 mA, EN = 0, COUT1 = 22 µF, COUT2= 47 µF (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN1/VIN2 terminal
UVLO threshold
2.4
UVLO hysteresis
2.65
110
V
mV
PG1/PG2 terminal
Minimum input voltage for valid PGx
I(PGx) = 300 µA,
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
tr(PGx)
Rising edge deglitch
Output low voltage
VI = 2.7 V,
Leakage current
V(PGx) = 6 V
V(PGx) ≤ 0.8 V
92%
I(PGx) = 1 mA
1.0
1.3
95%
98%
V
VO
0.5%
VO
30
µs
0.15
0.4
V
1
µA
EN1/EN2 terminal
High-level ENx input voltage
2
V
Low-level ENx input voltage
Input current (ENx)
–1
0.7
V
1
µA
MR terminal
High-level input voltage
2
V
Low-level input voltage
0.7
Pullup current source
V
µA
6
VOUT1 terminal
Dropout voltage (see Note 4)
IO = 1 A, VIN1 = 3.2 V, TJ = 25°C
160
IO = 1 A, VIN1 = 3.2 V
250
mV
Peak output current
2 ms pulse width
1.2
A
Discharge transistor current
VOUT1 = 1.5 V
7.5
mA
VOUT2 terminal
Peak output current
2 ms pulse width
Discharge transistor current
VOUT2 = 1.5 V
3
A
7.5
mA
FB terminal
Input current – TPS70402
FB = 1.8 V
1
µA
NOTE 4: Input voltage(VIN1 or VIN2) = VO(Typ) – 100 mV. For the 1.5-V, 1.8-V and 2.5-V regulators, the dropout voltage is limited by input voltage
range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test.
10
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VO
Output voltage
PSRR
zo
vs Output current
1, 2
vs Junction temperature
3, 4
Ground current
vs Junction temperature
Power supply rejection ratio
vs Frequency
6–9
Output spectral noise density
vs Frequency
10 – 13
Output impedance
vs Frequency
14 – 17
vs Temperature
18, 19
vs Input voltage
20, 21
Dropout voltage
5
Load transient response
22, 23
Line transient response
VO
24, 25
Output voltage
vs Time (start-up)
26, 27
Equivalent series resistance (ESR)
vs Output current
29 – 32
TPS70451
TPS70451
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.33
1.815
VIN1 = 4.3 V
TJ = 25°C
VOUT1
3.31
3.30
3.29
3.28
3.27
VIN2 = 2.8V
TJ = 25°C
VOUT2
1.81
VO – Output Voltage – V
VO – Output Voltage – V
3.32
1.805
1.8
1.795
1.79
1.785
0
200
400
600
800
IO – Output Current – mA
1000
0
500
1000
1500
2000
IO – Output Current – mA
Figure 1
Figure 2
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11
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TPS70451
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
3.354
VIN1 = 4.3 V
VOUT1
VO – Output Voltage – V
3.334
3.314
IO = 1 mA
3.294
IO = 1 A
3.274
3.254
3.234
–40 –25 –10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – °C
Figure 3
TPS70451
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
TPS70451
GROUND CURRENT
vs
JUNCTION TEMPERATURE
1.834
210
VIN2 = 2.8 V
VOUT2
Regulator 1 and Regulator 2
200
1.814
1.804
1.794
Ground Current – µ A
VO – Output Voltage – V
1.824
IO = 2 A
IO = 1 mA
1.784
IOUT1 = 1 mA
IOUT2 = 1 mA
190
180
170
1.774
160
1.764
–40 –25 –10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – °C
150
–40 –25 –10 5 20 35 50 65 80 95 110 125
TJ – Junction Temperature – °C
Figure 4
12
IOUT1 = 1 A
IOUT2 = 2 A
Figure 5
POST OFFICE BOX 655303
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TPS70451
TPS70451
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
0
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 10 mA
CO = 22 µF
–20
–30
PSRR – Power Supply Rejection Ratio – dB
PSRR – Power Supply Rejection Ratio – dB
–10
–40
–50
–60
–70
–80
–90
10
100
1k
10 k
100 k
–10
–20
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µF
–30
–40
–50
–60
–70
–80
–90
–100
10
1M
100
f – Frequency – Hz
TPS70451
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSRR – Power Supply Rejection Ratio – dB
PSRR – Power Supply Rejection Ratio – dB
1M
0
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 10 mA
CO = 47 µF
–30
–40
–50
–60
–70
–80
–90
–100
10
100 k
TPS70451
0
–20
10 k
Figure 7
Figure 6
–10
1k
f – Frequency – Hz
100
1k
10 k
100 k
1M
–10
–20
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µF
–30
–40
–50
–60
–70
–80
–90
–100
10
100
1k
10 k
100 k
1M
f – Frequency – Hz
f – Frequency – Hz
Figure 9
Figure 8
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13
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
1
0.1
0.01
100
1k
10 k
f – Frequency – Hz
VIN2 = 2.8 V
VOUT2 = 1.8 V
COUT2 = 47 µF
IO = 10 mA
TJ = 25°C
Hz
VIN1 = 4.3 V
VOUT1 = 3.3 V
COUT1 = 22 µF
IO = 10 mA
TJ = 25°C
Output Spectral Noise Density – µV/
Output Spectral Noise Density – µV/ Hz
10
1
0.1
0.01
100
100 k
1k
10 k
f – Frequency – Hz
Figure 10
Figure 11
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
VIN1 = 4.3 V
VOUT1 = 3.3 V
COUT1 = 22 µF
IO = 1 A
TJ = 25°C
Output Spectral Noise Density – µV/ Hz
Output Spectral Noise Density – µV/ Hz
10
1
0.1
0.01
100
1k
10 k
f – Frequency – Hz
100 k
VIN2 = 2.8 V
VOUT2 = 1.8 V
COUT2 = 47 µF
IO = 2 A
TJ = 25°C
1
0.1
0.01
100
Figure 12
14
100 k
1k
10 k
f – Frequency – Hz
Figure 13
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100 k
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µF
Z O – Output Impedance – Ω
Z O – Output Impedance – Ω
VOUT1 = 3.3 V
IO = 10 mA
CO = 22 µF
1
0.1
0.01
10
100
1k
10 k
100 k
1M
1
0.1
0.01
10
10 M
100
f – Frequency – Hz
Figure 15
10 M
1M
10 M
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µF
1
0.1
0.01
1k
1M
OUTPUT IMPEDANCE
vs
FREQUENCY
Z O – Output Impedance – Ω
Z O – Output Impedance – Ω
100 k
Figure 14
VOUT2 = 1.8 V
IO = 10 mA
CO = 47 µF
100
10 k
f – Frequency – Hz
OUTPUT IMPEDANCE
vs
FREQUENCY
10
1k
10 k
100 k
1M
10 M
1
0.1
0.01
10
100
1k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 16
Figure 17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TPS70451
TPS70451
DROPOUT VOLTAGE
vs
TEMPERATURE
DROPOUT VOLTAGE
vs
TEMPERATURE
25
250
VOUT1
VIN1 = 3.2 V
VOUT1
VIN1 = 3.2 V
20
200
Dropout Voltage – mV
Dropout Voltage – mV
IO = 1 A
150
100
IO = 100 mA
15
10
5
50
IO = 1 mA
IO = 10 mA
0
–40 –25 –10
5
20 35 50 65 80
T – Temperature – °C
0
–40 –25 –10
95 110 125
TPS70402
TPS70402
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
300
300
VOUT1
IO = 1 A
VOUT2
IO = 2 A
250
TJ = 125°C
Dropout Voltage – mV
Dropout Voltage – mV
250
200
TJ = 25°C
150
100
TJ= – 40°C
50
TJ = 125°C
200
TJ = 25°C
150
TJ= – 40°C
100
50
3
3.5
4
4.5
5
5.5
0
2.5
VI – Input Voltage – V
3
3.5
4
Figure 21
POST OFFICE BOX 655303
4.5
VI – Input Voltage – V
Figure 20
16
95 110 125
Figure 19
Figure 18
0
2.5
5 20 35 50 65 80
T – Temperature – °C
• DALLAS, TEXAS 75265
5
5.5
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
IO – Output Current – A
VIN1 = 4.3 V
VOUT1 = 3.3 V
CO = 22 µF
1
0.5
0
50
∆ VO – Change in
Output Voltage – mV
∆ VO – Change in
Output Voltage – mV
IO – Output Current – A
LOAD TRANSIENT RESPONSE
0
–50
–100
0
0.2
0.4 0.6 0.8
1
1.2
1.4 1.6
1.8
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µF
2
1
0
50
0
–50
0
2
0.2
0.4 0.6 0.8
Figure 22
1.4 1.6
1.8
2
4.3
VI – Input Voltage – V
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µF
LINE TRANSIENT RESPONSE
∆ VO – Change in
Output Voltage – mV
VI – Input Voltage – V
∆ VO – Change in
Output Voltage – mV
1.2
Figure 23
LINE TRANSIENT RESPONSE
5.3
1
t – Time – ms
t – Time – ms
50
0
–50
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µF
3.8
2.8
100
0
–100
–200
–100
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
t – Time – µs
t – Time – µs
Figure 25
Figure 24
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
TIME (START-UP)
VO – Output Voltage– V
4
3
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µF
VIN1 = 4.3 V
EN2 = High
2
1
0
Enable Voltage – V
Enable Voltage – V
VO – Output Voltage– V
OUTPUT VOLTAGE
vs
TIME (START-UP)
5
0
0
0.2 0.4
0.6
0.8 1 1.2 1.4
t – Time – ms
1.6 1.8
2
2
1
0
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µF
VIN2 = 2.8 V
EN1 = High
5
0
0
0.2 0.4
Figure 26
VI
0.6
0.8 1 1.2 1.4
t – Time – ms
1.6 1.8
2
Figure 27
To Load
IN
OUT
+
CO
EN
GND
RL
ESR
Figure 28. Test Circuit for Typical Regions of Stability
† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
VOUT1 = 3.3 V
CO = 22 µF
ESR – Equivalent Series Resistance – Ω
ESR – Equivalent Series Resistance – Ω
10
REGION OF INSTABILITY
1
0.1
50 mΩ
0.01
VOUT1 = 3.3 V
CO = 220 µF
REGION OF INSTABILITY
1
0.1
15 mΩ
0.01
0
0.1 0.2
0.3
0.4 0.5
0.6 0.7
0.8 0.9
1
0
0.1 0.2
IO – Output Current – A
Figure 29
0.4 0.5
0.6 0.7
0.8 0.9
1
Figure 30
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
ESR – Equivalent Series Resistance – Ω
REGION OF INSTABILITY
ESR – Equivalent Series Resistance – Ω
0.3
IO – Output Current – A
VOUT2 = 1.8 V
CO = 47 µF
1
0.1
50 mΩ
0.01
VOUT2 = 1.8 V
CO = 680 µF
1
0.1
15 mΩ
0.01
0
0.1 0.2
0.3
0.4 0.5
0.6 0.7
0.8 0.9
1
0
0.1 0.2
0.3
0.4 0.5
0.6 0.7
0.8 0.9
1
IO – Output Current – A
IO – Output Current – A
Figure 31
Figure 32
† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
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SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad)
The thermally enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see
Figure 33(c)] to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down
TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.
These packages, however, suffer from several shortcomings: they do not address the very low profile
requirements (< 2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough
to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages
require power-dissipation derating that severely limits the usable range of many high-performance analog
circuits.
The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal
performance comparable to much larger power packages.
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and
limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction
paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent
pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC.
When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the
ultrathin, fine-pitch, surface-mount package can be reliably achieved.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 33. Views of Thermally Enhanced PWP Package
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal
considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface),
which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference
Figure 35(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the
power dissipation range for the component. The power dissipation limit can be further improved by adding
airflow to a PWB/IC assembly (see Figures 34 and 35). The line drawn at 0.3 cm2 in Figures 34 and 35 indicates
performance at the minimum recommended heat-sink size, illustrated in Figure 36.
20
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
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SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad) (continued)
The thermal pad is directly connected to the substrate of the IC, which for the TPS704xx series is a secondary
electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane
or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary
electrical connection for a given terminal which is not always ground. The PWP package provides up to 24
independent leads that can be used as inputs and outputs (Note: leads 1, 12, 13, and 24 are internally connected
to the thermal pad and the IC substrate).
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150
Natural Convection
R θ JA – Thermal Resistance – ° C/W
125
50 ft/min
100 ft/min
100
150 ft/min
200 ft/min
75
50
250 ft/min
300 ft/min
25
0 0.3
1
2
3
4
5
6
7
8
Copper Heat-Sink Area – cm2
Figure 34
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
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SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad) (continued)
3.5
3.5
TA = 55°C
300 ft/min
3
PD – Power Dissipation Limit – W
PD – Power Dissipation Limit – W
TA = 25°C
150 ft/min
2.5
2
Natural Convection
1.5
1
0.5
0
3
300 ft/min
2.5
2
150 ft/min
1.5
Natural Convection
1
0.5
0
0.3
2
4
6
0
8
Copper Heat-Sink Size – cm2
0
0.3
2
4
6
Copper Heat-Sink Size – cm2
(a)
(b)
3.5
TA = 105°C
PD – Power Dissipation Limit – W
3
2.5
2
1.5
150 ft/min
300 ft/min
1
Natural Convection
0.5
0
0
0.3
2
4
6
8
Copper Heat-Sink Size – cm2
(c)
Figure 35. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
22
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad) (continued)
Figure 36 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board
configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and
Figure 35. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA
for this assembly is illustrated in Figure 34 as a function of heat-sink area. A family of curves is included to
illustrate the effect of airflow introduced into the system.
Heat-Sink Area
1 oz Copper
Board thickness
Board size
Board material
Copper trace/heat sink
Exposed pad mounting
62 mils
3.2 in. × 3.2 in.
FR4
1 oz
63/67 tin/lead solder
Figure 36. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package
From Figure 34, RθJA for a PWB assembly can be determined and used to calculate the maximum
power-dissipation limit for the component/PWB assembly, with the equation:
P
D(max)
+
T max * T
J
A
R
qJA(system)
(4)
Where:
TJmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended
operating limit) and TA is the ambient temperature.
PD(max) should then be applied to the internal power dissipated by the TPS704xx regulator. The equation for
calculating total internal power dissipation of the TPS704xx is:
P
D(total)
ǒ
+ V
IN1
*V
Ǔ
OUT1
I
OUT1
)V
I
ǒ
Ǔ
Q
) V
*V
IN2
OUT2
2
IN1
I
OUT2
)V
I
IN2
Q
2
(5)
Since the quiescent current of the TPS704xx is very low, the second term is negligible, further simplifying the
equation to:
P
D(total)
ǒ
+ V
IN1
*V
Ǔ
OUT1
I
OUT1
ǒ
) V
IN2
*V
Ǔ
OUT2
I
OUT2
(6)
For the case where TA = 55°C, airflow = 200 ft /min, copper heat-sink area = 4 cm2, the maximum
power-dissipation limit can be calculated. First, from Figure 34, we find the system RθJA is 50°C/W; therefore,
the maximum power-dissipation limit is:
P
D(max)
+
T max * T
°
J
A + 125 °C * 55 C
+ 1.4 W
°
R
50 CńW
qJA(system)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
(7)
23
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
THERMAL INFORMATION
thermally enhanced TSSOP-24 (PWP – PowerPad) (continued)
If the system implements a TPS70451 regulator, where VIN1 = 4.3 V, IOUT1 = 0.5 A, VIN2 = 2.8 V, and
IOUT2 = 0.75 A, the internal power dissipation is:
P
D(total)
ǒ
+ V
+ (4.3 * 3.3)
IN1
*V
Ǔ
OUT1
I
OUT1
0.5 ) (2.8 * 1.8)
ǒ
) V
IN2
*V
Ǔ
OUT2
I
(8)
OUT2
0.75 + 1.25 W
Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the
calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit
by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by
reducing the input voltage or the load current. In either case, the above calculations should be repeated with
the new system parameters. This parameter is measured with the recommended copper heat sink pattern on
a 4-layer PCB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both
regulator outputs at full load may exceed the power dissipation rating of the PWP package.
mounting information
The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The
thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.
Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The
data included in Figures 34 and 35 is for soldered connections with voiding between 20% and 50%. The thermal
analysis shows no significant difference resulting from the variation in voiding percentage.
Figure 37 shows the solder-mask land pattern for
the PWP package. The minimum recommended
heat-sink area is also illustrated. This is simply a
copper plane under the body extent of the
package, including metal routed under terminals
1, 12, 13, and 24.
Minimum Recommended
Heat-Sink Area
Location of Exposed
Thermal Pad on
PWP Package
Figure 37. PWP Package Land Pattern
24
POST OFFICE BOX 655303
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
APPLICATION INFORMATION
timing diagrams
The following figures provide a timing diagram of how this device functions in different configurations.
application conditions not shown in block diagram:
VIN1 and VIN2 are tied to the same fixed input
voltage greater than the VUVLO. PG2 is tied to MR.
TPS704xxPWP
(Fixed Output Option)
VIN
VIN1
explanation of timing diagrams:
0.22 µF
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 (tied to MR)
are at logic low. Since MR is at logic low, RESET
is also at logic low. When EN1 is taken to logic low,
VOUT1 turns on. Later, when EN2 is taken to logic
low, VOUT2 turns on. When VOUT1 reaches 95% of
its regulated output voltage, PG1 goes to logic
high. When VOUT2 reaches 95% of its regulated
output voltage, PG2 (tied to MR) goes to logic
high. When VIN1 is greater than VUVLO and MR
(tied to PG2) is at logic high, RESET is pulled to
logic high after a 120 ms delay. When EN1 and
EN2 are returned to logic high, both devices
power down and both PG1, PG2 (tied to MR2),
and RESET return to logic low.
VOUT1
VOUT1
VSENSE1
22 µF 250 k
PG1
VIN2
0.22 µF
>2 V
EN1
RESET
EN1
<0.7 V
EN2
>2 V
MR
PG2
MR
250 k
RESET
PG2
VSENSE2
EN2
VOUT2
VOUT2
<0.7 V
47 µF
EN2
EN1
VOUT2
VOUT1
95%
95%
PG2
PG1
MR
(PG2 tied to MR)
RESET
t1
120ms
NOTE A: t1 – Time at which VIN is greater than VUVLO and MR is logic high.
NOTE B: The timing diagrams are not drawn to scale.
Figure 38. Timing When VOUT1 Is Enabled Before VOUT2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
APPLICATION INFORMATION
application conditions not shown in block diagram:
VIN1 and VIN2 are tied to the same fixed input
voltage greater than VUVLO. MR is initially logic
high but is eventually toggled.
TPS704xxPWP
(Fixed Output Option)
VIN
0.22 µF
VSENSE1
explanation of timing diagrams:
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 are at logic
low. Since VIN1 is greater than VUVLO and MR is
at logic high, RESET is also at logic high. When
EN2 is taken to logic low, VOUT2 turns on. Later,
when EN1 is taken to logic low, VOUT1 turns on.
When VOUT2 reaches 95% of its regulated output
voltage, PG2 goes to logic high. When VOUT1
reaches 95% of its regulated output voltage, PG1
goes to logic high. When MR is taken to logic low,
RESET is taken low. When MR returns to logic
high, RESET returns to logic high after a 120 ms
delay.
250 k
0.22 µF
RESET
PG2
EN1 EN1
MR
>2 V
>2 V
<0.7 V
EN2 EN2
VSENSE2
<0.7 V
95%
95%
PG1
MR
RESET
t1
120ms
NOTES: A. t1 – Time at which VIN is greater than VUVLO and MR is logic high.
B. The timing diagram is not drawn to scale.
Figure 39. Timing When MR Is Toggled
POST OFFICE BOX 655303
VOUT2
RESET
PG2
MR
2V
0.7 V
VOUT2
47 µF
PG2
26
250 k
250 k
VIN2
EN1
VOUT1
22 µF
PG1
EN2
VOUT2
VOUT1
VOUT1
VIN1
• DALLAS, TEXAS 75265
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
APPLICATION INFORMATION
application conditions not shown in block diagram:
VIN1 and VIN2 are tied to same fixed input voltage
greater than VUVLO. PG1 is tied to MR.
TPS704xxPWP
(Fixed Output Option)
VIN
explanation of timing diagrams:
0.22 µF
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 (tied to MR) and PG2
are at logic low. Since MR is at logic low, RESET
is also at logic low. When EN2 is taken to logic low,
VOUT2 turns on. Later, when EN1 is taken to logic
low, VOUT1 turns on. When VOUT2 reaches 95% of
its regulated output voltage, PG2 goes to logic
high. When VOUT1 reaches 95% of its regulated
output voltage, PG1 goes to logic high. When VIN1
is greater than VUVLO and MR (tied to PG2) is at
logic high, RESET is pulled to logic high after a
120 ms delay. When a fault on VOUT1 causes it to
fall below 95% of its regulated output voltage, PG1
(tied to MR) goes to logic low. Since MR is logic
low, RESET goes to logic low. VOUT2 is
unaffected.
VOUT1
VOUT1
VIN1
VSENSE1
22 µF
250 k
PG1
MR
VIN2
0.22 µF
RESET
PG2
EN1
EN1
250 k
RESET
PG2
>2 V
VSENSE2
<0.7 V
EN2
EN2
>2 V
VOUT2
<0.7 V
VOUT2
47 µF
EN2
EN1
VOUT2
VOUT1
95%
95%
FAULT ON VOUT1
PG2
PG1
MR
(PG1 tied to MR)
RESET
t1
120ms
NOTES: A. t1 – Time at which VIN is greater than VUVLO and MR is logic high.
B. The timing diagram is not drawn to scale.
Figure 40. Timing When There Is a Fault on VOUT1
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
APPLICATION INFORMATION
input capacitor
For a typical application, a ceramic input bypass capacitor (0.22 µF – 1 µF) is recommended to ensure device
stability. This capacitor should be as close to the input pins as possible. Due to the impedance of the input supply,
large transient currents cause the input voltage to droop. If this droop causes the input voltage to drop below
the UVLO threshold, the device turns off. Therefore, it is recommended to place a larger capacitor in parallel
with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor is dependent upon the
output current, response time of the main power supply, and the main power supply’s distance to the regulator.
At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum
UVLO threshold voltage during normal operating conditions.
output capacitor
As with most LDO regulators, the TPS704xx requires an output capacitor connected between each OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value for VOUT1 is 22 µF
and the ESR (equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended
capacitance value for VOUT2 is 47 µF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic,
aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements
described above. Larger capacitors provide a wider range of stability and better load transient response. Below
is a partial listing of surface-mount capacitors usable with the TPS704xx for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
VALUE
28
MFR.
PART NO.
680 µF
Kemet
T510X6871004AS
470 µF
Sanyo
4TPB470M
150 µF
Sanyo
4TPC150M
220 µF
Sanyo
2R5TPC220M
100 µF
Sanyo
6TPC100M
68 µF
Sanyo
10TPC68M
68 µF
Kemet
T495D6861006AS
47 µF
Kemet
T495D4761010AS
33 µF
Kemet
T495C3361016AS
22 µF
Kemet
T495C2261010AS
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TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
APPLICATION INFORMATION
programming the TPS70402 adjustable LDO regulator
The output voltage of the TPS70402 adjustable regulators is programmed using an external resistor divider as
shown in Figure 41.
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at the sense terminal increase the output voltage error. The recommended design procedure is to
choose R2 = 30.1 kΩ to set the divider current at approximately 50 µA and then calculate R1 using:
R1 +
ǒ
V
V
Ǔ
O *1
ref
(1)
R2
where
Vref = 1.224 V typ (the internal reference voltage)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS70402
VI
OUTPUT
VOLTAGE
IN
0.1 µF
>2.0 V
OUT
EN
VO
<0.7V
R1
+
R1
R2
UNIT
2.5 V
31.6
30.1
kΩ
3.3 V
51.1
30.1
kΩ
3.6 V
59.0
30.1
kΩ
FB
GND
R2
Figure 41. TPS70402 Adjustable LDO Regulator Programming
regulator protection
Both TPS704xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS704xx also features internal current limiting and thermal protection. During normal operation, the
TPS704xx regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current
to approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator
operation resumes.
POST OFFICE BOX 655303
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29
TPS70445, TPS70448, TPS70451, TPS70458, TPS70402
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/E 03/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
30
POST OFFICE BOX 655303
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THERMAL PAD MECHANICAL DATA
PowerPAD™ PLASTIC SMALL-OUTLINE
PWP (R-PDSO-G24)
www.ti.com
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