TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 ULTRALOW-NOISE, HIGH PSRR, FAST RF 1-A LOW-DROPOUT LINEAR REGULATORS FEATURES • • • • • • • 1-A Low-Dropout Regulator With Enable Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, and Adjustable (1.2-V to 5.5-V) High PSRR (53 dB at 10 kHz) Ultralow-Noise (40 µVRMS, TPS79630) Fast Start-Up Time (50 µs) Stable With a 1-µF Ceramic Capacitor Excellent Load/Line Transient Response Very Low Dropout Voltage (250 mV at Full Load, TPS79630) 3 x 3 SON, 6-Pin SOT223-6, and 5-Pin DDPAK Packages The TPS796xx family of low-dropout (LDO) low-power linear voltage regulators features high power supply rejection ratio (PSRR), ultralow-noise, fast start-up, and excellent line and load transient responses in small outline, 3 x 3 SON, SOT223-6, and 5-pin DDPAK packages. Each device in the family is stable with a small 1-µF ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (e.g., 250 mV at 1 A). Each device achieves fast start-up times (approximately 50 µs with a 0.001-µF bypass capacitor) while consuming very low quiescent current (265 µA typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 µA. The TPS79630 exhibits approximately 40 µVRMS of output voltage noise at 3.0-V output, with a 0.1-µF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time. APPLICATIONS RF: VCOs, Receivers, ADCs Audio Bluetooth™, Wireless LAN Cellular and Cordless Telephones Handheld Organizers, PDAs DCQ PACKAGE SOT223-6 (TOP VIEW) EN IN GND OUT NR/FB 1 2 3 4 5 DRB PACKAGE 3 x 3 SON (TOP VIEW) IN 1 6 GND IN 2 OUT 3 OUT 4 8 EN 7 NC EN IN GND OUT NR/FB 1 2 3 4 5 TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.7 70 5 NR KTT (DDPAK) PACKAGE (TOP VIEW) TPS79630 RIPPLE REJECTION vs FREQUENCY 80 6 GND Ripple Rejection − dB • • • • • IOUT = 1 mA 60 50 VIN = 4 V COUT = 10 µF CNR = 0.01 µF Output Spectral Noise Density − µV/Hz • • DESCRIPTION IOUT = 1 A 40 30 20 10 0 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 0.6 VIN = 5.5 V COUT = 2.2 µF CNR = 0.1 µF 0.5 0.4 0.3 IOUT = 1 mA 0.2 0.1 IOUT = 1.5 A 0.0 100 1k 10k 100k Frequency (Hz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2004, Texas Instruments Incorporated TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) PRODUCT TPS79601 TPS79618 TPS79625 VOLTAGE PACKAGE TJ SYMBOL SOT223-6 PS79601 DDPAK TPS79601 SOT223-6 PS79618 1.2 to 5.5 V 1.8 V DDPAK TPS79618 SOT223-6 PS79625 DDPAK TPS79625 SOT223-6 PS79628 2.5 V -40°C to +125°C DDPAK TPS79628 2.8 V 3 x 3 SON TPS79630 TPS79633 2 AMI SOT223-6 PS79630 DDPAK TPS79630 SOT223-6 PS79633 3V 3.3 V DDPAK (1) TPS79628 TPS79633 PART NUMBER TRANSPORT MEDIA, QUANTITY TPS79601DCQ Tube, 78 TPS79601DCQR Tape and Reel, 2500 TPS79601KTTT Reel, 50 TPS79601KTTR Reel, 500 TPS79618DCQ Tube, 78 TPS79618DCQR Tape and Reel, 2500 TPS79618KTTT Reel, 50 TPS79618KTTR Reel, 500 TPS79625DCQ Tube, 78 TPS79625DCQR Tape and Reel, 2500 TPS79625KTTT Reel, 50 TPS79625KTTR Reel, 500 TPS79628DCQ Tube, 78 TPS79628DCQR Tape and Reel, 2500 TPS79628KTTT Reel, 50 TPS79628KTTR Reel, 500 TPS79628DRB Tube, 78 TPS79628DRBR Tape and Reel, 2500 TPS79628DRBG4 Tube, 78 TPS79628DRBG4R Tape and Reel, 2500 TPS79630DCQ Tube, 78 TPS79630DCQR Tape and Reel, 2500 TPS79630KTTT Reel, 50 TPS79630KTTR Reel, 500 TPS79633DCQ Tube, 78 TPS79633DCQR Tape and Reel, 2500 TPS79633KTTT Reel, 50 TPS79633KTTR Reel, 500 For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet. TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS over operating temperature range (unless otherwise noted) (1) UNIT VIN range -0.3 V to 6 V VEN range -0.3 V to VIN + 0.3 V VOUT range 6V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, TJ -40°C to 150°C Storage temperature range, Tstg -65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE DISSIPATION RATINGS PACKAGE BOARD RΘJC RΘJA DDPAK High-K (1) 2 °C/W 23 °C/W SOT223 Low-K (2) 15 °C/W 3 x 3 SON (1) (2) 53 °C/W 56.2 °C/W The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce copper traces on top of the board. 3 TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating temperature range (TJ = -40 to 125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF (unless otherwise noted). Typical values are at +25°C. PARAMETER TEST CONDITIONS VIN Input voltage (1) IOUT Continuous output MIN TYP 2.7 current (1) Output voltage 0 UNIT 5.5 V 1 A TPS79618 0 µA < IOUT < 1 A 2.8 V < VIN < 5.5 V 1.764 1.8 1.836 V TPS79625 0 µA < IOUT < 1 A 3.5 V < VIN < 5.5 V 2.45 2.5 2.55 TPS79628 0 µA < IOUT < 1 A 3.8 V < VIN < 5.5 V 2.744 2.8 2.856 TPS79630 0 µA < IOUT < 1 A 4 V < VIN < 5.5 V 2.94 3.0 3.06 TPS79633 0 µA < IOUT < 1 A 4.3 V < VIN < 5.5 V 3.3 3.366 0.05 0.12 Output voltage line regulation (∆VOUT%/VIN) (1) VOUT + 1 V < VIN ≤ 5.5 V Load regulation (∆VOUT%/∆IOUT) 0 µA < IOUT < 1 A TPS79628 Dropout voltage (2) (VIN = VOUT (nom) - 0.1V) MAX 3.234 TJ = 25°C 5 IOUT = 1 A IOUT = 250 mA TPS79630 IOUT = 1 A TPS79633 IOUT = 1 A %/V mV 270 365 67 90 250 345 220 325 mV Output current limit VOUT = 0 V 4.2 A Ground pin current 0 µA < IOUT < 1 A 265 385 µA Shutdown current (3) VEN = 0 V, 2.7 V < VIN < 5.5 V 0.07 1 µA FB pin current FB = 1.8 V 1 µA Power-supply ripple rejection Output noise voltage (TPS79630) Time, start-up (TPS79630) TPS79630 2.4 V f = 100 Hz IOUT = 10 mA 59 f = 100 Hz IOUT = 1 A 54 f = 10 Hz IOUT = 1 A 53 f = 100 Hz IOUT = 1 A 42 CNR = 0.001 µF 54 CNR = 0.0047 µF 46 CNR = 0.01 µF 41 CNR = 0.1 µF 40 CNR = 0.001 µF 50 BW = 100 Hz to 100 kHz, IOUT = 1 A RL = 3 Ω, COUT = 1 µF CNR = 0.0047 µF dB µVRMS 75 CNR = 0.01 µF µs 110 EN pin current VEN = 0V -1 1 µA High-level enable input voltage 2.7 V < VIN < 5.5 V 1.7 VIN V Low-level enable input voltage 2.7 V < VIN < 5.5 V 0 0.7 V (1) (2) (3) 4 Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7V. For adjustable version, this applies only after VIN is applied; then VEN transitions high to low. TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION IN OUT Current Sense UVLO SHUTDOWN ILIM _ GND R1 + FB EN UVLO R2 Thermal Shutdown Quickstart Bandgap Reference 1.225 V VIN 250 kΩ External to the Device VREF FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION IN OUT UVLO Current Sense GND SHUTDOWN ILIM _ EN + R1 UVLO Thermal Shutdown R2 Quickstart VIN Bandgap Reference 1.225 V R2 = 40k 250 kΩ VREF NR Table 1. Terminal Functions TERMINAL NAME DESCRIPTION ADJ FIXED NR N/A 5 Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This improves power-supply rejection and reduces output noise. EN 1 1 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. FB 5 N/A 3, Tab 3, Tab IN 2 2 Unregulated input to the device. OUT 4 4 Output of the regulator. GND This terminal is the feedback input voltage for the adjustable device. Regulator ground 5 TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS TPS79630 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS79628 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS79628 GROUND CURRENT vs JUNCTION TEMPERATURE 2.795 4 3.05 VIN = 4 V COUT = 10 µF TJ = 25°C 3.04 3.03 350 VIN = 3.8 V COUT = 10 µF IOUT = 1 mA 3 2.790 3.02 330 VOUT (V) 3.00 2.99 2.98 IGND (µA) 3.01 VOUT (V) VIN = 3.8 V COUT = 10 µF 340 2 2.785 IOUT = 1 A 320 IOUT = 1 A 310 1 2.780 IOUT = 1 mA 2.97 300 2.96 2.95 0.0 0.2 0.4 0.6 0.8 0 2.775 −40 −25 −10 5 1.0 TJ (°C) TJ (°C) Figure 1. Figure 2. Figure 3. TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS79630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.6 VIN = 5.5 V COUT = 2.2 µF CNR = 0.1 µF 0.5 0.4 0.3 IOUT = 1 mA 0.2 0.1 IOUT = 1.5 A 0.0 100 1k 10k Frequency (Hz) Figure 4. 100k 2.5 Output Spectral Noise Density − µV/Hz 0.6 Output Spectral Noise Density − µV/Hz Output Spectral Noise Density − µV/Hz 20 35 50 65 80 95 110 125 IOUT (A) 0.7 6 290 −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN = 5.5 V COUT = 10 µF CNR = 0.1 µF 0.5 0.4 0.3 IOUT = 1 mA 0.2 0.1 0.0 100 IOUT = 1 A 1k 10k Frequency (Hz) Figure 5. 100k 2.0 CNR = 0.01 µF VIN = 5.5 V COUT = 10 µF IOUT = 1 A CNR = 0.1 µF 1.5 CNR = 0.0047 µF 1.0 CNR = 0.001 µF 0.5 0.0 100 1k 10k Frequency (Hz) Figure 6. 100k TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) TPS79628 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 60 80 VIN = 2.7 V COUT = 10 µF IOUT = 1 A 300 50 Ripple Rejection − dB 200 150 20 100 IOUT = 250 mA COUT = 10 µF BW = 100 Hz to 100 kHz 10 0 0.001 µF 0.0047 µF 50 30 20 10 0 −40 −25 −10 5 0.1 µF 0 20 35 50 65 80 95 110 125 CNR (µF) 1 TPS79630 RIPPLE REJECTION vs FREQUENCY TPS79630 RIPPLE REJECTION vs FREQUENCY IOUT = 1 A 40 30 20 10M START-UP TIME VIN = 4 V COUT = 2.2 µF CNR = 0.01 µF IOUT = 1 mA 60 VIN = 4 V, COUT = 10 µF, IOUT = 1.0 A 2.75 2.50 IOUT = 1 A 40 30 Enable CNR = 0.001 µF 2 50 CNR = 0.0047 µF 2.25 VOUT (V) 50 1M 3 70 Ripple Rejection − dB 60 10k 100k Figure 9. 80 VIN = 4 V COUT = 10 µF CNR = 0.1 µF 1k 100 Frequency (Hz) Figure 8. IOUT = 1 mA 10 TJ (°C) Figure 7. 70 IOUT = 1 A 40 50 0.01 µF IOUT = 1 mA 60 40 30 VIN = 4 V COUT = 10 µF CNR = 0.01 µF 70 250 80 Ripple Rejection − dB TPS79630 RIPPLE REJECTION vs FREQUENCY 350 VDO (mV) RMS − Root Mean Squared Output Noise − µVRMS TPS79630 ROOT MEAN SQUARED OUTPUT NOISE vs BYPASS CAPACITANCE 1.75 1.50 CNR = 0.01 µF 1.25 1 20 10 10 0 0 0.75 0.50 0.25 1 10 100 1k 10k 100k 1M 10M 0 1 1k 10k 100k 1M 10M 200 300 400 500 600 Figure 11. Figure 12. TPS79618 LINE TRANSIENT RESPONSE TPS79630 LINE TRANSIENT RESPONSE TPS79628 LOAD TRANSIENT RESPONSE 4 5 1 3 dv 1V s dt IOUT = 1 A COUT = 10 µF CNR = 0.01 µF IOUT (A) 2 4 IOUT = 1 A COUT = 10 µF CNR = 0.01 µF 3 ∆VOUT (mV) 0 −20 dv 1V s dt 150 20 0 −20 −40 −40 20 40 60 80 100 120 140 160 180 200 t (µs) Figure 13. 0 0 −1 ∆VOUT (mV) 40 20 0 100 Figure 10. 6 40 0 t (ns) 5 2 ∆VOUT (mV) 100 Frequency (Hz) VIN (V) VIN (V) Frequency (Hz) 10 20 40 60 80 100 120 140 160 180 200 t (µs) Figure 14. VIN = 3.8 V COUT = 10 µF CNR = 0.01 µF di 1A s dt 75 0 −75 −150 0 100 200 300 400 500 600 700 800 900 1000 t (µs) Figure 15. 7 TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) TPS79630 DROPOUT VOLTAGE vs OUTPUT CURRENT TPS79625 POWER UP/POWER DOWN VOUT = 2.5 V RL = 10 Ω CNR = 0.01 µF 3.5 3.0 300 250 TJ = 125°C 2.5 2.0 200 VDO (mV) 200 TJ = 25°C 150 1.5 100 1.0 VOUT 0.5 2 3 4 5 6 7 8 9 0 2.5 0 100 200 300 400 500 600 700 800 9001000 10 IOUT = 1 A COUT = 10 µF CNR = 0.01 µF 50 0 1 TJ = −40°C TJ = −40°C 50 0 0 TJ = 25°C 150 100 VIN 200 µs/Div 3.0 3.5 IOUT (mA) 4.0 4.5 5.0 VIN (V) Figure 17. Figure 18. TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT TPS79630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT Region of Instability 10 1 Region of Stability 0.1 0.01 ESR − Equivalent Series Resistance − Ω 100 COUT = 1 µF COUT = 2.2 µF Region of Instability 10 1 Region of Stability 0.1 10 30 60 125 250 500 750 1000 IOUT (mA) Figure 19. 100 COUT = 10.0 µF Region of Instability 10 1 Region of Stability 0.1 0.01 1 0.01 1 ESR − Equivalent Series Resistance − Ω Figure 16. 100 ESR − Equivalent Series Resistance − Ω TJ = 125°C 250 VDO (mV) 500 mV/Div 300 350 4.0 8 TPS79601 DROPOUT VOLTAGE vs INPUT VOLTAGE 1 10 30 60 125 250 500 750 1000 10 30 60 125 250 500 750 1000 IOUT (mA) IOUT (mA) Figure 20. Figure 21. TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 APPLICATION INFORMATION The TPS796xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 µA typically), and enable input to reduce supply currents to less than 1 µA when the regulator is turned off. A typical application circuit is shown in Figure 22. VIN IN VOUT OUT TPS796xx 2.2µF EN GND 1 µF NR 0.01µF Figure 22. Typical Application Circuit External Capacitor Requirements Although not required, it is good analog design practice to place a 0.1-µF — 2.2-µF capacitor near the input of the regulator to counteract reactive input sources. A 2.2-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS796xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. Like most low dropout regulators, the TPS796xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 1 µF. Any 1 µF or larger ceramic capacitor is suitable. The internal voltage reference is a key source of noise in an LDO regulator. The TPS796xx has an NR pin which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1-µF in order to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the functional block diagram. For example, the TPS79630 exhibits 40 µVRMS of output voltage noise using a 0.1-µF ceramic bypass capacitor and a 10-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250-kΩ resistor and external capacitor. Board Layout Recommendation to Improve PSRR and Noise Performance To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device. Regulator Mounting The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation. Solder pad footprint recommendations for the devices are presented in an application bulletin Solder Pad Recommendations for Surface-Mount Devices, literature number AB-132, available for download from the TI web site (www.ti.com). Programming the TPS79601 Adjustable LDO Regulator The output voltage of the TPS79601 adjustable regulator is programmed using an external resistor divider as shown in Figure 28. The output voltage is calculated using Equation 1: V V 1 R1 O REF R2 (1) where: • VREF = 1.2246 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error. 9 TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 Regulator Protection The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 µA, C1 = 15 pF for stability, and then calculate R1 using Equation 2: R1 V V O 1 REF The TPS796xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. R2 (2) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. The approximate value of this capacitor can be calculated as Equation 3: (3 x 10 –7) x (R1 R2) C1 (R1 x R2) (3) The TPS796xx features internal current limiting and thermal protection. During normal operation, the TPS796xx limits output current to approximately 2.8 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation resumes. The suggested value of this capacitor for several resistor ratios is shown in the table below (see Figure 23). If this capacitor is not used (such as in a unity-gain configuration) then the minimum recommended output capacitor is 2.2 µF instead of 1 µF. VIN IN 2.2 µF OUT TPS79601 EN NR 0.01 µF GND OUTPUT VOLTAGE PROGRAMMING GUIDE VOUT R1 FB R2 C1 1 µF OUTPUT VOLTAGE R1 R2 1.8 V 14.0 kΩ 30.1 kΩ 33 pF 3.6V 57.9 kΩ 30.1 kΩ 15 pF Figure 23. TPS79601 Adjustable LDO Regulator Programming 10 C1 TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 THERMAL INFORMATION The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as Equation 4: IO(avg) VI(avg) x I(Q) P max V V D I(avg) O(avg) (4) where: • VI(avg) is the average input voltage. • VO(avg) is the average output voltage. • IO(avg) is the average output current. • I(Q) is the quiescent current. For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in A CIRCUIT BOARD COPPER AREA temperature due to the regulator's power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RΘJC), the case to heatsink (RΘCS), and the heatsink to ambient (RΘSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance. Figure 24 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and (b) a DDPAK package mounted on a JEDEC high-K board. Equation 5 summarizes the computation: T J T PDmax x R R R A θJC θCS θSA (5) The RΘJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator's data sheet. The RΘSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks can have RΘCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small heatsinks. The RΘCS is a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a SOT223 package, RΘCS of 1°C/W is reasonable. TJ A RθJC B C B TC B RθCS A C RθSA SOT223 Package (a) TA DDPAK Package (b) C Figure 24. Thermal Resistances 11 TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 Equation 5 simplifies into Equation 6: T T PDmax x R J A θJA Rearranging Equation 6 gives Equation 7: T –T R J A θJA P max D (6) (7) Using Equation 6 and the computer model generated curves shown in Figure 25 and Figure 28, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment. R θJA max (125 55)°C2.5 W 28°CW 40 ° C/W No Air Flow 35 150 LFM 30 250 LFM 25 20 15 0.1 DDPAK Power Dissipation The DDPAK package provides an effective means of managing power dissipation in surface mount applications. The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the package. To illustrate, the TPS72525 in a DDPAK package was chosen. For this example, the average input voltage is 5 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is calculated as Equation 8: P Dmax (5 2.5) V x 1 A 2.5 W (8) Substituting TJmax for TJ into Equation 6 gives Equation 9: 12 (9) From Figure 25, DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm2 for the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 25 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows the side view of the operating environment used in the computer model. Rθ JA − Thermal Resistance − Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RΘJA). This RΘJA is valid only for the specific operating environment used in the computer model. 1 10 Copper Heatsink Area − cm2 100 Figure 25. DDPAK Thermal Resistance vs Copper Heatsink Area 2 oz. Copper Solder Pad with 25 Thermal Vias 1 oz. Copper Power Plane 1 oz. Copper Ground Plane Thermal Vias, 0.3 mm Diameter, 1,5 mm Pitch Figure 26. DDPAK Thermal Resistance From the data in Figure 27 and rearranging Equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed. TPS79601, TPS79618, TPS79625 TPS79628, TPS79630, TPS79633 www.ti.com SLVS351D – SEPTEMBER 2002 – REVISED OCTOBER 2004 5 180 ° C/W TA = 55°C 250 LFM Rθ JA − Thermal Resistance − PD Maximum (W) 4 150 LFM 3 No Air Flow 2 No Air Flow 160 140 120 100 80 60 40 20 1 10 Copper Heatsink Area − cm2 0 0.1 100 Figure 27. Maximum Power Dissipation vs Copper Heatsink Area SOT223 Power Dissipation The SOT223 package provides an effective means of managing power dissipation in surface mount applications. The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the package. To illustrate, the TPS72525 in a SOT223 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, no air flow is present, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is calculated as Equation 10: P Dmax (3.3 2.5) V x 1 A 800 mW (10) Substituting TJmax for TJ into Equation 6 gives Equation 11: R max (125 55)°C800 mW 87.5°CW θJA (11) From Figure 28, RΘJA vs PCB Copper Area, the ground plane needs to be 0.55 in2 for the part to dissipate 800 mW. The operating environment used to construct Figure 28 consisted of a board with 1 oz. copper planes. The package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1 oz. ground plane. 1 PCB Copper Area − in2 10 Figure 28. SOT223 Thermal Resistance vs PCB Area From the data in Figure 28 and rearranging Equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (see Figure 29). 6 TA = 25°C 5 4 PD Maximum (W) 1 0.1 4 in2 PCB Area 3 0.5 in2 PCB Area 2 1 0 0 25 50 75 100 125 150 TA (°C) Figure 29. SOT223 Power Dissipation 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPS79601DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR TPS79601DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR TPS79601KTT OBSOLETE DDPAK/ TO-263 KTT 5 None Call TI Call TI TPS79601KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 None Call TI Level-3-240C-168 HR TPS79601KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 None Call TI Level-3-240C-168 HR TPS79618DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR TPS79618DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR TPS79618KTT OBSOLETE DDPAK/ TO-263 KTT 5 None Call TI Call TI TPS79618KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 None Call TI Level-3-240C-168 HR TPS79618KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 None Call TI Level-3-240C-168 HR TPS79625DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR TPS79625DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR TPS79625KTT OBSOLETE DDPAK/ TO-263 KTT 5 None Call TI Call TI TPS79625KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 None Call TI Level-3-240C-168 HR TPS79625KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 None Call TI Level-3-240C-168 HR TPS79628DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR 2500 None Call TI Level-3-235C-168 HR None Call TI Call TI TPS79628DCQR ACTIVE SOP DCQ 6 TPS79628KTT OBSOLETE DDPAK/ TO-263 KTT 5 TPS79628KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 None Call TI Level-3-240C-168 HR TPS79628KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 None Call TI Level-3-240C-168 HR TPS79630DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR TPS79630DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR TPS79630KTT OBSOLETE DDPAK/ TO-263 KTT 5 None Call TI Call TI TPS79630KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 None Call TI Level-3-240C-168 HR TPS79630KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 None Call TI Level-3-240C-168 HR TPS79633DCQ ACTIVE SOP DCQ 6 78 None Call TI Level-3-235C-168 HR TPS79633DCQR ACTIVE SOP DCQ 6 2500 None Call TI Level-3-235C-168 HR TPS79633KTT OBSOLETE DDPAK/ TO-263 KTT 5 None Call TI Call TI TPS79633KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 None Call TI Level-3-240C-168 HR TPS79633KTTT ACTIVE DDPAK/ KTT 5 50 None Call TI Level-3-240C-168 HR Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2004 Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TO-263 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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