T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8032 64 32 x 32 Crosspoint Switch Matrix Input Buffers D0 – 31 CONFIGURE 800 Megabit/sec 32x32 Digital ECL Crosspoint Switch 64 Output Buffers O0 – 31 32 5-Bit Configuration Latches RESET IA0 – 4 OA0 – 4 5 5 5:32 Decoder SWITCHING PRODUCTS 32 5-Bit Program Latches LOAD TQ8032 CNTRL LVL The TQ8032 is a non-blocking 32 x 32 digital crosspoint switch capable of 800 Megabits per second per port data rates. Utilizing a fully differential internal data path and ECL I/O, the TQ8032 offers a high data rate with exceptional signal fidelity. The symmetrical switching and noise rejection characteristics inherent in differential logic result in low jitter and signal skew. The TQ8032 is ideally suited for digital video, data communications and telecommunication switching applications. The non-blocking architecture uses 32 fully independent 32:1 multiplexers (see diagram on page 2), allowing each output port to be independently programmed to any input port. The switch is configured by sequentially loading each multiplexer’s 5-bit program latch (OA0:4) with the desired input port address (IA0:4) and enabling the LOAD pin. When complete, the CONFIGURE pin is strobed and all new configurations are simultaneously transferred into the switch multiplexers. Data integrity is maintained on all unchanged data paths. Typical output waveform with all channels driven Features • >25 Gb/s aggregate BW • 800 Mb/s/port NRZ data rate • Non-blocking architecture • 500 ps delay match • Differential ECL-level data I/O; Selectable CMOS/TTLlevel control inputs • Low jitter and signal skew • Fully differential data path • Double buffered configuration latches • 196-pin CQFP package Electrical Characteristics Min Max Units Jitter 150 ps pk-pk Channel Propagation Delay 2300 ps Ch-to-Ch Propagation Delay Skew 500 ps Data Rate/Port 800 Mb/s Applications • Telecom/Datacom Switching • Hubs and Routers • Video Switching For additional information and latest specifications, see our website: www.triquint.com 1 TQ8032 Figure 1. Architecture 32 X 1-BIT MULTIPLEXER . . . . . . DATA IN 0 (I0) 32 X 1-BIT MULTIPLEXER Input Buffers . . . . . . . . Output Buffers . DATA IN 15 (I15) . . . . . . DATA OUT 31 (O31) . DATA IN 16 (I16) DATA OUT 0 (O0) Input Buffers . . . . . . DATA IN 31 (I31) CONFIGURE RESET LOAD 5:32 5 DECODE OUTPUT SELECT ADDRESS (OA0:4) Configuration Register 5 Program Register 5 INPUT ADDRESS (IA0:4) Table 2. Pin Descriptions Signal Name/Level Description I0 to I31, NI0 to NI31 Data input true and complement. Differential ECL Differential data input ports. O0 to O31, NO0 to NO31 Data output true and complement. Differential ECL Differential data output ports. IA0:4 Input address. CMOS/TTL Input port selection address that is written into the selected output port program latches (OA0:4). IA4 IA3 IA2 IA1 IA0 Input port 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 : : : : : : 1 1 1 1 1 31 OA0:4 CMOS/TTL Output select address. Output port selection address. Selects the output port program latches to which the input port selection address (IA0:4) is written. OA4 OA3 OA2 OA1 OA0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 : : : : : 1 1 1 1 1 2 For additional information and latest specifications, see our website: www.triquint.com Output port 0 1 2 : 31 TQ8032 Figure 2. Package Pinout VEE (-5V) NI7 I7 GND NI6 I6 NI5 I5 GND NI4 I4 NI3 I3 GND NI2 I2 NI1 I1 GND NI0 I0 RESET GND O0 NO0 GND O1 NO1 O2 NO2 GND O3 NO3 O4 NO4 GND O5 NO5 O6 NO6 GND O7 NO7 CTRL LVL VCC (+5V) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 O8 NO8 GND O9 NO9 O10 NO10 GND O11 NO11 O12 NO12 GND O13 NO13 O14 NO14 GND O15 NO15 O16 NO16 GND O17 NO17 O18 NO18 GND O19 NO19 O20 NO20 GND O21 NO21 O22 NO22 GND O23 NO23 O24 NO24 GND O25 NO25 Top View 196-Pin Package NOTE: All unmarked pins are not connected. 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 VEE (-5V) 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 06 97 98 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 VEE (-5V) I8 NI8 I9 GND NI9 I10 NI10 I11 GND NI11 I12 NI12 I13 GND NI13 I14 NI14 I15 GND NI15 I16 NI16 I17 GND NI17 I18 NI18 I19 GND NI19 I20 NI20 I21 GND NI21 I22 NI22 I23 GND NI23 I24 NI24 I25 GND NI25 I26 NI26 VCC (+5V) SWITCHING PRODUCTS VCC (+5V) VCC (+5V) GND I27 NI27 I28 NI28 GND I29 NI29 I30 NI30 GND I31 NI31 IA(4) IA(3) GND IA(2) IA(1) IA(0) CONFIG GND LOAD OA(4) OA(3) OA(2) GND OA(1) OA(0) NO31 O31 GND NO30 O30 NO29 O29 GND NO28 O28 NO27 O27 GND NO26 O26 VEE (-5V) Table 2. Pin Descriptions (continued) Signal Name/Level Description LOAD CMOS/TTL Enables the selected output port program latches while set ‘high’. Latches the data when set to a 'low' level. CONFIGURE CMOS/TTL Transfers the program latches data to the configuration latches and implements the switch changes while set "high." Latches the data when set to a "low" level. RESET CMOS/TTL Puts the switch into Broadcast or Pass-Through configuration, overwriting existing configurations. Broadcast mode: All output ports are connected to data input port 0. This mode is selected by applying a RESET “high” pulse with CONFIGURE held “low." Pass-through mode: I0 is connected to O0, I1 to O1, etc. This mode is selected by applying a RESET “high” pulse with CONFIGURE held “high." CNTRL LVL Input level control. GND/Open Selects the input levels for the input address (IA0:4), output address(OA0:4), CONFIGURE, LOAD and RESET inputs. Inputs are configured for TTL when tied to GND and CMOS when left unconnected. For additional information and latest specifications, see our website: www.triquint.com 3 TQ8032 Table 3. Absolute Maximum Ratings5 Symbol Parameter Absolute Max. Rating Notes TSTOR Storage Temperature –65° C to +150° C TCH Junction (Channel) Temperature –65° C to +150° C TC Case Temperature Under Bias –65° C to +125° C 2 VCC Supply Voltage 0 V to +7 V 3 VEE Supply Voltage –7 V to 0 V 3 VTT Load Termination Supply Voltage VEE to 0 V 4 VIN Voltage Applied to Any ECL Input; Continuous VEE –0.5 V to +0.5 V IIN Current Into Any ECL Input; Continuous –1.0 mA to +1.0 mA VIN Voltage Applied to Any TTL/CMOS Input; Continuous –0.5 V to VCC +0.5 V IIN Current Into Any TTL/CMOS Input; Continuous –1.0 mA to +1.0 mA VOUT Voltage Applied to Any ECL Output VEE –0.5 V to +0.5 V IOUT Current From Any ECL Output; Continuous –40 mA PD Power Dissipation per Output POUT = (GND – VOUT) x IOUT 50 mW Notes: 1. 2. 3. 4. 5. 1 4 For die applications. TC is measured at case top. All voltages specified with respect to GND, defined as 0V. Subject to IOUT and power dissipation limitations. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device's performance may be impaired and/or permanent damage to the device may occur. Table 4. Recommended Operating Conditions4 Symbol Min Typ Max Units Notes 85 °C 1,3 V TC Case Operating Temperature 0 VCC Supply Voltage 4.5 5.5 VEE Supply Voltage –5.5 –4.5 VTT Load Termination Supply Voltage RLOAD Output Termination Load Resistance ΘJC Thermal Resistance Junction to Case Notes: 1. 2. 3. 4. 4 Parameter V –2.0 V 2 50 Ω 2 2 °C/W TC measured at case top. Use of adequate heatsink is required. The VTT and RLOAD combination is subject to maximum output current and power restrictions. Contact the Factory for extended temperature range applications. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified. For additional information and latest specifications, see our website: www.triquint.com TQ8032 Table 5. DC Characteristics1,2 – Within recommended operating conditions, unless otherwise indicated. Parameter Min Max Units Test Cond. Notes VIH ECL Input Voltage High –1100 –500 mV VIL ECL Input Voltage Low VTT –1500 mV IIH ECL Input Current High +30 µA VIH = –0.7 V IIL ECL Input Current Low –30 µA VIL = –2.0 V VICM ECL Input Common Mode Voltage –1100 mV VIDIF ECL Input Differential Voltage (pk-pk) 400 1200 mV VIH CMOS/TTL Input Voltage High 3.5/2.0 VCC/VCC V 2 VIL CMOS/TTL Input Voltage Low 0/0 1.5/0.8 V 2 IIH CMOS/TTL Input Current High +100 µA VIH = VCC 2 IIL CMOS/TTL Input Current Low –100 µA VIL = 0 V 2 VOCM ECL Output Common Mode –1100 mV VODIF ECL Output Differential Voltage VOH ECL Output Voltage High –1000 –600 mV VOL ECL Output Voltage Low VTT –1600 mV IOH ECL Output Current High 20 27 mA IOL ECL Output Current Low 0 8 mA ICC Power Supply Current (+) 20 mA Power Supply Current (–) –1950 mA IEE Notes: –1500 –1500 600 SWITCHING PRODUCTS Symbol mV 1. Test conditions unless otherwise indicated: VTT = –2.0 V, RLOAD = 50 Ω to VTT. 2. Input level is selected by the CNTRL_LVL input. Tieing CNTRL_LVL to GND selects TTL levels, leaving CNTRL_LVL OPEN selects CMOS levels. Table 6. AC Characteristics1 – Within recommended operating conditions, unless otherwise indicated. Symbol Parameter Min Typ Max Units Notes Maximum Data Rate/Port 800 Mb/s 1,2 Jitter 150 ps pk-pk 1 T1 Channel Progagation Delay 2300 ps T2 Channel-to-Channel Delay Skew 500 ps T3 CONFIG to Data Out (Oi) Delay 5 T4 LOAD Pulse Width T5 CONFIG Pulse Width 7 ns T6 IAi to LOAD High Setup Time 0 ns T7 LOAD to IAi Low Hold Time 3 ns T8 OAi to LOAD High Setup Time 0 ns 7 ns ns T9 LOAD to OAi Low Hold Time 3 ns T10 Load ↑ to CONFIG ↑ 0 ns T11 RESET Pulse Width 10 TR,F Output Rise or Fall Time ns 300 400 ps 3 Notes: 1. Test conditions: VTT = –2.0 V, RLOAD = 50 Ω to VTT; ECL inputs: VIH = –1.1 V; VIL = –1.5 V; CMOS inputs: VIH = 3.5 V, VIL = 1.5 V; ECL outputs: VOH ≥ –1.0 V, VOL ≤ –1.6 V; ECL inputs rise and fall times ≤1 ns; CMOS inputs rise and fall times ≤ 20 ns. A bit error rate of 1E – 13 BER or better for 223 – 1 PRBS pattern, jitter and rise/fall times are guaranteed through characterization. 2. 800 Mb/s Non-Return-Zero (NRZ) data equivalent to 400 MHz clock signal. 3. Rise and fall times are measured at the 20% and 80% points of the transition from VOL max to VOL min. For additional information and latest specifications, see our website: www.triquint.com 5 TQ8032 Figure 3. Timing Diagram – Switch Configuration RESET Input Address Output Address LOAD T4 T10 CONFIGURE T8 T7 Data1 In DA T5 T9 T6 DB DE DD DC T1 Data1 Out DF DG T3 OA OB OC OE OD OF Invalid Data Out Note:1 No data loss on nchanged data paths Notes: 1. No data loss on unchanged paths. Figure 4. Timing Diagram – Reset RESET T11 T3 CONFIGURE Output Data Notes: 6 Broadcast Pass-through 1. LOAD input must remain LOW to insure correct programming of the switch. 2. “Broadcast” is defined as data input 0 to all data outputs (0..31). 3. “Pass-through” is defined as data input 0 to data output 0, data input 1 to data output 1, etc. For additional information and latest specifications, see our website: www.triquint.com OG TQ8032 Typical Performance Data Figure 5. Jitter – Single Channel 250 Vee = –5.0 V, Tc = 40° C 150 SWITCHING PRODUCTS Jitter (ps) 200 100 p-p 50 rms 0 0 0.2 0.4 0.6 0.8 1 Data Rate (Gb/s) Figure 6. Output Delay Output Delay (ns) 2.50 Vee = –5.0 V, Vin = 900 mV p-p 2.25 2.00 1.75 1.50 –60 –30 0 30 60 90 120 Case Temperature (°C) For additional information and latest specifications, see our website: www.triquint.com 7 TQ8032 Figure 7. Mechanical Dimensions Bottom View (marking up) Top View (marking down) CHIP CAPACITOR, 4 PLACES CL 49 1 50 LID PIN 1 INDEX 196 0.011 PIN WIDTH TQ8032-M XXXX A CL YYWW LOT CODE A 0.675 0.600 ± .0035 0.775 ± .003 148 98 99 DATE CODE 147 1. Part is symmetrical about the center axes. 2. Centerline bisects center pin in both directions. 3. See pad detail below. Section A-A HEAT SPREADER DEVICE .060 0.450 ± .0025 0.025 centers .125 0.015 CL 0.010 SEATING PLANE .064 0.088 0.715 CL PAD LAYOUT DETAIL Ordering Information TQ8032-M 800 Mb/s 32x32 ECL Crosspoint Switch Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997 8 For additional information and latest specifications, see our website: www.triquint.com