STMICROELECTRONICS TS4975EIJT

TS4975
Stereo Headphone Drive Amplifier with
Digital Volume Control via I2C Bus
■
Operating from VCC = 2.5V to 5.5V
■
I²C bus control interface
■
40mW output power @ VCC = 3.3V,
THD = 1%, F = 1kHz, with 16Ω load
■
Ultra-low consumption in stdby mode: 0.6µA
■
Digital volume control range from 18dB to
-34dB
■
14-step digital volume control
■
9 different output mode selections
■
Pop & click noise reduction circuitry
■
Flip-chip package, 12 x 300µm bumps (leadfree)
TS4975EIJT - Flip Chip
Pin out (top view)
Description
The TS4975 is a stereo audio headphone driver
capable of delivering up to 102mW per channel of
continuous average power into a 16Ω singleended load with 1% THD+N from a 5V power
supply. The overall gain of these headphone
drivers is controlled digitally by volume control
registers programmed via the I2C interface,
minimizing the number of external components
needed. This device can also easily be driven by
an MCU to select the output modes, through the
I2C bus interface.
A phantom ground configuration allows one to
avoid using bulky capacitors on the outputs of the
headphone amplifiers.
The TS4975 is packaged in a 1.8mm X 2.3mm
Flip Chip package, ideally suited for spaceconscious portable applications.
It has also an internal
protection mechanism.
thermal shutdown
OUT1
PHG1
PHG2
IN1
VCC
GND
IN2
SCL
SDA
ADD
BYPASS
OUT2
Applications
■
■
Mobile phones (cellular / cordless)
PDAs
Laptop/notebook computers
■
Portable audio devices
■
Order Codes
Part Number
TS4975EIJT
November 2005
Temperature Range
Package
Packing
Marking
-40, +85°C
Flip-chip
Tape & Reel
A75
Rev 3
1/36
www.st.com
36
Absolute Maximum Ratings
1
TS4975
Absolute Maximum Ratings
Table 1.
Key parameters and their absolute maximum ratings
Symbol
Value
Unit
6
V
Input Voltage (2)
GND to VCC
V
Toper
Operating Free Air Temperature Range
-40 to + 85
°C
Tstg
Storage Temperature
-65 to +150
°C
Maximum Junction Temperature
150
°C
R thja
Thermal Resistance Junction to Ambient (3)
200
°C/W
Pdiss
Power Dissipation
ESD
Susceptibility - Human Body Model(5)
ESD
VCC
Vi
Tj
Latch-up
Parameter
Supply voltage (1)
Internally Limited(4)
2
kV
Susceptibility - Machine Model (min. Value)
200
V
Latch-up Immunity
200
mA
Lead Temperature (soldering, 10sec)
260
°C
1. All voltages values are measured with respect to the ground pin.
2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V
3. Device is protected in case of over temperature by a thermal shutdown active @ 150°C.
4. Exceeding the power derating curves during a long period, may involve abnormal operating condition.
5. Human body model, 100pF discharged through a 1.5kOhm resistor, into pin to VCC device.
Table 2.
Operating conditions
Symbol
2/36
Parameter
Value
Unit
VCC
Supply Voltage
2.5 to 5.5v
V
RL
Load Resistor
>16
Ω
CL
Load Capacitor
RL = 16 to 100Ω,
RL > 100Ω,
400
100
pF
-40 to +85
°C
90
°C/W
Toper
Operating Free Air Temperature Range
R thja
Flip Chip Thermal Resistance Junction to Ambient
TS4975
Typical Application Schematics
Typical application schematics for the TS4975 are show in Figure 1, for a single-ended output
configuration and in Figure 2, for a phantom ground output configuration.
Figure 1.
Single-ended configuration
+
Cb
1µF
Cs
1µF
A1
B2
+
Vcc
Vcc
Bypass
Bias
IN1
Pre-Amplifier
IN1
OUT1 Amplifier
A2
RL = 16/32 Ohms
Cout1
Cin1
IN1
OUT1
A3
330nF
+
+
220µF
1k
PHG1 Amplifier
PHG1
B3
Mode
Select
PHG2 Amplifier
PHG2
IN2
Pre-Amplifier
C3
OUT2 Amplifier
RL = 16/32 Ohms
Cout2
Cin2
D2
IN2
OUT2
330nF
D3
+
+
220µF
1k
Volume control
ADD
SCL
SDA
D1
B1
C1
I2C
GND
IN2
C2
2
Typical Application Schematics
TS4975
ADD
SCL
SDA
3/36
Typical Application Schematics
Figure 2.
TS4975
Phantom ground output configuration
+
+
Vcc
Cs
1µF
Vcc
B2
A1
Cb
1µF
Bypass
Bias
IN1
Pre-Amplifier
IN1
OUT1 Amplifier
RL = 16/32 Ohms
Cin1
A2
IN1
OUT1
A3
+
330nF
PHG1 Amplifier
PHG1
B3
Mode
Select
PHG2 Amplifier
PHG2
IN2
Pre-Amplifier
IN2
RL = 16/32 Ohms
OUT2 Amplifier
Cin2
D2
IN2
OUT2
D3
+
330nF
Volume control
SCL
SDA
ADD
SCL
SDA
D1
B1
C1
C2
GND
I2C
ADD
4/36
C3
TS4975
TS4975
3
Electrical Characteristics
Electrical Characteristics
Table 3.
Electrical characteristics for the I²C interface
Symbol
Parameter
Value
Unit
VIL
Maximum Low level Input Voltage on pins SDA, SCL, VADD
0.3 VCC
V
VIH
Minimum High Level Input Voltage on pins SDA, SCL, VADD
0.7 VCC
V
SCL Maximum clock Frequency
400
kHz
Max Low Level Output Voltage, SDA pin, Isink = 3mA
0.4
V
Max Input current on SDA, SCL(1)
from 0.1 VCC to 0.9 VCC
10
µA
FSCL
Vol
Ii
1. SCL and SDA are CMOS inputs. The nominal input current is about few pA and not 10uA. 10µA refer to the I2C
bus specification.
Table 4.
Output noise (all inputs grounded)
Unweighted Filter
from VCC = 2.5V to 5V
Weighted Filter (A)
from VCC = 2.5V to 5V
SE, G = +2dB
34µVrms
23µVrms
SE, G = +18dB
67µVrms
45µVrms
PHG, G = +2dB
34µVrms
23µVrms
PHG, G = +18dB
67µVrms
45µVrms
5/36
Electrical Characteristics
Table 5.
Symbol
ICC
ISTBY
Voo
Pout
THD + N
PSRR
6/36
TS4975
VCC = +2.5 V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Parameter
Typ.
Max.
No input signal, no load,
Single-ended, Mode 1-4
3
4.2
No input signal, no load,
Single-ended, Mode 5-8
2
2.8
No input signal, no load,
Phantom Ground, Mode 1-4
4.6
6.5
No input signal, no load,
Phantom Ground, Mode 5-8
3.6
5.3
Standby Current
SCL and SDA at VCC level,
No input signal
0.6
2
µA
Output Offset Voltage
No input signal, RL = 32Ω,
Phantom Ground
5
50
mV
Supply Current
Output Power
(per channel)
Total Harmonic
Distortion + Noise
Power Supply
Rejection Ratio(1)
Conditions
Min.
Unit
mA
Single-ended, THD+N = 1% Max,
F = 1kHz, RL = 16Ω
15
21
Single-ended, THD+N = 1% Max,F = 1kHz,
RL = 32Ω
11
13
Phantom Ground, THD+N = 1% Max,
F = 1kHz, RL = 16Ω
15
21
Phantom Ground, THD+N = 1% Max,
F = 1kHz, RL = 32Ω
11
13
mW
Single-ended, AV = 2dB, RL = 32Ω,
Pout = 10 mW, 20Hz < F < 20kHz,
0.3
Single-ended, AV = 2dB, RL = 16Ω,
Pout = 15 mW, 20Hz < F < 20kHz
0.3
Phantom Ground, AV = 2dB, RL = 32Ω,
Pout = 10 mW, 20Hz < F < 20kHz
0.3
Phantom GroundAV = 2dB, RL = 16Ω,
Pout = 15 mW, 20Hz < F < 20kHz
0.3
Single-ended Output referenced to
Phantom Ground
F = 217Hz, RL = 16Ω, AV = 2dB
Vripple = 200mV pp, Input Grounded,
Cb = 1µF
60
Single-ended Output referenced to
Ground,
F = 217Hz, RL = 16Ω, AV = 2dB
Vripple = 200mV pp, Input Grounded,
Cb = 1µF
60
%
dB
TS4975
Table 5.
Symbol
Electrical Characteristics
VCC = +2.5 V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Parameter
Conditions
Min.
RL = 32Ω, AV = 2dB with Single-ended
SNR
ONoise
G
Channel Separation
Signal to Noise Ratio
A-Weighted
RL = 32Ω, AV = 2dB with Single-ended
F = 20Hz to 20kHz, Pout = 10mW
75
RL = 32Ω, AV = 2dB with Phantom Ground,
F = 1kHZ, Pout = 10mW
69
RL = 32Ω, AV = 2dB with Phantom Ground,
F = 20Hz to 20kHz, Pout = 10mW
69
AV = 2dB, RL = 32Ω, Pout = 12mW
Single-Ended
88
AV = 2dB, RL = 32Ω, Pout = 12mW
Phantom Ground
88
In1 & In2 to Out1 & Out2
dB
23
µVrms
23
-34
Digital Gain Stepsize
+18
4
Gain Error Tolerance
In1 & In2 Input
Impedance
All gain settings
twu
Wake up time
Cb = 1µF
tws
Standby time
25.5
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to
dB
dB
-1
Zin
Unit
dB
Output Noise Voltage, AV = 2dB, Single-ended
A-Weighted
AV = 2dB, Phantom Ground
Digital Gain Range
Max.
103
F = 1kHZ, Pout = 10mW
Crosstalk
Typ.
+1
dB
30
34.5
kΩ
110
180
ms
1
µs
VCC @ F = 217Hz
7/36
Electrical Characteristics
Table 6.
Symbol
ICC
ISTBY
Voo
Pout
THD + N
PSRR
8/36
TS4975
VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Parameter
Typ.
Max.
No input signal, no load,
Single-ended, Mode 1-4
3
4.2
No input signal, no load,
Single-ended, Mode 5-8
2
2.8
No input signal, no load,
Phantom Ground, Mode 1-4
4.6
6.5
No input signal, no load,
Phantom Ground, Mode 5-8
3.6
5.3
Standby Current
SCL and SDA at VCC level,
No input signal
0.6
2
µA
Output Offset Voltage
No input signal, RL = 32Ω,
Phantom Ground
5
50
mV
Supply Current
Output Power
(per channel)
Total Harmonic
Distortion + Noise
Power Supply
Rejection Ratio(1)
Conditions
Min.
Unit
mA
Single-ended, THD+N = 1% Max,
F = 1kHz, RL = 16Ω
34
40
Single-ended, THD+N = 1%
Max,F = 1kHz, RL = 32Ω
24
26
Phantom Ground, THD+N = 1% Max,
F = 1kHz, RL = 16Ω
34
40
Phantom Ground, THD+N = 1% Max,
F = 1kHz, RL = 32Ω
24
26
mW
Single-ended, AV = 2dB, RL = 32Ω,
Pout = 20 mW, 20Hz < F < 20kHz,
0.3
Single-ended, AV = 2dB, RL = 16Ω,
Pout = 30 mW, 20Hz < F < 20kHz
0.3
Phantom Ground, AV = 2dB, RL = 32Ω,
Pout = 20 mW, 20Hz < F < 20kHz
0.3
Phantom GroundAV = 2dB, R L = 16Ω,
Pout = 30 mW, 20Hz < F < 20kHz
0.3
Single-ended Output referenced to
Phantom Ground
F = 217Hz, RL = 16Ω, AV = 2dB
Vripple = 200mVpp, Input Grounded,
Cb = 1µF
61
Single-ended Output referenced to
Ground,
F = 217Hz, RL = 16Ω, AV = 2dB
Vripple = 200mVpp, Input Grounded,
Cb = 1µF
61
%
dB
TS4975
Table 6.
Symbol
Electrical Characteristics
VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Parameter
Conditions
Min.
RL = 32Ω, AV = 2dB with Single-ended
SNR
ONoise
G
Signal To Noise Ratio
RL = 32Ω, AV = 2dB with Single-ended
F = 20Hz to 20kHz, Pout = 20mW
75
RL = 32Ω, AV = 2dB with Phantom Ground,
F = 1kHZ, Pout = 20mW
69
RL = 32Ω, AV = 2dB with Phantom Ground,
F = 20Hz to 20kHz, Pout = 20mW
69
AV = 2dB, RL = 32Ω, Pout = 25mW
Single-Ended
90
AV = 2dB, RL = 32Ω, Pout = 25mW
Phantom Ground
90
In1 & In2 to Out1 & Out2
dB
23
µVrms
23
-34
Digital Gain Step size
+18
4
Gain Error Tolerance
In1 & In2 Input
Impedance
All gain settings
twu
Wake up time
Cb=1µF
tws
Standby time
25.5
dB
dB
-1
Zin
Unit
dB
Output Noise Voltage, AV = 2dB, Single-ended
A-Weighted
AV = 2dB, Phantom Ground
Digital Gain Range
Max.
103
F = 1kHZ, Pout = 20mW
Crosstalk Channel Separation
Typ.
+1
dB
30
34.5
kΩ
90
156
ms
1
µs
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217Hz
9/36
Electrical Characteristics
Table 7.
Symbol
ICC
ISTBY
Voo
Pout
VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Parameter
Supply Current
10/36
Conditions
Min.
Typ.
Max.
No input signal, no load,
Single-ended, Mode 1-4
3
4.2
No input signal, no load,
Single-ended, Mode 5-8
2
2.8
Unit
mA
No input signal, no load,
Phantom Ground, Mode 1-4
4.6
6.5
No input signal, no load,
Phantom Ground, Mode 5-8
3.6
5.3
Standby Current
SCL and SDA at VCC level,
No input signal
0.6
2
µA
Output Offset Voltage
No input signal, RL = 32Ω,
Phantom Ground
5
50
mV
Output Power
(per channel)
Total Harmonic
THD + N
Distortion + Noise
PSRR
TS4975
Power Supply
Rejection Ratio(1)
Single-ended, THD+N = 1% Max,
F = 1kHz, RL = 16Ω
92
102
Single-ended, THD+N = 1%
Max,F = 1kHz, RL = 32Ω
59
64
Phantom Ground, THD+N = 1% Max,
F = 1kHz, RL = 16Ω
92
98
Phantom Ground, THD+N = 1% Max,
F = 1kHz, RL = 32Ω
59
63
mW
Single-ended, AV = 2dB, RL = 32Ω,
Pout = 50 mW, 20Hz < F < 20kHz,
0.3
Single-ended, AV = 2dB, RL = 16Ω,
Pout = 80 mW, 20Hz < F < 20kHz
0.3
Phantom Ground, AV = 2dB, RL = 32Ω,
Pout = 50 mW, 20Hz < F < 20kHz
0.3
Phantom GroundAV = 2dB, RL = 16Ω,
Pout = 80 mW, 20Hz < F < 20kHz
0.3
Single-ended Output referenced to
Phantom Ground
F = 217Hz, RL = 16Ω, AV = 2dB
Vripple = 200mVpp, Input Grounded,
Cb = 1µF
63
Single-ended Output referenced to
Ground
F = 217Hz, RL = 16Ω, AV = 2dB
Vripple = 200mVpp, Input Grounded,
Cb = 1µF
63
%
dB
TS4975
Table 7.
Symbol
Electrical Characteristics
VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Parameter
Conditions
Min.
RL = 32Ω, AV = 2dB with Single-ended
RL = 32Ω, AV = 2dB with Single-ended
F = 20Hz to 20kHz, Pout = 50mW
75
RL = 32Ω, AV = 2dB with Phantom Ground,
F = 1kHZ, Pout = 50mW
69
RL = 32Ω, AV = 2dB with Phantom Ground,
F = 20Hz to 20kHz, Pout = 50mW
69
AV = 2dB, RL = 32Ω, Pout = 62mW
Single-Ended
95
AV = 2dB, RL = 32Ω, Pout = 62mW
Phantom Ground
95
Output Noise
Voltage,
A-Weighted
AV = 2dB, Single-ended
23
AV = 2dB, Phantom Ground
23
Digital Gain Range
In1 & In2 to Out1 & Out2
Crosstalk Channel Separation
ONoise
G
Signal To Noise
Ratio, A-Weighted
Max.
dB
dB
µVrms
-34
Digital Gain Step size
+18
4
Gain Error Tolerance
-1
Zin
In1 & In2 Input
Impedance
All gain settings
twu
Wake up time
Cb=1µF
tws
Standby time
Unit
103
F = 1kHZ, Pout = 50mW
SNR
Typ.
25.5
dB
dB
+1
dB
30
34.5
kΩ
80
144
ms
1
µs
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple )). Vripple is an added sinus signal to VCC @ F = 217Hz
11/36
Electrical Characteristics
10
THD + N (%)
1
THD+N vs. output power
RL = 8 Ω
Out. mode 1 - 8
SE, G = +2dB
BW < 125kHz
Tamb = 25 °C
Figure 4.
10
Vcc=2.5V
F=20kHz
1
Vcc=2.5V
F=1kHz
THD + N (%)
Figure 3.
TS4975
0.1
0.01
Vcc=3.3V
F=1kHz
Vcc=3.3V
F=20kHz
1E-3
1E-3
Vcc=5V
F=20kHz
0.01
THD+N vs. output power
RL = 8 Ω
Out. mode 1 - 8
SE, G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=3.3V
F=1kHz
Vcc=2.5V
F=1kHz
0.01
Output power (W)
10
THD + N (%)
1
THD+N vs. output power
RL = 16 Ω
Out. mode 1 - 8
SE, G = +2dB
BW < 125kHz
Tamb = 25 °C
Figure 6.
10
Vcc=2.5V
F=20kHz
1
Vcc=2.5V
F=1kHz
0.1
0.01
Vcc=3.3V
F=20kHz
Vcc=3.3V
F=1kHz
1E-3
1E-3
Vcc=5V
F=20kHz
0.01
THD+N vs. output power
RL = 16 Ω
Out. mode 1 - 8
SE, G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
F=20kHz
0.01
Vcc=5V
F=1kHz
THD + N (%)
1
THD+N vs. output power
Vcc=2.5V
F=20kHz
1
0.1
0.01
Vcc=2.5V
F=1kHz
1E-3
1E-3
Vcc=5V
F=20kHz
Vcc=3.3V
F=20kHz
Vcc=3.3V
F=1kHz
0.01
Output power (W)
12/36
Figure 8.
10
RL = 32 Ω
Out. mode 1 - 8
SE, G = +2dB
BW < 125kHz
Tamb = 25 °C
Vcc=5V
F=20kHz
0.01
Vcc=5V
F=1kHz
0.1
Output power (W)
THD + N (%)
10
Vcc=2.5V
F=1kHz
Vcc=3.3V
F=1kHz
1E-3
1E-3
0.1
Vcc=3.3V
F=20kHz
0.1
Output power (W)
Figure 7.
0.1
Output power (W)
THD + N (%)
Figure 5.
Vcc=5V
F=1kHz
Vcc=5V
F=20kHz
1E-3
1E-3
0.1
Vcc=2.5V
F=20kHz
0.1
0.01
Vcc=5V
F=1kHz
Vcc=3.3V
F=20kHz
THD+N vs. output power
RL = 32 Ω
Out. mode 1 - 8
SE, G = +18dB
BW < 125kHz
Tamb = 25 °C
0.1
0.01
Vcc=5V
F=1kHz
0.1
Vcc=2.5V
F=20kHz
1E-3
1E-3
Vcc=5V
F=20kHz
Vcc=2.5V
F=1kHz
Vcc=3.3V
F=20kHz
Vcc=3.3V
F=1kHz
0.01
Output power (W)
Vcc=5V
F=1kHz
0.1
TS4975
Electrical Characteristics
Figure 9.
THD + N (%)
1
RL = 8 Ω
Out. mode 1 - 8
PHG, G = +2dB
BW < 125kHz
Tamb = 25 °C
Figure 10. THD+N vs. output power
10
Vcc=2.5V
F=20kHz
Vcc=2.5V
F=1kHz
0.1
0.01
Vcc=3.3V
F=1kHz
Vcc=3.3V
F=20kHz
1E-3
1E-3
Vcc=2.5V
F=20kHz
Vcc=5V
F=20kHz
0.01
0.1
0.01
Vcc=5V
F=1kHz
0.01
Figure 12. THD+N vs. output power
Vcc=3.3V
F=20kHz
Vcc=2.5V
F=20kHz
Vcc=2.5V
F=1kHz
1
Vcc=2.5V
F=1kHz
THD + N (%)
THD + N (%)
10
0.1
Vcc=3.3V
F=20kHz
1E-3
1E-3
Vcc=5V
F=20kHz
0.01
0.1
0.01
Vcc=5V
F=1kHz
Vcc=2.5V
F=20kHz
0.01
10
Vcc=2.5V
F=20kHz
1
Vcc=5V
F=20kHz
1E-3
1E-3
Vcc=2.5V
F=1kHz
THD + N (%)
THD + N (%)
Figure 14. THD+N vs. output power
0.1
0.01
Vcc=3.3V
F=1kHz
0.01
Output power (W)
RL = 32 Ω
Out. mode 1 - 8
PHG, G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
F=1kHz
Vcc=5V
F=1kHz
0.1
Vcc=2.5V
F=20kHz
0.1
0.01
Vcc=3.3V
F=20kHz
0.1
Output power (W)
Figure 13. THD+N vs. output power
1
Vcc=5V
F=1kHz
Vcc=5V
F=20kHz
1E-3
1E-3
0.1
RL = 32 Ω
Out. mode 1 - 8
PHG, G = +2dB
BW < 125kHz
Tamb = 25 °C
Vcc=3.3V
F=1kHz
RL = 16 Ω
Out. mode 1 - 8
PHG, G = +18dB
BW < 125kHz
Tamb = 25°C
Output power (W)
10
0.1
Output power (W)
10
Vcc=3.3V
F=1kHz
Vcc=5V
F=1kHz
Vcc=5V
F=20kHz
1E-3
1E-3
0.1
Figure 11. THD+N vs. output power
0.01
Vcc=3.3V
F=1kHz
RL = 8 Ω
Out. mode 1 - 8
SE, G = +18dB
BW < 125kHz
Tamb = 25 °C
Output power (W)
RL = 16 Ω
Out. mode 1 - 8
PHG, G = +2dB
1 BW < 125kHz
Tamb = 25 °C
Vcc=3.3V
F=20kHz
1
Vcc=2.5V
F=1kHz
THD + N (%)
10
THD+N vs. output power
1E-3
1E-3
Vcc=5V
F=20kHz
Vcc=3.3V
F=20kHz
Vcc=3.3V
F=1kHz
0.01
Vcc=5V
F=1kHz
0.1
Output power (W)
13/36
Electrical Characteristics
TS4975
Figure 15. THD+N vs. frequency
Figure 16. THD+N vs. frequency
10
RL = 8Ω
Output mode 1 - 8
Single Ended
G = +2dB
1 BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=20mW
Vcc=3.3V
P=40mW
Vcc=5V
P=110mW
THD + N (%)
THD + N (%)
10
0.1
0.01
1
RL = 8Ω
Output mode 1 - 8
Single Ended
G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=20mW
100
1000
0.01
10000
100
Vcc=3.3V
P=30mW
Vcc=5V
P=80mW
THD + N (%)
THD + N (%)
10
RL = 16 Ω
Output mode 1 - 8
Single Ended
G = +2dB
BW < 125kHz
Tamb = 25°C
Vcc=2.5V
P=15mW
0.1
1
RL = 16 Ω
Output mode 1 - 8
Single Ended
G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=15mW
100
1000
0.01
10000
100
1000
10000
Figure 20. THD+N vs. frequency
10
RL = 32 Ω
Output mode 1 - 8
Single Ended
G = +2dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=10mW
Vcc=3.3V
P=20mW
Vcc=5V
P=50mW
0.1
THD + N (%)
10
THD + N (%)
Vcc=5V
P=80mW
Frequency (Hz)
Figure 19. THD+N vs. frequency
1
RL = 32 Ω
Output mode 1 - 8
Single Ended
G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=10mW
Vcc=3.3V
P=20mW
Vcc=5V
P=50mW
0.1
100
1000
Frequency (Hz)
14/36
Vcc=3.3V
P=30mW
0.1
Frequency (Hz)
0.01
10000
Figure 18. THD+N vs. frequency
10
1
1000
Frequency (Hz)
Figure 17. THD+N vs. frequency
0.01
Vcc=5V
P=110mW
0.1
Frequency (Hz)
1
Vcc=3.3V
P=40mW
10000
0.01
100
1000
Frequency (Hz)
10000
TS4975
Electrical Characteristics
Figure 21. THD+N vs. frequency
1
10
RL = 8 Ω
Output mode 1 - 8
Phantom Ground
G = +2dB
BW < 125kHz
Tamb = 25°C
Vcc=2.5V
P=20mW
Vcc=3.3V
P=40mW
Vcc=5V
P=110mW
THD + N (%)
THD + N (%)
10
Figure 22. THD+N vs. frequency
0.1
1
RL = 8 Ω
Output mode 1 - 8
Phantom Ground
G = +18dB
BW < 125kHz
Tamb = 25°C
Vcc=3.3V
P=40mW
Vcc=2.5V
P=20mW
0.1
Vcc=5V
P=110mW
0.01
100
1000
0.01
10000
100
Frequency (Hz)
Figure 23. THD+N vs. frequency
Vcc=3.3V
P=30mW
Vcc=5V
P=80mW
THD + N (%)
THD + N (%)
10
RL = 16 Ω
Output mode 1 - 8
Phantom Ground
G = +2dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=15mW
0.1
0.01
1
RL = 16 Ω
Output mode 1 - 8
Phantom Ground
G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=15mW
100
1000
0.01
10000
100
1000
10000
Figure 26. THD+N vs. frequency
10
RL = 32 Ω
Output mode 1 - 8
Phantom Ground
G = +2dB
BW < 125kHz
Tamb = 25°C
Vcc=2.5V
P=10mW
Vcc=3.3V
P=20mW
Vcc=5V
P=50mW
0.1
THD + N (%)
10
THD + N (%)
Vcc=5V
P=80mW
Frequency (Hz)
Figure 25. THD+N vs. frequency
0.01
Vcc=3.3V
P=30mW
0.1
Frequency (Hz)
1
10000
Figure 24. THD+N vs. frequency
10
1
1000
Frequency (Hz)
1
0.1
100
1000
Frequency (Hz)
10000
0.01
RL = 32 Ω
Output mode 1 - 8
Phantom Ground
G = +18dB
BW < 125kHz
Tamb = 25 °C
Vcc=2.5V
P=10mW
100
Vcc=3.3V
P=20mW
1000
Vcc=5V
P=50mW
10000
Frequency (Hz)
15/36
Electrical Characteristics
TS4975
Figure 27. Output power vs. power supply
voltage (each channel)
Figure 28. Output power vs. power supply
voltage (each channel)
160
140
120
220
F = 1kHz
Output mode 1 - 8
Single Ended
BW < 125 kHz
Tamb = 25 °C
Output power at 10% THD + N (mW)
Output power at 1% THD + N (mW)
180
8Ω
16 Ω
100
32 Ω
80
60
40
20
64 Ω
0
2.5
3.0
3.5
4.0
4.5
5.0
200
180
160
140
F = 1kHz
Output mode 1 - 8
Single Ended
BW < 125 kHz
Tamb = 25 °C
120
80
60
40
20
64 Ω
3.0
3.5
Vcc (V)
100
8Ω
16 Ω
32Ω
80
60
40
20
0
2.5
64 Ω
3.0
3.5
4.0
Vcc (V)
16/36
5.0
5.5
220
F = 1kHz
Output mode 1 - 8
Phantom Ground
BW < 125 kHz
Tamb = 25 °C
Output power at 10% THD + N (mW)
Output power at 1% THD + N (mW)
120
4.5
Figure 30. Output power vs. power supply
voltage (each channel)
180
140
4.0
Vcc (V)
Figure 29. Output power vs. power supply
voltage (each channel)
160
16 Ω
32 Ω
100
0
2.5
5.5
8Ω
4.5
5.0
5.5
200
180
160
140
F = 1kHz
Output mode 1 - 8
Phantom Ground
BW < 125 kHz
Tamb = 25 °C
120
8Ω
16 Ω
32 Ω
100
80
60
40
20
0
2.5
64 Ω
3.0
3.5
4.0
Vcc (V)
4.5
5.0
5.5
TS4975
Electrical Characteristics
Figure 31. PSSR vs. frequency
Figure 32. PSSR vs. frequency
0
0
Vcc = 2.5V
RL ≥ 16 Ω
Output mode 1 - 8
SE, Inp. grounded
Vripple = 200mVpp
-20
PSRR (dB)
-30
-10
-20
-30
G=+18dB
PSRR (dB)
-10
-40
G=+10dB
-50
G=+2dB
-60
-70
Vcc = 2.5V
RL ≥ 16Ω
Output mode 1 - 8
PHG, Inp. grounded
Vripple = 200mVpp
-40
G=+10dB
-50
G=+18dB
G=+2dB
-60
-70
-80
-80
G=-34dB
G=-10dB
-90
G=-2dB
-90
G=-10dB
G=-34dB
G=-2dB
-100
20
100
1000
-100
20
10000
100
Frequency (Hz)
Figure 33. PSSR vs. frequency
10000
Figure 34. PSSR vs. frequency
0
0
Vcc = 3.3V
RL ≥ 16 Ω
Output mode 1 - 8
SE, Inp. grounded
Vripple = 200mVpp
-20
-30
-10
-20
-30
G=+18dB
PSRR (dB)
-10
PSRR (dB)
1000
Frequency (Hz)
-40
G=+10dB
-50
G=+2dB
-60
-70
Vcc = 3.3V
RL ≥ 16Ω
Output mode 1 - 8
PHG, Inp. grounded
Vripple = 200mVpp
-40
G=+10dB
-50
G=+18dB
G=+2dB
-60
-70
-80
-80
G=-10dB
-90
G=-2dB
-90
G=-34dB
G=-10dB
G=-34dB
G=-2dB
-100
20
100
1000
-100
20
10000
100
Frequency (Hz)
Figure 35. PSSR vs. frequency
PSRR (dB)
-30
0
Vcc = 5V
RL ≥ 16 Ω
Output mode 1 - 8
SE, Inp. grounded
Vripple = 200mVpp
-10
-20
-30
G=+18dB
PSRR (dB)
-20
-40
G=+10dB
-50
G=+2dB
-60
-70
-80
Vcc = 5V
RL ≥ 16 Ω
Output mode 1 - 8
PHG, Inp. grounded
Vripple = 200mVpp
G=+18dB
-40
G=+10dB
-50
G=+2dB
-60
-70
-80
G=-10dB
-90
G=-34dB
G=-2dB
-100
20
10000
Figure 36. PSSR vs. frequency
0
-10
1000
Frequency (Hz)
100
1000
Frequency (Hz)
10000
G=-2dB
-90
-100
20
100
G=-10dB
1000
G=-34dB
10000
Frequency (Hz)
17/36
Electrical Characteristics
TS4975
Figure 37. Crosstalk vs. frequency
Figure 38. Crosstalk vs. frequency
0
Vcc = 2.5V
Output mode 1
-20 Single Ended
G = +2dB
-40 Tamb = 25 °C
-10
RL=16 Ω
Po=15mW
-60
RL=32Ω
Po=10mW
-80
Crosstalk Level (dB)
Crosstalk Level (dB)
0
-100
-120
-20
Vcc = 2.5V
Output mode 1
Phantom Ground
G = +2dB
Tamb = 25 °C
-30
-40
-60
-70
100
1000
-80
10000
100
Frequency (Hz)
0
-10
RL=16 Ω
Po=30mW
RL=32Ω
Po=20mW
-80
Crosstalk Level (dB)
Crosstalk Level (dB)
Vcc = 3.3V
Output mode 1
Single Ended
G = +2dB
Tamb = 25 °C
-60
-100
-120
-20
Vcc = 3.3V
Output mode 1
Phantom Ground
G = +2dB
Tamb = 25 °C
-30
-40
-60
-70
100
1000
-80
10000
100
10000
Figure 42. Crosstalk vs. frequency
0
0
Vcc = 5V
Output mode 1
-20 Single Ended
G = +2dB
-40 Tamb = 25 °C
-10
RL=16 Ω
Po=80mW
-60
RL=32Ω
Po=50mW
-80
-100
Crosstalk Level (dB)
Crosstalk Level (dB)
1000
Frequency (Hz)
Figure 41. Crosstalk vs. frequency
-20
Vcc = 5V
Output mode 1
Phantom Ground
G = +2dB
Tamb = 25 °C
-30
-40
RL=16 Ω
Po=80mW
RL=32 Ω
Po=50mW
-50
-60
-70
100
1000
Frequency (Hz)
18/36
RL=16 Ω
Po=30mW
RL=32 Ω
Po=20mW
-50
Frequency (Hz)
-120
10000
Figure 40. Crosstalk vs. frequency
0
-40
1000
Frequency (Hz)
Figure 39. Crosstalk vs. frequency
-20
RL=16 Ω
Po=15mW
RL=32 Ω
Po=10mW
-50
10000
-80
100
1000
Frequency (Hz)
10000
TS4975
Electrical Characteristics
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
SE, G = +2dB
Unweighted filter (20Hz to 20kHz)
THD+N < 0.5%
Tamb = 25 °C
2.5
3.3
Figure 44. SNR vs. power supply voltage
SNR (dB)
SNR (dB)
Figure 43. SNR vs. power supply voltage
5
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
SE, G = +2dB
Weighted filter type A
THD+N < 0.5%
Tamb = 25 °C
2.5
Vcc (V)
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
SE, G = +18dB
Unweighted filter (20Hz to 20kHz)
THD+N < 0.5%
Tamb = 25°C
2.5
3.3
5
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
SE, G = +18dB
Weighted filter type A
THD+N < 0.5%
Tamb = 25°C
2.5
Vcc (V)
3.3
Vcc (V)
5
Figure 48. SNR vs. power supply voltage
SNR (dB)
SNR (dB)
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
PHG, G = +2dB
Unweighted filter (20Hz to 20kHz)
THD+N < 0.5%
Tamb = 25 °C
2.5
3.3
Vcc (V)
Figure 47. SNR vs. power supply voltage
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
5
Figure 46. SNR vs. power supply voltage
SNR (dB)
SNR (dB)
Figure 45. SNR vs. power supply voltage
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
3.3
Vcc (V)
5
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
RL = 32Ω
RL = 16Ω
Out. mode 1 - 8
PHG, G = +2dB
Weighted filter type A
THD+N < 0.5%
Tamb = 25 °C
2.5
3.3
5
Vcc (V)
19/36
Electrical Characteristics
TS4975
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
Figure 50. SNR vs. power supply voltage
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
PHG, G = +18dB
Unweighted filter (20Hz to 20kHz)
THD+N < 0.5%
Tamb = 25°C
2.5
SNR (dB)
SNR (dB)
Figure 49. SNR vs. power supply voltage
3.3
5
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
RL = 32 Ω
RL = 16 Ω
Out. mode 1 - 8
PHG, G = +18dB
Weighted filter type A
THD+N < 0.5%
Tamb = 25°C
2.5
3.3
Vcc (V)
Figure 51. Frequency response
Figure 52. Current consumption vs. power
supply voltage
20
6
No loads
Tamb = 25 °C
18
Vcc = 5V, 3.3V, 2.5V
G = +18dB
10
8
Vcc = 5V, 3.3V, 2.5V
G = +2dB
6
PHG, Out. mode 5, 6, 7, 8
4
Output mode 1 - 8
RL = 32, 16Ω
Cin = 330nF
SE, PHG
BW < 125kHz
Tamb = 25 °C
12
Icc (mA)
14
Output level (dB)
PHG, Out. Mode 1, 2, 3, 4
5
16
3
Reset state
2
SE, Out. mode 1, 2, 3, 4
4
1
SE, Out. mode 5, 6, 7, 8
2
0
20
100
1000
0
10000
0
1
2
Frequency (Hz)
3
100
All gain setting
Tamb = 25°C
Low -3 dB Cut Off frequency (Hz)
All gain setting
Tamb=25 °C
Low -3dB Cut Off Frequency (Hz)
5
Figure 54. 3dB lower cut off frequency vs.
output capacitance
100
Minimum Input
Impedance
10
4
Vcc (V)
Figure 53. 3dB lower cut off frequency vs.
input capacitance
Typical Input
Impedance
Maximum Input
Impedance
0.1
1
Input Capacitor Cin ( µF)
20/36
5
Vcc (V)
10
RL=16 Ω
RL=32 Ω
1
100
1000
Output capacitor Cout ( µF)
TS4975
Electrical Characteristics
Figure 55. Power dissipation vs. output power Figure 56. Power dissipation vs. output power
(one channel
(one channel
120
70
Vcc = 3.3V
110 F = 1kHz
100 THD+N < 1%
50
Power Dissipation (mW)
Power Dissipation (mW)
Vcc = 2.5V
F = 1kHz
60
THD+N < 1%
RL=16 Ω , PHG
RL=32Ω , PHG
40
30
RL=16 Ω , SE
20
RL=32 Ω , SE
10
90
RL=16 Ω , PHG
80
RL=32 Ω , PHG
70
60
RL=16 Ω , SE
50
40
30
RL=32 Ω , SE
20
10
0
0
5
10
15
20
0
25
0
5
10
Output Power (mW)
15
20
25
30
35
40
45
Output Power (mW)
280
Vcc = 5V
260
F = 1kHz
240
THD+N < 1%
220
200
180
160
140
120
100
80
60
40
20
0
0
10 20 30
RL=16Ω , PHG
RL=32 Ω , PHG
RL=16 Ω , SE
RL=32 Ω , SE
40
50
60
70
Output Power (mW)
80
90 100 110
Flip-Chip Package Power Dissipation (W)
Power Dissipation (mW)
Figure 57. Power dissipation vs. output power Figure 58. Power derating curves
(one channel
1.4
1.2
Heat sink surface = 125mm
2
1.0
0.8
0.6
0.4
No Heat sink
0.2
0.0
0
25
50
75
100
125
150
Ambiant Temperature (°C)
21/36
Application Information
4
TS4975
Application Information
The TS4975 integrates 2 monolithic power amplifiers. The amplifier output can be configured
as either SE (single-ended) capacitively-coupled output or PHG (phantom ground) output.
Figure 1 on page 3 and Figure 2 on page 4 show schemes of these two configurations and
Section 4.2: Output configuration describes these configurations.
This chapter gives information on how to configure the TS4975 in application.
4.1
I²C bus interface
The TS4975 uses a serial bus, which conforms to the I²C protocol (the TS4975 must be
powered when it is connected to I²C bus), to control the chip’s functions with two wires: Clock
and Data. The Clock line and the Data line are bi-directional (open-collector) with an external
chip pull-up resistor (typically 10 kOhm). The maximum clock frequency in Fast-mode specified
by the I²C standard is 400kHz, which TS4975 supports. In this application, the TS4975 is
always the slave device and the controlling micro controller MCU is the master device.
The ADD pin is allows one to set one of two possible 7-bit device addresses. This setting is
needed for when a number of chips are connected to the same bus (for example two TS4975
devices), to avoid address conflicts. The two possible TS4975 addresses are:
●
$CCh when the ADD pin is connected to logic low voltage,
●
$CEh when ADD pin is connected to logic high voltage.
Table 8 summarizes the pin descriptions for the I²C bus interface.
Table 8.
I²C bus interface pin descriptions
Pin
4.1.1
Functional Description
SDA
This is the serial data pin
SCL
This is the clock input pin
ADD
User-setable portion of device’s I2C address
I²C bus operation
The host MCU can write into the TS4975 control register to control the TS4975, and read from
the control register to get a configuration from the TS4975. The TS4975 is addressed by the
byte consisting of 7-bit slave address and R/W bit.
Table 9.
The first byte after the START message for addressing the device
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
0
1
1
A0
X
In order to write data into the TS4975, after the “start” message, the MCU must send the
following data:
22/36
●
send byte with the I²C 7-bit slave address and with a low level for the R/W bit
●
send the data (control register setting)
TS4975
Application Information
All bytes are sent with MSB bit first. The transfer of written data ends with a “stop” message.
When transmitting several data, the data can be written with no need to repeat the “start”
message and addressing byte with the slave address.
In order to read data from the TS4975, after the “start” message, the MCU must send and
receive the following data:
●
send byte with the I²C 7-bit slave address and with a high level for the R/W bit
●
receive the data (control register value)
All bytes are read with MSB bit first. The transfer of read data is ended with “stop” message.
When transmitting several data, the data can be read with no need to repeat the “start”
message and the byte with slave address. In this case the value of control register is read
repeatedly.
When the thermo shutdown or pop and click reduction is active, specific values are read from
the TS4975 (see Section 4.9: Pop and click performance on page 31 and Section 4.10: Thermo
shutdown on page 32).
Figure 59. I²C write/read operations
SLAVE ADDRESS
SDA
S
1
1
0
0
1
CONTROL REGISTERS
1 A0
0
A
D7 D6 D5 D4 D3 D2 D1 D0 A
Volume Control
settings
Start condition
Output
Mode settings
R/W
Acknowledge
from Slave
Phantom Ground
settings
P
Stop condition
Acknowledge
from Slave
Ouput mode selection: G from -34 dB to + 18dB (by steps of 4dB)(1)
Table 10.
Output Mode #
Headphone Output 1
Headphone Output 2
0
SD
SD
1
G x In1
G x In2
2
G x In2
G x In1
3
G x In1
G x In1
4
G x In2
G x In2
5
SD
G x In1
6
SD
G x In2
7
G x In1
SD
8
G x In2
SD
1. SD = Shutdown Mode
In1 = Audio Input 1
In2= Audio Input2
G = Gain from Audio Input 1and Input 2 to Output1 and Output2
23/36
Application Information
4.1.2
TS4975
Gain setting operation
The gain of the TS4975 ranges from -34dB to +18 dB. At Power-up, both the right and left
channels are set in Standby mode.
Table 11.
G: Gain (dB) #
D7
(MSB)
D6
D5
D4
-34
0
0
0
1
-30
0
0
1
0
-26
0
0
1
1
-22
0
1
0
0
-18
0
1
0
1
-14
0
1
1
0
-10
0
1
1
1
-6
1
0
0
0
-2
1
0
0
1
+2
1
0
1
0
+6
1
0
1
1
+10
1
1
0
0
+14
1
1
0
1
+18
1
1
1
0
Table 12.
D2
D1
D0
COMMENTS
D7
(MSB)
24/36
Output mode settings truth table
D3: PHG
on / off
Table 13.
0
Gain settings truth table
0
X
X
X
PHG off
1
x
x
x
PHG on
x
0
0
0
MODE 1
X
0
0
1
MODE 2
X
0
1
0
MODE 3
X
0
1
1
MODE4
X
1
0
0
MODE 5
X
1
0
1
MODE 6
X
1
1
0
MODE 7
X
1
1
1
MODE 8
Stand-by mode I²C condition
D6
D5
D4
D3
D2
D1
D0
0
0
0
X
X
X
X
TS4975
Application Information
Table 14.
4.1.3
I²C control byte states
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
x
X
X
X
Undefined State
Acknowledge
The number of data bytes transferred between the start and the stop conditions from the CPU
master to the TS4975 slave is not limited. Each byte of eight bits is followed by one
acknowledge bit.
The TS4975 which is addressed, generates an acknowledge after the reception of each byte
that has been clocked out.
4.2
Output configuration
When the device is switched to Mode 5,6,7 or 8, where one channel is in shutdown, it means
that corresponding output is in a high impedance state.
4.2.1
Single-ended configuration
When the device is woken-up or switched via I²C interface to SE configuration, output amplifiers
are biased to the VCC/2 voltage and this voltage is present on OUT1 and OUT2 pins. Pins
PHG1 and PHG2 are in high impedance state. In this configuration an output capacitor, Cout, on
each output is needed to block the VCC/2 voltage and couples the audio signal to the load.
4.2.2
Phantom ground configuration
In a PHG configuration the internal buffers are connected to PHG1 and PHG2 pins and biased
to the VCC/2 voltage. Output amplifiers (pins OUT1 and OUT2) are also biased to the VCC/2
voltage. Therefore, no output capacitors are needed. The advantage of the PHG configuration
is the need for fewer external components as compared with a SE configuration. However, note
that the device has higher power dissipation (see Section 4.3: Power dissipation and efficiency
on page 26).
In this configuration, PHG1 and PHG2 pins must be shorted and the connection between these
pins should be as short as possible. For best crosstalk results, in this case, each speaker
should be connected with a separate PHG wire (2 speakers connected with 4 wires) as shown
in Figure 2: Phantom ground output configuration on page 4. You should avoid using only one
common PHG wire for both speakers (i.e. 2 speakers connected with 3 wires), which would give
much poorer crosstalk results.
4.2.3
Shutdown
When the device goes to shutdown from SE or PHG mode, PHG1 and PHG2 outputs are in a
high impedance state and OUT1 and OUT2 outputs are shorted together and connected to
bias voltage. This voltage steadily decreases as the bypass capacitor Cb discharges, and
reaches GND voltage when Cbypass is fully discharged. This output configuration is
implemented to reach the best pop performance during chip wake-up.
25/36
Application Information
4.3
TS4975
Power dissipation and efficiency
Hypotheses:
●
Voltage and current in the load are sinusoidal (Vout and I out).
●
Supply voltage is a pure DC source (VCC).
Regarding the load we have:
V out = V PEAK sin ωt ( V )
and
V out
I out = ---------RL
(A)
and
2
V PEAK
P out = ----------------2R L
(A )
Single-ended configuration:
The average current delivered by the supply voltage is:
π
Icc AVG
V PEAK
1 V PEAK
= ------ ∫ ----------------sin ( t ) dt = ----------------2π
RL
πR L
(A)
0
Figure 60. Current delivered by supply voltage in single-ended model
The power delivered by supply voltage is:
P supply = V C CI CC
AVG
(W)
So, the power dissipation by each amplifier is
P diss = P supply – P out ( W )
2V CC
- P out – P out ( W )
P diss = -----------------π RL
and the maximum value is obtained when:
∂P diss
∂ P out
26/36
= 0
TS4975
Application Information
and its value is:
2
P diss
Note:
MAX
V CC
= -----------2
π RL
(W)
This maximum value depends only on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
πV PEAK
P out
- = -------------------η = -----------------P supply
2V CC
The maximum theoretical value is reached when VPEAK = VCC/2, so
π
η = --- = 78.5%
4
Phantom ground configuration:
The average current delivered by the supply voltage is:
π
Icc AVG
2V PEAK
1 V PEAK
= --- ∫ ----------------sin ( t ) d t = -------------------π
RL
πR L
(A )
0
Figure 61. Current delivered by supply voltage in phantom ground mode
The power delivered by supply voltage is:
P supply = V C CI CC
AVG
(W)
Then, the power dissipation by each amplifier is
2 2V CC
P diss = ---------------------P out – P out
π RL
(W)
and the maximum value is obtained when:
∂P diss
∂ P out
= 0
and its value is:
2
P diss
Note:
MAX
2V CC
= -------------2
π RL
(W)
This maximum value depends only on power supply voltage and load values.
27/36
Application Information
TS4975
The efficiency is the ratio between the output power and the power supply:
P out
πV PEAK
η = ------------------ = -------------------P supply
4V CC
The maximum theoretical value is reached when VPEAK = VCC/2, so
π
η = --- = 39.25%
8
The TS4975 is a stereo amplifier so it has two independent power amplifiers. Each amplifier
produces heat due to its power dissipation. Therefore the maximum die temperature is the sum
of each amplifier’s maximum power dissipation. It is calculated as follows:
Pdiss 1 = Power dissipation due to the first channel power amplifier.
Pdiss 2 = Power dissipation due to the second channel power amplifier.
Total Pdiss = Pdiss 1 + Pdiss 2 (W)
In most cases, Pdiss 1 = Pdiss 2 , giving:
TotalP diss = 2P diss1
Single ended configuration:
2 2V CC
TotalP diss = ---------------------P out – 2P out ( W )
π RL
Phantom ground configuration:
4 2V C C
TotalPdiss = ---------------------P out – 2P out ( W )
π RL
4.4
Low frequency response
Input capacitor Cin
The input coupling capacitor blocks the DC part of the input signal at the amplifier input. In the
low-frequency region, Cin starts to have an effect. Cin with Zin forms a first-order, high-pass filter
with -3 dB cut-off frequency.
1
F C L = ------------------------ ( Hz )
2πZ in C in
Zin is the input impedance of the corresponding input (30 kΩ for In1 & In2).
Note:
For all inputs, the impedance value remains for all gain settings. This means that the lower cutoff frequency doesn’t change with gain setting. Note also that 30 kΩ is a typical value and there
is tolerance around this value (see Chapter 3: Electrical Characteristics on page 5).
From Figure 53 you could easily establish the Cin value for a -3dB cut-off frequency required.
28/36
TS4975
Application Information
Output capacitor Cout
In single-ended mode the external output coupling capacitors Cout are needed. This coupling
capacitor Cout with the output load RL also forms a first-order high-pass filter with -3 dB cut off
frequency.
1
F CL = -------------------------- ( Hz )
2πR L C out
See Figure 54 to establish the Cout value for a -3dB cut-off frequency required.
These two first-order filters form a second-order high-pass filter. The -3 dB cut-off frequency of
these two filters should be the same, so the following formula should be respected:
1
1
------------------------ ≅ -------------------------2πZ in C in 2πR L C out
4.5
Decoupling of the circuit
Two capacitors are needed to properly bypass the TS4975 — a power supply capacitor Cs and
a bias voltage bypass capacitor Cb.
Cs has a strong influence on the THD+N in high frequency (above 7kHz) and indirectly on the
power supply disturbances.
With 1 µF, you could expect similar THD+N performances like shown in the datasheet.
If Cs is lower than 1 µF, THD+N increases in high frequency and disturbances on power supply
rail are less filtered.
To the contrary, if Cs is higher than 1 µF, those disturbances an the power supply rail are more
filtered.
Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of
PSRR with input grounded in lower frequency:
●
If Cb is lower than 1 µF, THD+N increases at lower frequencies and the PSRR worsens
upwards.
●
If Cb is higher than 1 µF, the benefit on THD+N and PSRR in the lower frequency range is
small.
The value of Cb also has an influence on startup time.
4.6
Power-on reset
When power is applied to VCC, an internal Power On Reset holds the TS4975 in a reset state
(shutdown) until the supply voltage reaches its nominal value. The Power On Reset has a
typical threshold of 1.75V.
During this reset state the outputs configuration is the same like in the shutdown mode (see
Section 4.2: Output configuration on page 25).
29/36
Application Information
4.7
TS4975
Notes on PSRR measurement
What is PSRR?
The PSRR is the Power Supply Rejection Ratio. The PSRR of a device is the ratio between a
power supply disturbance and the result on the output. In other words, the PSRR is the ability of
a device to minimize the impact of power supply disturbance to the output.
How we measure the PSRR?
The PSRR was measured according to the schematic shown in Figure 62.
Figure 62. PSRR measurement schematic
Principles of operation
●
The DC voltage supply (VCC) is fixed
●
The AC sinusoidal ripple voltage (Vripple) is fixed
●
No bypasss capacitor Cs is used
The PSRR value for each frequency is calculated as:
RMS ( Out put )
( dB )
PSRR = 20Log --------------------------------RMS ( V
)
ripple
RMS is a rms selective measurement.
30/36
TS4975
4.8
Application Information
Startup time
When the TS4975 is controlled to switch from full standby (output mode 0) to another output
mode, a delay is necessary to stabilize the DC bias.This length of this delay depends on the Cb
and VCC values. A typical value can be calculated by following formula:
VC C
t wu = C b × ------------------------- × 50000 + 0.008 ( s )
V CC – 1.2
This formula assumes that Cb voltage is equal to 0 V. If the Cb voltage is not equal 0 V, the
startup time will be always lower.
In Figure 63 you could easily establish typical startup time for given supply voltage and bypass
capacitor Cb.
Figure 63. Typical startup time versus bypass capacitance
400
350
Startup time (ms)
300
Vcc=2.5V
250
200
Vcc=3.3V
150
100
Vcc=5V
50
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Bypass capacitor Cb (µF)
4.9
Pop and click performance
The TS4975 has internal pop and click reduction circuitry which eliminates the output
transients, for example during switch-on or switch-off phases, during a switch from an output
mode to another or during change in volume. The performance of this circuitry is closely linked
to the values of the input capacitor Cin, the output capacitor Cout (for Single-Ended
configuration) and the bias voltage bypass capacitor Cb.
The value of Cin and Cout is determined by the lower cut-off frequency value requested. The
value of Cb will affect the THD+N and PSRR values in lower frequencies.
The TS4975 is optimized to have a low pop and click in the typical schematic configuration (see
Figure 1 on page 3 and Figure 2 on page 4).
During the device start-up period when the pop and click reduction is active, the value $Fxh
(1111xxxx binary) can be read from the internal device registry.
Once the device is fully operational and the pop and click is inactive, the last value of control
register can be read.
31/36
Application Information
4.10
TS4975
Thermo shutdown
The TS4975 device has internal protection in case of over temperature by thermal shutdown.
Thermal shutdown is active when the device reaches temperature 150°C.
When thermo shutdown protection is active, value $Fxh (1111xxxx binary) can be read from the
internal device registry.
When thermo shutdown protection state disappears, the last value of control register can be
read.
4.11
Demoboard
A demoboard for the TS4975 is available.
For more information about this demoboard, please refer to Application Note AN2151, which
can be found on www.st.com.
Figure 67 on page 33 shows the schematic of the demoboard. Figure 64, Figure 65 and
Figure 66, show bottom layer, top layer and the component locations, respectively.
Figure 64. Bottom layer
Figure 66. Component location
32/36
Figure 65. Top layer
TS4975
Application Information
Figure 67. Demoboard schematic
Vcc1
Vcc1
+
+
Cn1
C2
1µF
U1
Cn6
Vcc
2
14
C1
1µF
Bypass
R1
1k
1
2
3
Bias
IN1
Pre-Amplifier
OUT1 Amplifier
C3
C10
IN1
1
IN1
OUT1
+
13
+
330nF
220µF
JP1
PHG1 Amplifier
PHG1
1
2
3
4
12
Mode
Select
1 J1
2
3
PHG2 Amplifier
PHONEJACK STEREO
PHG2
IN2
Pre-Amplifier
P2
Cn7
HEADER 4
1
2
3
P1
10
OUT2 Amplifier
C11
C4
6
IN2
IN2
OUT2
+
9
+
330nF
Volume control
ADD
SCL
SDA
3
4
Vcc1
5
I2C
GND
8
1
2
3
220µF
R2
1k
Cn8
TS4975
JP2
R3
10k
4
3
2
1
Cn2
Cn4
HEADER 4
Cn3
Vcc1
R4
10k
I2C BUS
SCL SDA
SCL
SDA
SDA
Vcc1
R5
10k
SDA
SCL
Vcc2
Vcc1
Vcc2
R6
360R
U2B
3
Vcc2
R7
10K
+
C5
1µF
CON1
1
6
2
7
3
8
4
9
5
KP1040
GND2
GND2
GND2
TXD
13
8
DTR
11
10
GND
GND2
C8
0.1µF
1
3
4
5
2
6
C9
0.1µF
T1IN
T2IN
C1+
C1C2+
C2V+
V-
U3
R1OUT
R2OUT
T1OUT
T2OUT
12
9
14
7
13
KP1040
R9
360R
U2C
5
12
6
11
KP1040
ST232
+
C7
0.1µF
+
C6
0.1µF
+
GND2
+
RS232
R1IN
R2IN
16
15
Cn5
Vcc
2
4
Vcc2
GND
16
14
Vcc2
15
R8
180R
U2A
1
Vcc2
GND2
GND2
33/36
Package Mechanical Data
5
TS4975
Package Mechanical Data
Figure 68. TS4975 footprint recommendation
75µm min.
100µm max.
500µm
500µm
Track
Φ=400µm typ.
150µm min.
Φ=340µm min.
500µm
500µm
Φ=250µm
Non Solder mask opening
Pad in Cu 18µm with Flash NiAu (2-6µm, 0.2µm max.)
Figure 69. Pin out (top view)
3
OUT1
PHG1
PHG2
OUT2
2
IN1
VCC
GND
IN2
1
BYPASS
SCL
SDA
ADD
C
D
A
B
Figure 70. Marking (top view)
■
Logo: ST
■
Part Number: A75
■
Date Code: YWW
■
The Dot is for marking pin A1
●
E Lead Free symbol
E
A75
YW W
34/36
TS4975
Package Mechanical Data
Figure 71. Flip-chip - 12 bumps
2300µm
1800µm
500µm
500µm
600µm
■
Die size: 2.3mm x 1.8mm ± 30µm
■
Die height (including bumps): 600µm
■
Bumps diameter: 315µm ±50µm
■
Bump diameter before reflew: 300µm ±10µm
■
Bumps height: 250µm ±40µm
■
Die height: 350µm ±20µm
■
Pitch: 500µm ±50µm
■
Capillarity: 60µm max
Figure 72. Tape & reel specification (top view)
1.5
4
1
1
A
Die size Y + 70µm
A
8
Die size X + 70µm
4
All dimensions are in mm
User direction of feed
35/36
Revision History
6
TS4975
Revision History
Date
Revision
Nov. 2004
1
Initial release.
July 2005
2
Product in full production
3
The following changes were made in this revision:
– Application notes updated
– Formatting changes throughout
Nov. 2005
Changes
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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36/36