TSA1203 Dual-channel 12-bit 40Msps 215mW A/D converter Features Dual simultaneous sample and hold inputs ■ Multiplexed binary word outputs ■ Built-in reference voltage with external bias capability D1 ■ VCCBE Common clocking between channels 41 40 39 38 37 36 D2 AGND 1 2 35 D3 AGND 3 34 D4 INIB 4 33 D5 INI ■ 44 43 42 D0(LSB) 1GHz analog bandwidth track-and-hold 48 47 46 45 GNDBE ■ index corner VCCBI SFDR = -75 dBc @ Fin = 10 MHz VCCBI CLKD ■ OEB Independent supply for CMOS output stage with 2.5 V/3.3 V capability AVCC ■ 7x7mm TQFP48 AVCC Single supply voltage: 2.5 V INCMI ■ REFMI Low power consumption: 215 mW@40 Msps REFPI ■ AGND 5 32 D6 IPOL 6 31 D7 TSA1203 AVCCB 7 30 D8 29 D9 AGND 8 INQ 9 28 D10 27 D11(MSB) AGND 10 Description 25 GNDBE GNDBI DVCC DGND SELECT CLK AVCC DGND 23 24 DVCC 17 18 19 20 21 22 AGND 14 15 16 INCMQ 13 REFMQ The TSA1203 is specifically designed for applications requiring a very low noise floor, high SFDR and good insulation between channels. It is based on a pipeline structure and digital error correction to provide high static linearity at FS = 40 Msps, and Fin = 10 MHz. 26 VCCBE AGND 12 REFPQ The TSA1203 is a new generation high-speed, dual-channel analog-to-digital converter implemented in a mainstream 0.25 µm CMOS technology that offers high performance and very low power consumption. INBQ 11 Applications ■ Medical imaging and ultrasound ■ 3G base station ■ I/Q signal processing applications ■ High-speed data acquisition systems ■ Portable instrumentation Each channel has an integrated voltage reference to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references. The ADC binary word outputs are multiplexed in a common bus with a small number of pins. A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially driven. The TSA1203 is available in extended temperature range (-40° C to +85° C), in a small 48-pin TQFP package. December 2006 Rev 4 1/30 www.st.com 30 Contents TSA1203 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 8.2 9 2/30 Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 Output enable mode (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.2 Select mode (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.1 Internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.2 External reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 Driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.5 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.7 EVAL1203/BA evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.7.1 Evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7.2 Consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7.3 Single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 Digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 Medical imaging applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TSA1203 10 Contents Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11.1 TQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3/30 Schematic diagram 1 TSA1203 Schematic diagram Figure 1. TSA1203 block diagram +2.5V/3.3V SELECT OEB CLK VCCBE Timing VINI VINBI VINCMI 12 AD 12 I channel common mode VREFPI REF I VREFMI IPOL M U X Polar. VREFPQ VREFMQ VINCMQ 12 12 Buffers REF Q common mode VINQ 12 AD 12 Q channel VINBQ GND Figure 2. D0 TO D11 GNDBE Timing diagram Simultaneous sampling on I/Q channels N+4 N+3 N+11 N+7 N+2 N N+13 N+12 N+6 I N-1 N+5 N+1 N+8 N+9 Q N+10 CLK Tpd I + Tod Tod SELECT CLOCK AND SELECT CONNECTED TOGETHER OEB sample N-8 I channel sample N-6 Q channel sample N Q channel sample N+1 Q channel sample N+2 Q channel DATA OUTPUT sample N-9 I channel 4/30 sample N-7 Q channel sample N+1 sample N+2 I channel I channel sample N+3 I channel TSA1203 Pin descriptions 2 Pin descriptions Table 1. Pin descriptions (TQFP48 package) Pin nb Name Description 1 AGND 2 INI 3 AGND 4 INBI 5 AGND Analog ground 6 IPOL Analog bias current input 7 AVCC Analog power supply 8 AGND Analog ground 9 INQ 10 AGND Analog ground 11 INBQ Q channel inverted analog input 12 AGND Analog ground 13 14 15 16 Observation Pin nb Name Analog ground I channel analog input 0V 25 GNDBE Analog ground 0V 26 I channel inverted analog input Digital buffer ground Digital buffer power VCCBE supply D11(MS Most significant bit B) output 28 D10 Digital output 29 D9 Digital output 30 D8 Digital output 2.5 V 31 D7 Digital output 0V 32 D6 Digital output 33 D5 Digital output 34 D4 Digital output 35 D3 Digital output 36 D2 Digital output 37 D1 Digital output 38 D0(LSB) 39 VCCBE 0V 40 GNDBE 0V Q channel analog input Q channel top reference voltage Q channel bottom REFMQ reference voltage Q channel input INCMQ common mode AGND Analog ground 27 Description 0V 0V REFPQ 0V Least significant bit output Digital buffer power supply Digital buffer ground Digital buffer power supply 17 AVCC Analog power supply 2.5 V 41 VCCBI 18 DVCC Digital power supply 2.5 V 42 CLKD Data clock input 19 DGND Digital ground 0V 43 OEB Output enable input 20 CLK 44 AVCC 45 AVCC 0V 46 INCMI 21 Clock input SELECT Channel selection 2.5 V CMOS input 2.5 V CMOS input 22 DGND Digital ground 23 DVCC Digital power supply 2.5 V 47 REFMI 24 GNDBI Digital buffer ground 0V 48 REFPI Analog power supply Analog power supply I channel input common mode I channel bottom reference voltage I channel top reference voltage Observation 0V 2.5 V/3.3 V CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) 2.5 V/3.3 V - see Table 14. 0V 2.5 V Idle at high level 2.5 V or 3.3 V 2.5 V/3.3 V CMOS input 2.5 V 2.5 V 0V 5/30 Dynamic characteristics 3 TSA1203 Dynamic characteristics Dynamic characteristics are measured under the following conditions, unless otherwise specified: AVCC = DVCC = VCCB = 2.5 V, FS = 40 Msps, Fin=10.13 MHz, Vin@ -1 dBFS, VREFP=0.8 V, VREFM=0 V, Tamb = 25° C. Table 2. Dynamic characteristics Symbol SFDR 4 Parameter Min Spurious free dynamic range SNR Signal to noise ratio THD Total harmonics distortion Typ Max Unit -75 -59.5 dBc 60.7 67 dB -73 -58 dBc SINAD Signal to noise and distortion ratio 56.5 66 dB ENOB Effective number of bits 9.1 10.8 bits Timing characteristics Timing characteristics are measured under the following conditions, unless otherwise specified: AVCC = DVCC = VCCB = 2.5 V, FS = 40 Msps, Fin=10.13 MHz, Vin@ -1 dBFS, VREFP=0.8 V, VREFM=0 V, Tamb = 25° C. Table 3. Symbol 6/30 Timing characteristics Parameter Test conditions Min Typ Max Unit 40 MHz 55 % FS Sampling frequency 0.5 DC Clock duty cycle 45 50 TC1 Clock pulse width (high) 22.5 25 ns TC2 Clock pulse width (low) 22.5 25 ns Tod Data output delay (clock edge to data valid) 9 ns 10 pF load capacitance Tpd I Data pipeline delay for I channel 7 cycles Tpd Q Data pipeline delay for Q channel 7.5 cycles Ton Falling edge of OEB to digital output valid data 1 ns Toff Rising edge of OEB to digital output tristate 1 ns TSA1203 5 Absolute maximum ratings Absolute maximum ratings Table 4. Absolute maximum ratings Symbol AVCC DVCC Parameter Analog supply voltage (1) Digital supply voltage (1) Values Unit 0 to 3.3 V 0 to 3.3 V VCCBE Digital buffer supply voltage (1) 0 to 3.6 V VCCBI Digital buffer supply voltage (1) 0 to 3.3 V IDout Digital output current -100 to 100 mA Tstg Storage temperature -65 to +150 °C HBM: human body ESD Latch-up model(2) 2 kV CDM: charged device model(3) 1.5 Class(4) A 1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3 V or VCC. 2. Electrostatic discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ.. 3. Discharge to ground of a device that has been previously charged. 4. ST Microelectronics corporate procedure number 0018695. 6 Operating conditions Table 5. Symbol Operating conditions Parameter Min Typ Max Unit AVCC Analog supply voltage 2.25 2.5 2.7 V DVCC Digital supply voltage 2.25 2.5 2.7 V VCCBE External digital buffer supply voltage 2.25 2.5 3.5 V VCCBI Internal digital buffer supply voltage 2.25 2.5 2.7 V VREFP I VREFP Q Forced top voltage reference 0.94 1.5 V VREFM I VREFM Q Forced bottom reference voltage 0 0.4 V VINCM I VINCM Q Forced input common mode voltage 0.2 1 V 7/30 Electrical characteristics 7 TSA1203 Electrical characteristics Electrical characteristics, unless otherwise specified, are measured at AVCC = DVCC = VCCB = 2.5 V, FS = 40 Msps, Rpol = 18 kΩ, Fin = 2 MHz, Vin@ -1 dBFS, VREFP=0.8 V, VREFM=0 V, and Tamb = 25° C. Table 6. Analog inputs Symbol Test conditions Parameter Min Typ Max Unit 1.1 2.0 2.8 Vpp Differential inputs mandatory VIN-VINB Full scale reference voltage Cin Input capacitance 7.0 pF Req Equivalent input resistor 10 kΩ BW Analog input bandwidth 1000 MHz ERB Effective resolution bandwidth 70 MHz Table 7. Vin@full scale, Fs=40 Msps Digital inputs and outputs Symbol Parameter Test conditions Min Typ Max Unit 0 0.8 V Clock and Select inputs VIL Logic "0" voltage VIH Logic "1" voltage 2.0 2.5 V OEB input VIL Logic "0" voltage VIH Logic "1" voltage 0 0.75 x VCCBE 0.25 x VCCBE VCCBE V V Digital outputs VOL Logic "0" voltage IOL=10 µA VOH Logic "1" voltage IOH=10 µA 0.9 x VCCBE VCCBE IOZ High impedance leakage current OEB set to VIH -1.67 0 CL Output load capacitance Table 8. 0.1 x VCCBE V V 1.67 µA 15 pF Reference voltage Symbol 8/30 0 Parameter Min Typ Max Unit VREFP I VREFP Q Top internal reference voltage 0.81 0.88 0.94 V VINCM I VINCM Q Input common mode voltage 0.41 0.46 0.50 V TSA1203 Electrical characteristics Table 9. Power consumption Symbol Parameter Min Typ Max Unit ICCA Analog supply current 76 96.5 mA ICCD Digital supply current 3.5 4.9 mA ICCBE Digital buffer supply current (10 pF load) 6 9.4 mA ICCBI Digital buffer supply current 100 440 µA Power consumption in normal operation mode 215 271 mW Thermal resistance (TQFP48) 80 Pd Rthja Table 10. °C/W Accuracy Symbol Parameter Min Typ Max Unit OE Offset error 2.97 LSB GE Gain error 0.1 % DNL Differential non linearity ±0.52 LSB INL Integral non linearity ±3 LSB Monotonicity and no missing codes Guaranteed - Table 11. Matching between channels Symbol Parameter Min Typ Max Unit 1 % GM Gain match 0.04 OM Offset match 0.88 LSB PHM Phase match 1 dg XTLK Crosstalk rejection 85 dB 9/30 Electrical characteristics Figure 3. TSA1203 Static parameter: integral non linearity(a) FS = 40 Msps, ICCA = 60 mA, Fin = 2 MHz 2.5 2 INL (LSBs) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code Figure 4. Static parameter: differential non linearity(a) Fs = 40 Msps, ICCA = 60 mA, Fin = 2 MH 0.6 DNL (LSBs) 0.4 0.2 0 -0.2 -0.4 -0.6 0 500 1000 1500 2000 2500 3000 3500 Output Code a. For parameter definitions, see Section 10: Definitions of specified parameters on page 25. 10/30 4000 TSA1203 Electrical characteristics Figure 5. Linearity vs. FS Fin = 5MHz Figure 6. 12 ENOB_I -40 11.5 11 75 10.5 70 10 SNR_I 9.5 SNR_Q 65 9 8.5 60 SINAD_I 8 SINAD_Q 7.5 55 Dynamic parameters (dBc) ENOB_Q ENOB (bits) Dynamic parameters (dB) 80 7 35 40 45 Distortion vs. FS Fin = 5MHz -50 THD_Q SFDR_Q -60 -70 -80 THD_I -90 SFDR_I -100 50 35 40 Fs (MHz) Linearity vs. Fin FS= 40MHz, ICCA = 60mA Figure 8. ENOB_Q 85 11 80 10 75 SNR_Q SNR_I 70 9 ENOB_I 65 8 60 SINAD_I 7 SINAD_Q 55 50 6 0 20 40 60 -60 -70 -80 THD_I SFDR_I -90 0 SINAD_I SNR_I 8 65 7 60 6 SINAD_Q SNR_Q 55 5 50 -40 10 60 Temperature (°C) 4 110 Dynamic parameters (dBc) 9 ENOB (bits) Dynamic parameters (dB) 10 ENOB_Q 70 60 80 100 11 75 40 Figure 10. Distortion vs. temperature FS=40Msps, ICCA=60mA, Fin=2MHz 12 80 20 Fin (MHz) ENOB_I 85 SFDR_Q THD_Q -100 80 Linearity vs. temperature FS=40MHz, ICCA=60mA, Fin=2MHz 90 Distortion vs. Fin FS= 40MHz, ICCA = 60mA -50 Fin (MHz) Figure 9. 50 -40 12 ENOB (bits) Dynamic parameters (dB) 90 Dynamic parameters (dBc) Figure 7. 45 Fs (MHz) 95 90 85 80 SFDR_Q 75 THD_Q 70 65 THD_I 60 SFDR_I 55 50 -40 10 60 110 Temperature (°C) 11/30 Electrical characteristics TSA1203 12 68 66 11.5 SNR_Q SINAD_Q 64 11 62 60 SINAD_I SNR_I 10.5 58 10 56 ENOB_I ENOB (bits) Dynamic parameters (dB) 70 ENOB_Q 54 9.5 52 50 2.25 Dynamic Parameters (dBc) Figure 11. Linearity vs. AVCC Figure 12. Distortion vs. AVCC FS=40Msps, ICCA=60mA, Fin=10MHz FS=40Msps, ICCA=60mA, Fin=10MHz 2.45 2.55 -55 -60 2.65 SFDR_I -65 SFDR_Q -70 -75 THD_I -80 -85 -90 -95 -100 2.25 9 2.35 -50 THD_Q 2.35 2.45 2.55 2.65 AVCC (V) AVCC (V) 12 68 66 11.5 SNR_Q SINAD_Q 64 11 62 60 SINAD_I 10.5 SNR_I 58 10 56 ENOB_I ENOB (bits) Dynamic parameters (dB) 70 ENOB_Q 54 9.5 52 50 2.25 Dynamic Parameters (dBc) Figure 13. Linearity vs. DVCC Figure 14. Distortion vs. DVCC FS=40Msps, ICCA=60mA, Fin=10MHz FS=40Msps, ICCA=60mA, Fin=10MHz 2.45 2.55 -55 -60 2.65 SFDR_I -65 SFDR_Q -70 -75 -80 THD_Q THD_I -85 -90 2.25 9 2.35 -50 2.35 2.45 2.55 2.65 DVCC (V) DVCC (V) 12 68 66 11.5 SNR_Q SINAD_Q 64 11 62 60 SINAD_I SNR_I 10.5 58 10 56 ENOB_I ENOB_Q 54 9.5 52 50 2.25 9 2.35 2.45 2.55 VCCBI (V) 12/30 2.65 ENOB (bits) Dynamic parameters (dB) 70 Dynamic Parameters (dBc) Figure 15. Linearity vs. VCCBI Figure 16. Distortion vs.VCCBI FS=40Msps, ICCA=60mA, Fin=10MHz FS=40Msps, ICCA=60mA, Fin=10MHz -50 -55 -60 SFDR_I -65 SFDR_Q -70 -75 -80 THD_I THD_Q -85 -90 2.25 2.35 2.45 VCCBI (V) 2.55 2.65 TSA1203 Electrical characteristics 12 69 11.5 68 ENOB_I ENOB_Q 11 67 10.5 66 SNR_Q 65 SNR_I 10 64 9.5 63 SINAD_Q 62 ENOB (bits) Dynamic parameters (dB) 70 9 SINAD_I 8.5 61 60 2.25 Figure 18. Distortion vs. VCCBE FS=40Msps, ICCA=60mA, Fin=5MHz Dynamic Parameters (dBc) Figure 17. Linearity vs. VCCBE FS=40Msps, ICCA=60mA, Fin=5MHz -50 -60 SFDR_Q 3.25 -80 -90 -100 2.75 Figure 20. Distortion vs. duty cycle FS=40MHz, ICCA=60mA, Fin=5MHz 12 11 90 10 80 9 ENOB_Q SNR_I SINAD_I 8 7 60 SNR_Q 6 SINAD_Q 5 40 4 49 50 51 Positive Duty Cycle (%) 52 Dynamic parameters (dBc) -40 ENOB_I ENOB (bits) Dynamic parameters (dB) 100 48 3.25 VCCBE (V) Figure 19. Linearity vs. duty cycle FS=40MHz, ICCA=60mA, Fin=5MHz 50 THD_Q THD_I VCCBE (V) 70 SFDR_I -70 -110 2.25 8 2.75 -40 -50 SFDR_Q THD_Q -60 -70 THD_I -80 SFDR_I -90 -100 48 49 50 51 52 Positive Duty Cycle (%) 13/30 Electrical characteristics TSA1203 Figure 21. Single-tone 8K FFT at 40 Msps - Channel Q Fin = 5MHz, ICCA = 60mA, Vin@-1dBFS Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 22. Dual-tone 8K FFT at 40Msps - Channel Q Fin1 = 0.93MHz, Fin2 = 1.11MHz, ICCA = 70mA, Vin1@-7dBFS, Vin2@-7dBFS, IMD = -69dBc Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 2.5 5 7.5 10 12.5 Frequency (MHz) 14/30 15 17.5 20 TSA1203 8 Application information Application information The TSA1203 is a dual-channel, 12-bit resolution high speed analog-to-digital converter based on a pipeline structure and deep sub-micron CMOS process to achieve the best performance in terms of linearity and power consumption. Each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. The input signals are simultaneously sampled, for both channels, on the rising edge of the clock. The output data is delivered on the rising edge of the clock for channel I, and on the falling edge of the clock for channel Q, as shown in Figure 2: Timing diagram on page 4. The digital data produced at the various stages must be time-delayed according to the order of conversion. Finally, a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. The TSA1203 is pin-to-pin compatible with the dual 10 bits/20 Msps TSA1005-20, the dual 10 bits /40 Msps TSA1005-40 and the dual 12 bits/ 20 Msps TSA1204. 8.1 Additional functions To simplify the application board as much as possible, the following operating modes are provided: 8.1.1 ● Output enable (OEB) mode ● Select mode Output enable mode (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital output buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data arrives on the output with a very short Ton delay. This mechanism allows the chip select of the device. Figure 2: Timing diagram on page 4 summarizes this functionality. If you do not want to use OEB mode, the OEB pin should be grounded through a low value resistor. 8.1.2 Select mode (SELECT) The digital data output from each of the ADC cores is multiplexed to share the same output bus. This prevents an increase in the number of pins and allows to use the same package as for a single-channel ADC like the TSA1201. The information channel is selected with the "SELECT" pin. When set to high level (VIH), the channel I data is present on the D0-D11 output bus. When set to low level (VIL), the channel Q data is delivered on D0-D11. By connecting SELECT to CLK, channel I and channel Q are simultaneously present on D0D11, channel I on the rising edge of the clock and channel Q on the falling edge of the clock. (refer to Figure 2: Timing diagram on page 4). 15/30 Application information 8.2 TSA1203 References and common mode connection VREFM must always be connected directly to ground externally for most applications. 8.2.1 Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. It is recommended to decouple the VREFP and INCM pins in order to minimize low and high frequency noise (see Figure 23). Figure 23. Internal reference and common mode setting 0.89V VIN TSA1203 VINB 330pF 10nF 4.7μF VREFP INCM 0.46V 330pF 10nF 4.7μF VREFM 8.2.2 External reference and common mode Each of the voltages VREFP, VREFM and INCM can be fixed externally to better fit the application needs (refer to Table 5: Operating conditions on page 7 for min/max values). It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. The VREFP and VREFM voltages set the analog dynamic range at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). The INCM voltage is half the value of VREFP-VREFM. The best signal-to-noise performance is achieved with a dynamic range at its maximum value. To obtain this, VREFM can be connected to GND, and VREFP can be set up to 1.5 V maximum. However, signal to noise performance is a trade-off with the THD, with a possibility of degraded THD under these conditions. To obtain the highest performance from the TSA1203 device, we recommend implementing the configuration shown in Figure 24 with the STMicroelectronics TS821 or TS4041-1.2 Vref. 16/30 TSA1203 Application information Figure 24. External reference setting 1kΩ 1.2V 330pF 10nF 4.7μF VCCA VREFP VIN TSA1203 VINB VREFM 8.3 TS821 TS4041 external reference Driving the differential analog inputs The TSA1203 is designed to deliver optimum performance when driven on differential inputs. An RF transformer is an efficient way of achieving this high performance. Figure 25 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. It determines the DC component of the analog signal. Being a high-impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Mini circuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog source. Each analog input can drive a 1.4 Vpp amplitude input signal, so the resulting differential amplitude is 2.8 Vpp. Figure 25. Differential input configuration with transformer Analog source 50Ω ADT1-1 1:1 VIN TSA1203 channels VINB I or Q 33pF INCM 330pF 10nF 470nF 17/30 Application information TSA1203 Figure 26. AC-coupled differential input 50Ω VIN 10nF 100kΩ 33pF common mode 50Ω INCM 100kΩ TSA1203 VINB 10nF Figure 26 represents the biasing of a differential input signal in an AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, which can be left internal, or fixed externally. Figure 27. DC-coupled 2 Vpp differential analog input analog AC+DC VREFP VIN DC TSA1203 VINB analog VREFM INCM DC VREFP-VREFM = 1 V 330pF 10nF 4.7µF VINCM = 0.5 V Figure 27 shows a DC-coupled configuration with forced VREFP and INCM to the 1V DC analog input while VREFM is connected to ground; the differential amplitude obtained is 2 Vpp. 8.4 Clock input The quality of your TSA1203 converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended. Further points to consider in your implementation are: 18/30 ● The duty cycle must be between 45% and 55%. ● The clock power supplies must be independent from the ADC output supplies to avoid digital noise modulation on the output. ● When powered-on, the circuit needs several clock periods to reach its normal operating conditions. Therefore, it is recommended to keep the circuit clocked to avoid random states before applying the supply voltages. TSA1203 8.5 Application information Power consumption optimization The internal architecture of the TSA1203 makes it possible to optimize power consumption according to the sampling frequency of the application. For this purpose, an external resistor is placed between IPOL and the analog ground pins. Therefore, the total dissipation can be optimized over the full sampling range (0.5 Msps to 40 Msps). The TSA1203 combines the highest performance with the lowest consumption at 40 Msps when Rpol is equal to 18 kΩ. This value is nevertheless dependent on the application and the environment. In the lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performance. Table 12 gives some values to illustrate this. Table 12. 8.6 Total power consumption optimization depending on Rpol value FS (Msps) 30 35 40 Rpol (kΩ) 38 28 18 Optimized power (mW) 145 180 215 Layout precautions To use the ADC circuits most efficiently at high frequencies, some precautions have to be taken for power supplies: ● The implementation of 4 proper separate supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is mandatory for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital output part is essential to prevent noise from coupling onto the input signal. The best compromise is to connect AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the AVCC, DVCC and VCCBI power supplies must be separate from the VCCBE power supply. ● Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. ● All inputs and outputs must be properly terminated with output termination resistors; thus, the amplifier load is resistive only and the stability of the amplifier is improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. ● To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, use buffers or latches close to the output pins. ● Choose component sizes as small as possible (SMD). 19/30 Application information 8.7 TSA1203 EVAL1203/BA evaluation board The EVAL1203/BA is a 4-layer board with high decoupling and grounding level. The schematic of the board is shown in Figure 30 and its top overlay view in Figure 29. The board has been characterized with a fully devoted ADC test bench as shown in Figure 28. All characterization measurements are made with: ■ SFSR=1 dB for static parameters, ■ SFSR=-1 dB for dynamic parameters. Figure 28. Analog to digital converter characterization bench HP8644 Sine Wave Generator Data Vin ADC evaluation board Logic Analyzer PC Clk Clk Note: HP8133 Pulse Generator HP8644 Sine Wave Generator The analog input signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. Figure 29. Evaluation board printed circuit 20/30 1 Q JQ1B InQB JI1B InIB 0 RQ19 50 RQ1 50 3 3 RSQ61 0 RI19 50 RI1 50 RSI6 1 0 0 NC RSQ9 4 RSQ8 T2-AT1-1WT 0 0 NC RSQ7 TQ2 6 0 2 RSQ5 ANALOGIC VCC GND JA AVCC 0 NC RSI9 4 RSI8 T2-AT1-1WT0 2 RSI7 + 0NM 0NM 0 NC TI2 6 RSI5 R22 R21 C42 47µF10µF C41 0NM R23 CI9 C4 470nF 10nF JQ2 VREFQ 330pF CQ8 NM 33pF CQ10 CQ9 CQ6 CQ1 330pF C2 NM 33pF 470nF 10nF C3 CI6 330pF CI8 CI1 470nF 10nF CI10 0NM R24 CI31 1K R2 330pF CI30 470nF 10nF 330pF CI12 AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND ADC DUAL12B 8-14bits ADC C36 47µF C23 10µF C22 470nF C21 10nF C20 330pF AVCC DVCC C32 47µF C31 10µF C13 470nF C11 10nF C10 330pF J27 2 1 DIGITAL JD CON2 C5 CLK 100nF J4 50 R3 DVCC SW1 CD3 330pF CD2 10nF 330pF CD1 470nF DVcc J9 10µF R5 50 J25 CKDATA C35 VCCB2 47µF C19 470nF C18 10nF C17 330pF C29 36 35 34 33 32 31 30 29 28 27 26 25 330pF 10nF C25 470nF C27 C28 VCCB2 CON2 VCCB2 2 1 J26 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11(MSB) VCCBE GNDBE 470nF 10nF 1 2 3 4 5 6 7 8 9 10 11 12 330pF CI11 C52 10nF C14 330pF C51 330pF C53 470nF C43 10µF 47µF STG719 IN S2 Vcc D GNDS1 U1 VCCB1 C44 AVCC R12 47K S5 SW-SPST C15 10nF C16 470nF 47K R11 S4 SW-SPST VCCB1 VCCB2 CQ13 CQ12 CQ11 470nF 10nF CI13 REFP REFM INCM CQ32 CQ31 CQ30 Raj1 47K 470nF 10nF CI32 JI2 VREFI 48 47 46 45 44 43 42 41 40 39 38 37 REFPI REFMI INCMI AVCC AVCC OEB CLKD VCCBI VCCBI GNDBE VCCBE D0(LSB) D1 REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI NM: non soudé + + REFP REFM INCM + 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 10nF 330pF C26 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 74LCX573 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE 470nF C39 47µF C37 C34 VCCB3 C33 C40 C38 330pF 10nF 470nF 74LCX573 VCCB2 GndB1 VccB1 GndB2 VccB2 GndB3 VccB3 VCCB1 J17 BUFPOW + VCC GND 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 Normal mode Test mode Switch S5 Open Short VCCB3 OEB Mode Normal mode High Impedance output mode Switch S4 Open Short analog input with transformer (default) single input differential input CLK D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RS5 RS6 RS7 RS8 RS9 C C C C C C C J6 CLK GND D11 GND D10 GND D9 GND D8 GND D7 GND D6 GND D5 GND D4 GND D3 GND D2 GND D1 GND D0 GND TSA1203 Application information Figure 30. TSA1203 evaluation board schematic + + 21/30 Application information Table 13. TSA1203 Printed circuit board — list of components Name Part Type RSQ6 0 RSQ7 0 RSQ8 0 RSI6 0 RSI7 0 RSI8 0 47 R3 47 R5 RQ19 47 47 RI1 RQ1 47 RI19 47 RSI9 0NC RSQ5 0NC RSQ9 0NC RSI5 0NC 0NC R24 0NC R23 0NC R21 0NC R22 1K R2 47K R12 47K R11 Raj1 200K C23 C41 C29 8.7.1 Footprint Name Part Type 805 CD2 10nF 805 C40 10nF 805 C39 10nF 805 CQ12 10nF 805 CQ9 10nF 805 C52 10nF 603 C18 10nF 603 C21 10nF 603 C4 10nF 603 C15 10nF 603 C27 10nF 603 C11 10nF 805 CI9 10nF 805 CI12 10nF 805 CI31 10nF 805 CQ31 10nF 805 CQ30 330pF 805 CI11 330pF 805 C51 330pF 805 C2 330pF 603 C17 330pF 603 CD3 330pF 603 C10 330pF CQ8 330pF VR5 CQ11 330pF trimmer 10µF 1210 CI8 330pF 10µF 1210 C14 330pF 10µF 1210 CI30 330pF 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 Name Part Type C26 330pF C20 330pF C33 330pF C25 330pF CI1 33pF CQ1 33pF C34 47µF C42 47µF C35 47µF C44 47µF C36 47µF C32 47µF C37 470nF CQ10 470nF C28 470nF CI10 470nF CQ32 470nF CQ13 470nF CI32 470nF C13 470nF C53 470nF C16 470nF C3 470nF C22 470nF CI13 470nF C38 470nF CD1 470nF C19 470nF Footprint Name Part Footprint Type 603 CQ6 NC 805 603 CI6 NC 805 603 U2 74LCX573 TSSOP20 603 U3 74LCX573 TSSOP20 603 U1 STG719 SOT23-6 603 JA ANALOGIC connector RB.1 J17 BUFPOW connector RB.1 J25 CKDATA SMA RB.1 J4 CLK SMA RB.1 J27 CON2 SIP2 RB.1 J26 CON2 SIP2 RB.1 JD DIGITAL connector 805 JI1 InI SMA 805 JI1B InIB SMA 805 JQ1 InQ SMA 805 JQ1B InQB SMA 805 SW1 SWITCH connector 805 S5 SW-SPST connector 805 S4 SW-SPST connector 805 TI2 T2-AT1-1WT ADT 805 TQ2 T2-AT1-1WT ADT 805 JI2 VREFI connector 805 JQ2 VREFQ connector 805 J6 32Pin IDC-32 805 connector 805 805 NC: non soldered 805 Evaluation board operating conditions Table 14. 22/30 Footprint Board connections for power supplies and other pins Board marking Connection Internal voltage (V) AV AVCC 2.5 AG AGND 0 RPI REFPI RMI REFMI CMI INCMI 0.46 <1 RPQ REFPQ 0.89 <1.4 RMQ REFMQ CMQ INCMQ DV DVCC 2.5 DG DGND 0 GB1 GNDBI 0 VB1 VCCBI 2.5 GB2 GNDBE 0 0.89 External voltage (V) <1.4 <0.4 <0.4 0.46 <1 TSA1203 Application information Table 14. Board connections for power supplies and other pins (continued) Board marking Connection Internal voltage (V) External voltage (V) VB2 VCCBE 2.5/3.3 GB3 GNDB3 0 VB3 VCCB3 2.5 Caution: Do not use the VB3 power supply (5 V) dedicated to the 74LCX573 external buffers to supply the VB2 of the TSA1203 which cannot exceed 3.3 V. 8.7.2 Consumption adjustment Before beginning characterization tests, make sure to adjust the Rpol (Raj1), and therefore Ipol value, according to your sampling frequency. 8.7.3 Single and differential inputs The test board can be driven on a single analog input, or on differential inputs. With a single analog input, you must use the ADT1-1WT transformer to generate a differential signal. In this configuration, the resistors RSI6, RSI7, RSI8 for channel I (respectively RSQ6, RSQ7, RSQ8 for channel Q) are connected as short-circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9 for channel Q) are open circuits. Alternatively, you can use the JI1 and JI1B differential inputs. In this case, the resistances RSI5, RSI9 for channel I (respectively RSQ5, RSQ9 for channel Q) are connected as shortcircuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for channel Q) are open circuits. 8.7.4 Mode selection In order to select the channel you want to evaluate, you must set a jumper on the board in the relevant position for the SELECT pin (see Figure 31). The channels selected depend on the position of the jumper: ● With the jumper connected to the upper connectors, channel I at the output is selected. ● With the jumper connected horizontally, channel Q at the output is selected. ● With the jumper connected to the lower connectors, both channels are selected, relative to the clock edge. Figure 31. Mode selection SELECT I channel SELECT Q channel I/Q channels CLK DGND DVCC 23/30 Practical application examples TSA1203 9 Practical application examples 9.1 Digital interface applications The wide external buffer power supply range of the TSA1203 makes it a perfect choice for plugging into 2.5 V or 3.3 V low voltage DSPs or digital interfaces. 9.2 Medical imaging applications Driven by the increasing demand for applications requiring either portability or a high degree of parallelism (or both), this product satisfies the requirements of medical imaging and telecom infrastructures. The typical system diagram in Figure 32, shows how a narrow input beam of acoustic energy is sent into a living body via the transducer, and how the energy reflected back is analyzed. Figure 32. Medical imaging application HV TX amps TX beam former Mux and T/R switches ADC RX beam former TGC amplifier Processing and display The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can reach up to 512 channels. The TX beam former, amplified by the HV TX amps, delivers up to 100 V amplitude excitation pulses with phase and amplitude shifts. The mux and T/R switch is a two way input signal transmitter/ output receiver. To compensate for skin and tissues attenuation effects, the time gain compensation (TGC) amplifier is an exponential amplifier that amplifies low voltage signals to the ADC input range. A differential output structure with low noise and very high linearity are essential factors. These applications need high speed, low power and high performance ADCs. 10-12 bit resolution is necessary to lower the quantification noise. As multiple channels are used, a dual converter is a must for room saving issues. The input signal is in the range of 2 to 20 MHz (mainly 2 to 7 MHz) and the application uses mostly a 4 over-sampling ratio for spurious free dynamic range (SFDR) optimization. The next RX beam former and processing blocks enable the analysis of the output channels versus the input beam. 24/30 TSA1203 10 Definitions of specified parameters Definitions of specified parameters Static parameters Static measurements are performed using the histograms method on a 2 MHz input signal, sampled at 50 Msps, which is high enough to fully characterize the test frequency response. The input level is +1 dBFS to saturate the signal. Differential non linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral non linearity (INL) An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. The INL is the deviation from this ideal line for each transition. Dynamic parameters Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies sampled at 40 Msps. The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter. Spurious free dynamic range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total harmonic distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to noise ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/ 2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to noise and distortion ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula: SINAD= 6.02 × ENOB + 1.76 dB. When the applied signal is not full scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS) 25/30 Definitions of specified parameters TSA1203 SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog input bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 dB. Higher values can be achieved with smaller input levels. Effective resolution bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. 26/30 TSA1203 11 Package mechanical data Package mechanical data In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com. 11.1 TQFP48 package TQFP48 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 1.6 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.055 B 0.17 0.22 0.27 0.007 0.009 C 0.09 0.20 0.0035 0.006 D 9.00 0.354 7.00 0.276 D3 5.50 0.216 e 0.50 0.020 E 9.00 0.354 E1 7.00 0.276 L 5.50 0.45 L1 K 0.60 3.5˚ 0.011 0.216 0.75 0.018 1.00 0˚ 0.057 0.0079 D1 E3 MAX. 0.063 0.024 0.030 0.039 7˚ 0˚ 3.5˚ 7˚ 0110596/C 27/30 Ordering information 12 Ordering information Part number Temperature range Package Packing Marking TSA1203IFT-E -40° C to +85° C TQFP48 Tape & reel SA1203I TSA1203IF -40° C to +85° C TQFP48 Tray SA1203I EVAL1203/BA 28/30 TSA1203 Evaluation board TSA1203 13 Revision history Revision history Date Revision Changes 1-Feb-2003 1 Initial release. 2-Jan-2006 2 Update of dynamic performance measurements in Table 2 on page 6. 26-Sep-2006 3 Editorial updates. Reorganized document structure. No technical changes. 12-Dec-2006 4 Pin 42 renamed to CLKD. 29/30 TSA1203 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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